A Seven-Level Inverter Topology for Induction Motor Drive Using Two-Level Inverters and Floating Capacitor Fed H-Bridges

A multilevel inverter topology for seven-level space vector generation is proposed in this paper. In this topology, the seven-level structure is realized using two conventional two-level inverters and six capacitor-fed H-bridge cells. It needs only two isolated dc-voltage sources of voltage rating V(dc)/2 where V(dc) is the dc voltage magnitude required by the conventional neutral point clamped (NPC) seven-level topology. The proposed topology is capable of maintaining the H-bridge capacitor voltages at the required level of V(dc)/6 under all operating conditions, covering the entire linear modulation and overmodulation regions, by making use of the switching state redundancies. In the event of any switch failure in H-bridges, this inverter can operate in three-level mode, a feature that enhances the reliability of the drive system. The two-level inverters, which operate at a higher voltage level of V(dc)/2, switch less compared to the H-bridges, which operate at a lower voltage level of V(dc)/6, resulting in switching loss reduction. The experimental verification of the proposed topology is carried out for the entire modulation range, under steady state as well as transient conditions.

Subnatural linewidth in a strongly-driven degenerate two-level system

We observe linewidths below the natural linewidth for a probe laser on a degenerate two-level F -> F' transition, when the same transition is driven by a strong control laser. We take advantage of the fact that each level of the transition is made of multiple magnetic sublevels, and use the phenomenon of electromagnetically induced transparency (EIT) or absorption ( EIA) in multilevel systems. Optical pumping by the control laser redistributes the population so that only a few sublevels contribute to the probe absorption, an explanation which is verified by a density-matrix analysis of the relevant sublevels. We observe more than a factor of 3 reduction in linewidth in the D(2) line of Rb in room-temperature vapor. Such subnatural features vastly increase the scope of applications of EIT, such as high-resolution spectroscopy and tighter locking of lasers to atomic transitions, since it is not always possible to find a suitable third level. (C) 2011 Elsevier B.V. All rights reserved.

Influence of the highest occupied molecular orbital energy level of the donor material on the effectiveness of the anode buffer layer in organic solar cells

Efficiency of organic photovoltaic cells based on organic electron donor/organic electron acceptor junctions can be strongly improved when the transparent conductive Anode is coated with a Buffer Layer (ABL). Here, the effects of a metal (gold) or oxide (molybdenum oxide) ABL are reported, as a function of the Highest Occupied Molecular Orbital (HOMO) of different electron donors. The results indicate that a good matching between the work function of the anode and the highest occupied molecular orbital of the donor material is the major factor limiting the hole transfer efficiency. Indeed, gold is efficient as ABL only when the HOMO of the organic donor is close to its work function Phi(Au). Therefore we show that the MoO(3) oxide has a wider field of application as ABL than gold. (C) 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

Bounds on Defect Level and Fault Coverage in Linear Analog Circuit Testing

Transfer function coefficients (TFC) are widely used to test linear analog circuits for parametric and catastrophic faults. This paper presents closed form expressions for an upper bound on the defect level (DL) and a lower bound on fault coverage (FC) achievable in TFC based test method. The computed bounds have been tested and validated on several benchmark circuits. Further, application of these bounds to scalable RC ladder networks reveal a number of interesting characteristics. The approach adopted here is general and can be extended to find bounds of DL and FC of other parametric test methods for linear and non-linear circuits.

An improved sapce phasor based current hysteresis controller with reduced switching frequency variations using variable parabolic bands

A current error space phasor based simple hysteresis controller is proposed in this paper to control the switching frequency variation in two-level pulsewidth-modulation (PWM) inverter-fed induction motor (IM) drives. A parabolic boundary for the current error space phasor is suggested for the first time to obtain the switching frequency spectrum for output voltage with hysteresis controller similar to the constant switching frequency voltage-controlled space vector PWM-based IM drive. A novel concept of online variation of this parabolic boundary, which depends on the operating speed of motor, is presented. A generalized technique that determines the set of unique parabolic boundaries for a two-level inverter feeding any given induction motor is described. The sector change logic is self-adaptive and is capable of taking the drive up to the six-step mode if needed. Steady-state and transient performance of proposed controller is experimentally verified on a 3.7-kW IM drive in the entire speed range. Close resemblance of the simulation and experimental results is shown.

A Multilevel inverter structure with cascaded two level and three level inverters for IM drive with CMV elimination and DC link capacitor voltage balancing

Common mode voltage (CMV) variations in PWM inverter-fed drives generate unwanted shaft and bearing current resulting in early motor failure. Multilevel inverters reduce this problem to some extent, with higher number of levels. But the complexity of the power circuit increases with an increase in the number of inverter voltage levels. In this paper a five-level inverter structure is proposed for open-end winding induction motor (IM) drives, by cascading only two conventional two-level and three-level inverters, with the elimination of the common mode voltage over the entire modulation range. The DC link power supply requirement is also optimized by means of DC link capacitor voltage balancing, with PWM control, using only inverter switching state redundancies. The proposed power circuit gives a simple power bus structure.

A five level inverter scheme with common mode volatge elimination by cascading conventional two level and three level NPC inverters for an induction motor drive

Common-mode voltage generated by the PWM inverter causes shaft voltage, bearing current and ground leakage current in induction motor drive system, resulting in an early motor failure. This paper presents a common-mode elimination scheme for a five-level inverter with reduced power circuit complexity. The proposed scheme is realised by cascading conventional two-level and conventional NPC three-level inverters in conjunction with an open-end winding three-phase induction motor drive and the common-mode voltage (CMV) elimination is achieved by using only switching states that result in zero CMV, for the entire modulation range.

Limits of Data Level Parallelism

Abstract—A new breed of processors like the Cell Broadband Engine, the Imagine stream processor and the various GPU processors emphasize data-level parallelism (DLP) and threadlevel parallelism (TLP) as opposed to traditional instructionlevel parallelism (ILP). This allows them to achieve order-ofmagnitude improvements over conventional superscalar processors for many workloads. However, it is unclear as to how much parallelism of these types exists in current programs. Most earlier studies have largely concentrated on the amount of ILP in a program, without differentiating DLP or TLP. In this study, we investigate the extent of data-level parallelism available in programs in the MediaBench suite. By packing instructions in a SIMD fashion, we observe reductions of up to 91 % (84 % on average) in the number of dynamic instructions, indicating a very high degree of DLP in several applications. I.

Regional Flood Frequency Analysis using Two-level Clustering Approach

Clustering techniques are used in regional flood frequency analysis (RFFA) to partition watersheds into natural groups or regions with similar hydrologic responses. The linear Kohonen's self‐organizing feature map (SOFM) has been applied as a clustering technique for RFFA in several recent studies. However, it is seldom possible to interpret clusters from the output of an SOFM, irrespective of its size and dimensionality. In this study, we demonstrate that SOFMs may, however, serve as a useful precursor to clustering algorithms. We present a two‐level. SOFM‐based clustering approach to form regions for FFA. In the first level, the SOFM is used to form a two‐dimensional feature map. In the second level, the output nodes of SOFM are clustered using Fuzzy c‐means algorithm to form regions. The optimal number of regions is based on fuzzy cluster validation measures. Effectiveness of the proposed approach in forming homogeneous regions for FFA is illustrated through application to data from watersheds in Indiana, USA. Results show that the performance of the proposed approach to form regions is better than that based on classical SOFM.

Two-level Mapping Based Cache Index Selection for Packet Forwarding Engines

Packet forwarding is a memory-intensive application requiring multiple accesses through a trie structure. The efficiency of a cache for this application critically depends on the placement function to reduce conflict misses. Traditional placement functions use a one-level mapping that naively partitions trie-nodes into cache sets. However, as a significant percentage of trie nodes are not useful, these schemes suffer from a non-uniform distribution of useful nodes to sets. This in turn results in increased conflict misses. Newer organizations such as variable associativity caches achieve flexibility in placement at the expense of increased hit-latency. This makes them unsuitable for L1 caches.We propose a novel two-level mapping framework that retains the hit-latency of one-level mapping yet incurs fewer conflict misses. This is achieved by introducing a secondlevel mapping which reorganizes the nodes in the naive initial partitions into refined partitions with near-uniform distribution of nodes. Further as this remapping is accomplished by simply adapting the index bits to a given routing table the hit-latency is not affected. We propose three new schemes which result in up to 16% reduction in the number of misses and 13% speedup in memory access time. In comparison, an XOR-based placement scheme known to perform extremely well for general purpose architectures, can obtain up to 2% speedup in memory access time.