Radio link quality estimation in wireless sensor networks: a survey

Radio link quality estimation in Wireless Sensor Networks (WSNs) has a fundamental impact on the network performance and also affects the design of higher-layer protocols. Therefore, for about a decade, it has been attracting a vast array of research works. Reported works on link quality estimation are typically based on different assumptions, consider different scenarios, and provide radically different (and sometimes contradictory) results. This article provides a comprehensive survey on related literature, covering the characteristics of low-power links, the fundamental concepts of link quality estimation in WSNs, a taxonomy of existing link quality estimators, and their performance analysis. To the best of our knowledge, this is the first survey tackling in detail link quality estimation in WSNs. We believe our efforts will serve as a reference to orient researchers and system designers in this area.

Action, reaction and protest by publishers in 1960s Portugal: books and other publications in the Catholic opposition

The authoritarian regime of the Portuguese Estado Novo (New State), the longest dictatorship in twentieth-century Western Europe, suffered one of its most serious threats during the late 1950s and the whole of the following decade. An array of events and dynamics of opposition to the regime and condemnation of the political and social situation in Portugal appeared at that time. One of the core groups that displayed their dissidence in the 1960s, with the awakening of their critical conscience, originated in Catholic sectors that rallied the laity and the clergy to express their disagreement or even break with the government of Salazar (and, later, Marcelo Caetano). This article aims to establish the role of print culture and, in particular, publishing in the opposition’s mobilisation of Catholics who criticised the Estado Novo. It will also closely examine the contribution of certain publishers to the formulation of the terms of this mobilisation, in publishing new authors and topics and creating new printed forums (e.g. periodicals) for discussion and reflection. The most detailed case will be that of the publishing house Livraria Moraes Editora, under the command of the publisher António Alçada Baptista.

Unified transform architecture for AVC, AVS, VC-1 and HEVC high-performance codecs

A unified architecture for fast and efficient computation of the set of two-dimensional (2-D) transforms adopted by the most recent state-of-the-art digital video standards is presented in this paper. Contrasting to other designs with similar functionality, the presented architecture is supported on a scalable, modular and completely configurable processing structure. This flexible structure not only allows to easily reconfigure the architecture to support different transform kernels, but it also permits its resizing to efficiently support transforms of different orders (e. g. order-4, order-8, order-16 and order-32). Consequently, not only is it highly suitable to realize high-performance multi-standard transform cores, but it also offers highly efficient implementations of specialized processing structures addressing only a reduced subset of transforms that are used by a specific video standard. The experimental results that were obtained by prototyping several configurations of this processing structure in a Xilinx Virtex-7 FPGA show the superior performance and hardware efficiency levels provided by the proposed unified architecture for the implementation of transform cores for the Advanced Video Coding (AVC), Audio Video coding Standard (AVS), VC-1 and High Efficiency Video Coding (HEVC) standards. In addition, such results also demonstrate the ability of this processing structure to realize multi-standard transform cores supporting all the standards mentioned above and that are capable of processing the 8k Ultra High Definition Television (UHDTV) video format (7,680 x 4,320 at 30 fps) in real time.

Multifunctional controller architecture for sold-state marx modulator based on FPGA

This paper proposes a multifunctional architecture to implement field-programmable gate array (FPGA) controllers for power converters and presents a prototype for a pulsed power generator based on a solid-state Marx topology. The massively parallel nature of reconfigurable hardware platforms provides very high processing power and fast response times allowing the implementation of many subsystems in the same device. The prototype includes the controller, a failure detection system, an interface with a safety/emergency subsystem, a graphical user interface, and a virtual oscilloscope to visualize the generated pulse waveforms, using a single FPGA. The proposed architecture employs a modular design that can be easily adapted to other power converter topologies.

Incidence and risk factors for intimate partner violence during the postpartum period

OBJECTIVE To estimate the incidence and identify risk factors for intimate partner violence during postpartum.METHODS This prospective cohort study was conducted with women, aged between 18-49 years, enrolled in the Brazilian Family Health Strategy in Recife, Northeastern Brazil, between 2005 and 2006. Of the 1.057 women interviewed during pregnancy and postpartum, 539 women, who did not report violence before or during pregnancy, were evaluated. A theoretical-conceptual framework was built with three levels of factors hierarchically ordered: women’s and partners’ sociodemografic and behavioral characteristics, and relationship dynamics. Incidence and risk factors of intimate partner violence were estimated by Poisson Regression.RESULTS The incidence of violence during postpartum was 9.3% (95%CI 7.0;12.0). Isolated psychological violence was the most common (4.3%; 95%CI 2.8;6.4). The overlapping of psychological with physical violence occurred at 3.3% (95%CI 2.0;5.3) and with physical and/or sexual in almost 2.0% (95%CI 0.8;3.0) of cases. The risk of partner violence during postpartum was increased for women with a low level of education (RR = 2.6; 95%CI 1.3;5.4), without own income (RR = 1.7; 95%CI 1.0;2.9) and those who perpetrated physical violence against their partner without being assaulted first (RR = 2.0; 95%CI 1.2;3.4), had a very controlling partner (RR = 2.5; 95%CI 1.1;5.8), and had frequent fights with their partner (RR = 1.7; 95%CI 1.0;2.9).CONCLUSIONS The high incidence of intimate partner violence during postpartum and its association with aspects of the relationship’s quality between the couple, demonstrated the need for public policies that promote conflict mediation and enable forms of empowerment for women to address the cycle of violence.

A Review of antenas for indoor positioning systems

This paper provides a review of antennas applied for indoor positioning or localization systems. The desired requirements of those antennas when integrated in anchor nodes (reference nodes) are discussed, according to different localization techniques and their performance. The described antennas will be subdivided into the following sections according to the nature of measurements: received signal strength (RSS), time of flight (ToF), and direction of arrival (DoA). This paper intends to provide a useful guide for antenna designers who are interested in developing suitable antennas for indoor localization systems.

Peers' evaluation of a reconfigurable IEEE1451.0-compliant and FPGA-based weblab

It is already more than 10 years that weblabs are seen as important resources to provide the experimental work required in engineering education. Several weblabs have been applied in engineering courses, but there are still unsolved problems related to the development of their infrastructures. For solving some of those problems, it was implemented a weblab with a reconfigurable infrastructure compliant with the IEEE1451.0 Std. and supported by Field Programmable Gate Array (FPGA) technology. This paper presents the referred weblab, and provides and analyses a set of researchers' opinions about the implemented infrastructure, and the adopted methodology for the conduction of real experiments.

Reconfigurable IEEE1451-FPGA based weblab infrastructure

Weblabs are spreading their influence in Science and Engineering (S&E) courses providing a way to remotely conduct real experiments. Typically, they are implemented by different architectures and infrastructures supported by Instruments and Modules (I&Ms) able to be remotely controlled and observed. Besides the inexistence of a standard solution for implementing weblabs, their reconfiguration is limited to a setup procedure that enables interconnecting a set of preselected I&Ms into an Experiment Under Test (EUT). Moreover, those I&Ms are not able to be replicated or shared by different weblab infrastructures, since they are usually based on hardware platforms. Thus, to overcome these limitations, this paper proposes a standard solution that uses I&Ms embedded into Field-Programmable Gate Array (FPGAs) devices. It is presented an architecture based on the IEEE1451.0 Std. supported by a FPGA-based weblab infrastructure able to be remotely reconfigured with I&Ms, described through standard Hardware Description Language (HDL) files, using a Reconfiguration Tool (RecTool).

Determinação do teor de compostos aromáticos policíclicos de óleos minerais isolantes para transformadores

Mestrado em Engenharia Química - Ramo Optimização Energética na Indústria Química

Sistema didáctico de baixo custo com FPGA de alta densidade

O uso das Field-Programmable Gate Array tem crescido de forma exponencial. Com isto dito, é importante que os engenheiros electrotécnicos estejam familiarizados com este tipo de tecnologia. Foi com o intuído de passar estas valências para os alunos do ISEP, que surgiu a ideia de criar um sistema didáctico, que permitisse ao alunos aprender a trabalhar com estes dispositivos. O seguinte trabalho iniciou-se com base num estudo das características destes dispositivos e das suas potencialidades, seguido de uma avaliação do que o mercado tem para oferecer. Posteriormente, com base em toda a informação reunida, foi definida a arquitectura do sistema, que levou selecção de dispositivos a incluir no mesmo, e culminando na concepção do esquema eléctrico do sistema e da placa de circuito impresso correspondente ao protótipo do mesmo. As principais directivas para este projecto foram o uso de uma FPGA de alta densidade e a concepção da ferramenta com o custo de projecto o mais reduzido possível.

Real time manufacturing systems simulator

A área da simulação computacional teve um rápido crescimento desde o seu apareciment, sendo actualmente uma das ciências de gestão e de investigação operacional mais utilizadas. O seu princípio baseia-se na replicação da operação de processos ou sistemas ao longo de períodos de tempo, tornando-se assim uma metodologia indispensável para a resolução de variados problemas do mundo real, independentemente da sua complexidade. Das inúmeras áreas de aplicação, nos mais diversos campos, a que mais se destaca é a utilização em sistemas de produção, onde o leque de aplicações disponível é muito vasto. A sua aplicação tem vindo a ser utilizada para solucionar problemas em sistemas de produção, uma vez que permite às empresas ajustar e planear de uma maneira rápida, eficaz e ponderada as suas operações e os seus sistemas, permitindo assim uma rápida adaptação das mesmas às constantes mudanças das necessidades da economia global. As aplicações e packages de simulação têm seguindo as tendências tecnológicas pelo que é notório o recurso a tecnologias orientadas a objectos para o desenvolvimento das mesmas. Este estudo baseou-se, numa primeira fase, na recolha de informação de suporte aos conceitos de modelação e simulação, bem como a respectiva aplicação a sistemas de produção em tempo real. Posteriormente centralizou-se no desenvolvimento de um protótipo de uma aplicação de simulação de ambientes de fabrico em tempo real. O desenvolvimento desta ferramenta teve em vista eventuais fins pedagógicos e uma utilização a nível académico, sendo esta capaz de simular um modelo de um sistema de produção, estando também dotada de animação. Sem deixar de parte a possibilidade de integração de outros módulos ou, até mesmo, em outras plataformas, houve ainda a preocupação acrescida de que a sua implementação recorresse a metodologias de desenvolvimento orientadas a objectos.

O trabalho individual e o trabalho de grupo no processo de ensino-aprendizagem do estudo do meio no 1º Ciclo

Relatório Final apresentado à Escola Superior de Educação de Lisboa para obtenção de grau de mestre em Ensino do 1º e 2º ciclo do Ensino Básico

A self-healing real-time system based on run-time self-reconfiguration

The new generations of SRAM-based FPGA (field programmable gate array) devices are the preferred choice for the implementation of reconfigurable computing platforms intended to accelerate processing in real-time systems. However, FPGA's vulnerability to hard and soft errors is a major weakness to robust configurable system design. In this paper, a novel built-in self-healing (BISH) methodology, based on run-time self-reconfiguration, is proposed. A soft microprocessor core implemented in the FPGA is responsible for the management and execution of all the BISH procedures. Fault detection and diagnosis is followed by repairing actions, taking advantage of the dynamic reconfiguration features offered by new FPGA families. Meanwhile, modular redundancy assures that the system still works correctly

JPEG decoder implementation on FPGA using dynamic partial reconfiguration

Trabalho Final de Mestrado para obtenção do grau de Mestre em Engenharia de Electrónica e telecomunicações

Projeto e implementação de um pré-regulador de fator de potência com controlo digital

Hoje em dia as fontes de alimentação possuem correção do fator de potência, devido às diversas normas regulamentares existentes, que introduziram grandes restrições no que respeita à distorção harmónica (THD) e fator de potência (FP). Este trabalho trata da análise, desenvolvimento e implementação de um Pré-Regulador de fator de potência com controlo digital. O controlo digital de conversores com recurso a processamento digital de sinal tem vindo a ser ao longo dos últimos anos, objeto de investigação e desenvolvimento, estando constantemente a surgirem modificações nas topologias existentes. Esta dissertação tem como objetivo estudar e implementar um Pré-Regulador Retificador Boost e o respetivo controlo digital. O controlo do conversor é feito através da técnica dos valores médios instantâneos da corrente de entrada, desenvolvido através da linguagem de descrição de hardware VHDL (VHSIC HDL – Very High Speed Integrated Circuit Hardware Description Language) e implementado num dispositivo FPGA (Field Programmable Gate Array) Spartan-3E. Neste trabalho são apresentadas análises matemáticas, para a obtenção das funções de transferência pertinentes ao projeto dos controladores. Para efetuar este controlo é necessário adquirir os sinais da corrente de entrada, tensão de entrada e tensão de saída. O sinal resultante do módulo de controlo é um sinal de PWM com valor de fator de ciclo variável ao longo do tempo. O projeto é simulado e validado através da plataforma MatLab/Simulink e PSIM, onde são apresentados resultados para o regime permanente e para transitórios da carga e da tensão de alimentação. Finalmente, o Pré-Regulador Retificador Boost controlado de forma digital é implementado em laboratório. Os resultados experimentais são apresentados para validar a metodologia e o projeto desenvolvidos.