A Scalable Low Power Issue Queue for Large Instruction Window Processors

Large instruction windows and issue queues are key to exploiting greater instruction level parallelism in out-of-order superscalar processors. However, the cycle time and energy consumption of conventional large monolithic issue queues are high. Previous efforts to reduce cycle time segment the issue queue and pipeline wakeup. Unfortunately, this results in significant IPC loss. Other proposals which address energy efficiency issues by avoiding only the unnecessary tag-comparisons do not reduce broadcasts. These schemes also increase the issue latency.To address both these issues comprehensively, we propose the Scalable Lowpower Issue Queue (SLIQ). SLIQ augments a pipelined issue queue with direct indexing to mitigate the problem of delayed wakeups while reducing the cycle time. Also, the SLIQ design naturally leads to significant energy savings by reducing both the number of tag broadcasts and comparisons required.A 2 segment SLIQ incurs an average IPC loss of 0.2% over the entire SPEC CPU2000 suite, while achieving a 25.2% reduction in issue latency when compared to a monolithic 128-entry issue queue for an 8-wide superscalar processor. An 8 segment SLIQ improves scalability by reducing the issue latency by 38.3% while incurring an IPC loss of only 2.3%. Further, the 8 segment SLIQ significantly reduces the energy consumption and energy-delay product by 48.3% and 67.4% respectively on average.

Two-level Mapping Based Cache Index Selection for Packet Forwarding Engines

Packet forwarding is a memory-intensive application requiring multiple accesses through a trie structure. The efficiency of a cache for this application critically depends on the placement function to reduce conflict misses. Traditional placement functions use a one-level mapping that naively partitions trie-nodes into cache sets. However, as a significant percentage of trie nodes are not useful, these schemes suffer from a non-uniform distribution of useful nodes to sets. This in turn results in increased conflict misses. Newer organizations such as variable associativity caches achieve flexibility in placement at the expense of increased hit-latency. This makes them unsuitable for L1 caches.We propose a novel two-level mapping framework that retains the hit-latency of one-level mapping yet incurs fewer conflict misses. This is achieved by introducing a secondlevel mapping which reorganizes the nodes in the naive initial partitions into refined partitions with near-uniform distribution of nodes. Further as this remapping is accomplished by simply adapting the index bits to a given routing table the hit-latency is not affected. We propose three new schemes which result in up to 16% reduction in the number of misses and 13% speedup in memory access time. In comparison, an XOR-based placement scheme known to perform extremely well for general purpose architectures, can obtain up to 2% speedup in memory access time.

Novel Switching Sequences for a Space-Vector-Modulated Three-Level Inverter

A three-level inverter produces six active vectors, each of normalized magnitudes 1, 0.866, and 0.5, besides a zero vector. The vectors of relative length 0.5 are termed pivot vectors.The three nearest voltage vectors are usually used to synthesize the reference vector. In most continuous pulsewidth-modulation(PWM) schemes, the switching sequence begins from a pivot vector and ends with the same pivot vector. Thus, the pivot vector is applied twice in a subcycle or half-carrier cycle. This paper proposes and investigates alternative switching sequences, which use the pivot vector only once but employ one of the other two vectors twice within the subcycle. The total harmonic distortion(THD) in the fundamental line current pertaining to these novel sequences is studied theoretically as well as experimentally over the whole range of modulation. Compared with centered space vector PWM, two of the proposed sequences lead to reduced THD at high modulation indices at a given average switching frequency.

H-DBUG: A High-level Debugging Framework for Protocol Verification using Assertions

The success of an ABV IP depends highly on the associated debugging environment. An efficient debugging environment helps the user to find out the exact location of the failure. Moreover, it provides information to the user in a refined detail of abstraction and permit adequate interaction. It has also been realized that adequate visualization support helps in tracking the behavioral aspects of the Design Under Test (DUT). Currently, the debugging tools provide information in the signal level and do not provide any information about the high-level behavior of the DUT. We present a debugging framework that takes the design specification, assertions and the user intent in a simple format and provides detailed information by processing the design trace on-line, or off-line. We also present a visualization framework to ease the debugging procedure. We have experimented with industrial standard on-chip bus protocols that ensure that this utility can be incorporated successfully in the present functional verification flow.

Performance analysis of subband-level channel quality indicator feedback scheme of LTE

Frequency-domain scheduling and rate adaptation enable next generation wireless cellular systems such as Long Term Evolution (LTE) to achieve significantly higher downlink throughput. LTE assigns subcarriers in chunks, called physical resource blocks (PRBs), to users to reduce control signaling overhead. To reduce the enormous feedback overhead, the channel quality indicator (CQI) report that is used to feed back channel state information is averaged over a subband, which, in turn, is a group of multiple PRBs. In this paper, we develop closed-form expressions for the throughput achieved by the subband-level CQI feedback mechanism of LTE. We show that the coarse frequency resolution of the CQI incurs a significant loss in throughput and limits the multi-user gains achievable by the system. We then show that the performance can be improved by means of an offset mechanism that effectively makes the users more conservative in reporting their CQI.

A hybrid nine-level inverter for IM drive

This paper proposes a new hybrid nine-level inverter topology for IM drive. The nine-level structure is realized by using two three-phase two-level inverters fed by isolated DC voltage sources and six H-bridges fed by capacitors. The number of switches required in this topology is only 36 where as the conventional nine-level topologies require 48 switches. The voltages across the capacitors, feeding the H-bridges that operate at asymmetric voltages, are effectively balanced by making use of the switching state redundancies. In this topology, the requirement of DC link voltage is only half of the maximum magnitude of the voltage space vector. As the two-level inverters are powered by isolated voltage sources, the circulation of triplen harmonic current in the motor winding is prevented. The proposed drive system is capable of functioning in three-level mode in case of any switch failure in H-bridges. The performance of the proposed topology in the entire modulation range is verified by simulation study and experiment.

A deep‐level spectroscopic technique for determining capture cross‐section activation energy of Si‐related DX centers in AlxGa1-xAs

A deep‐level transient spectroscopy (DLTS) technique is reported for determining the capture cross‐section activation energy directly. Conventionally, the capture activation energy is obtained from the temperature dependence of the capture cross section. Capture cross‐section measurement is often very doubtful due to many intrinsic errors and is more critical for nonexponential capture kinetics. The essence of this technique is to use an emission pulse to allow the defects to emit electrons and the transient signal from capture process due to a large capture barrier was analyzed, in contrast with the emission signal in conventional DLTS. This technique has been applied for determining the capture barrier for silicon‐related DX centers in AlxGa1−xAs for different AlAs mole fractions.

Influence of planning and governance on the level of urban services

A theoretical framework to analyse the interaction of planning and governance on the extent of outgrowth and level of services is proposed. An indicator framework for quantifying sprawl is also proposed and the same is operationalised for Bangalore. The indicators comprise spatial metrics (derived from temporal satellite remote sensing data) and other metrics obtained from a house-hold survey. The interaction of different indicators with respect to the core city and the outgrowth is determined by multi-dimensional scaling. The analysis reveals the underlying similarities (and dissimilarities) that relate with the different governance structures that prevail here. The paper concludes outlining the challenges in addressing urban sprawl while ensuring adequate level of services that planning and governance have to ensure towards achieving sustainable urbanisation.

Mathematical Model of Viral Kinetics In Vitro Estimates the Number of E2-CD81 Complexes Necessary for Hepatitis C Virus Entry

Interaction between the hepatitis C virus (HCV) envelope protein E2 and the host receptor CD81 is essential for HCV entry into target cells. The number of E2-CD81 complexes necessary for HCV entry has remained difficult to estimate experimentally. Using the recently developed cell culture systems that allow persistent HCV infection in vitro, the dependence of HCV entry and kinetics on CD81 expression has been measured. We reasoned that analysis of the latter experiments using a mathematical model of viral kinetics may yield estimates of the number of E2-CD81 complexes necessary for HCV entry. Here, we constructed a mathematical model of HCV viral kinetics in vitro, in which we accounted explicitly for the dependence of HCV entry on CD81 expression. Model predictions of viral kinetics are in quantitative agreement with experimental observations. Specifically, our model predicts triphasic viral kinetics in vitro, where the first phase is characterized by cell proliferation, the second by the infection of susceptible cells and the third by the growth of cells refractory to infection. By fitting model predictions to the above data, we were able to estimate the threshold number of E2-CD81 complexes necessary for HCV entry into human hepatoma-derived cells. We found that depending on the E2-CD81 binding affinity, between 1 and 13 E2-CD81 complexes are necessary for HCV entry. With this estimate, our model captured data from independent experiments that employed different HCV clones and cells with distinct CD81 expression levels, indicating that the estimate is robust. Our study thus quantifies the molecular requirements of HCV entry and suggests guidelines for intervention strategies that target the E2-CD81 interaction. Further, our model presents a framework for quantitative analyses of cell culture studies now extensively employed to investigate HCV infection.

Hypersonic wave drag reduction in re-entry capsules using concentrated energy deposition

Experiments are carried out in a shock tunnel at a nominal Mach number of 5.75 in order to study the effect of concentrated energy deposition on the drag force experienced by a 120° blunt cone. Electrical energy was deposited along the stagnation streamline of the model using a high voltage DC discharge circuit (1.5 – 3.5KW) and the drag force was measured by a single component accelerometer balance. Numerical simulations were also carried complimenting the experiments. These simulations showed a substantial drag reduction (20% ~ 65%) whereas the experiments show no appreciable reduction in drag

Tar characterisation in new generation agro-residue gasifiers - Cyclone and downdraft open top twin air entry systems

This paper deals with the characterisation of tar from two configurations of bioresidue thermochemical conversion reactors designed for producer gas based power generation systems. The pulverised fuel reactor is a cyclone system (R1) and the solid bioresidue reactor (denoted R2) is an open top twin air entry system both at 75-90 kg/h capacity (to generate electricity similar to 100 kVA). The reactor, R2, has undergone rigorous test in a major Indo-Swiss programme for the tar quantity at various conditions. The former is a recent technology development. Tars collected from these systems by a standard tar collection apparatus at the laboratory at Indian Institute of Science have been analysed at the Royal Institute of Technology (KTH), Sweden. The results of these analyses show that these thermochemical conversion reactors behave differently from the earlier reactors reported in literature in so far as tar generation is concerned. The extent of tar in hot gas is about 700-800 ppm for R1 and 70-100 ppm for R2. The amounts of the major compounds - naphthalene and phenol-are much lower that what is generally understood to happen in the gasifiers in Europe. It is suggested that the longer residence times at high temperatures allowed for in these reactors is responsible for this behavior. It is concluded the new generation reactor concepts extensively tried out at lower power levels hold promise for high power atmospheric gasification systems for woody as well as pulverisable bioresidues.

Space vector based bus clamped PWM algorithms for three level inverters: implementation, performance analysis and application considerations

This paper describes the different types of space vector based bus clamped PWM algorithms for three level inverters. A novel bus clamp PWM algorithm for low modulation indices region is also presented. The principles and switching sequences of all the types of bus clamped algorithms for high switching frequency are presented. Synchronized version of the PWM sequences for high power applications where switching frequency is low is also presented. The implementation details on DSP based digital controller and experimental results are presented. The THD of the output waveforms is studied for the entire operating region and is compared with the conventional space vector PWM technique. The bus clamped techniques can be used to reduce the switching losses or to improve the output voltage quality or both.. Different issues dominate depending on the type of application and power rating of the inverters. The results presented in this paper can be used for judicious use of the PWM techniques, which result in improved system efficiency and performance.