二穗短柄草的遗传转化及VER2等基因在水稻中的功能初探

作为模式植物，水稻和拟南芥对于禾本科植物的研究都有其不足，二穗短柄草（Brachypodiumdistachyon）有望成为它们良好的补充。它具有作为一种模式植物所应该具有的各项优点，并且它与温带禾本科植物的亲缘关系比水稻更近。建立其良好转化体系是其成功应用的一环。本论文第一章以建立其农杆菌转化体系为目的，成功的诱导了其胚性愈伤组织，获得了潮霉素抗性愈伤，发现乙酰丁香酮浓度与转化效率的关系，并证明Silwet L-77对提高其转化效率有明显的作用，为进一步完善其转化体系打下了基础。 VER2是由本实验室发现的小麦春化相关基因，并己证明它可能参与春化过程中O-CJlcNAc介导的信号传导。本论文第二章研究了将VER2在水稻中过表达所引起的表型，发现VER2与光有类似的抑制根生长的作用，并且能够互相影响对方的表型，说明二者在水稻内调控根生长的信号途径既有共同的作用，但是又相互制约。进一步的研究有可能会找到水稻根内IAA响应的重要因子。 在第三章中，根据芯片数据克隆了水稻的十个可能与赤霉素、茉莉酸和减数分裂相关的上下调基因，并对其中四个利用过表达和RNAi技术进行了水稻转化，以研究它们在水稻中的功能。其中一个基因过表达的表型与赤霉素缺陷造成矮化和叶色深绿两个特征一致，而RNAi导致植株高度增加、叶色黄绿。而该基因受赤霉素诱导上调的程度在三个芯片杂交结果中最大(log2=2.3275)这一点也为其功能提供了很好的提示，即可能参与了赤霉素信号途径。

Selective epitaxial growth in silicon on insulator: Planarity and mass flow

Seeded zone-melt recrystallization using a dual electron beam system has been performed on silicon-on-insulator material, which was prepared with single-crystal silicon filling of the seed windows by selective epitaxial growth. The crystal quality has been assessed by a variety of microscopic techniques, and it is shown that single-crystal films 0.5-1.0 μm thick over 1.0 μm of isolating oxide may be prepared by this method. These films have considerably less lateral variation in thickness than standard material, in which the windows are not so filled. The filling method is suitable for both single- and multiple-layer silicon-on-insulator, and gives the advantages of excellent layer uniformity after recrystallization and improved planarity of the whole chip structure. Experiments using various amounts of seed window filling have shown that the lateral variations of silicon film thickness seen in unplanarized material are due to stress relief in the cap oxide when the silicon film is molten, rather than the effect previously postulated in which they were assumed to be due to the contraction of silicon on melting.

Study on fishing gears, species selectivity toward gears and catch composition of BSKB beel, Khulna, Bangladesh

An investigation on the types of fishing gear used and their species selectivity and effects on fishes of BSKB beel in Khulna was conducted from June '95 to January '96. Fishermen were found to follow 6 fishing techniques viz., netting, trapping, angling, spearing, dewatering and hand picking. Among them 23 types of the fishing gear was recorded to be used by the fishermen of which 7, 8, 4 and 4 are nets, traps, hooks and lines, and hand harpoon respectively. A total of 47 species of fish were identified in the catches of different gears used by the fishermen in BSKB beel. Particulars, mode of operation, fishing season and catch composition of different fishing gears were determined. Seine, cast and lift net, traps (charo, arinda and ghuni), and hooks and lines (dhawn and nol broshi) were recorded as nonselective gear considering the fish species caught. However, gill nets (punti, koi and fash jal), clasp nets (bhuti jal), some traps (khadom, tubo), hooks and lines (chip borshi, chasra) and all spears were used as more or less selective gear. With respect to species and its size fash jal, bhuti jal, trap (khadom, ramani), and koach, juti and jhupi among spears were regarded to be more or less large-species-gear. But punti jal, koi jal, trap (koi dughair, charo, tubo, arinda and ghuni), nol borshi and spear (ful-kuchi) were small-species-gear. Among all gears seine net, cast net, lift net, koi dughair and ramani were recorded deleterious for carps especially for stocked fingerlings. For relatively small sized wild fishes koi jal, punti jal and ghuni traps were identified as detrimental gear.

High speed performance of Mach-Zehnder all-optical regenerators using semiconductor optical amplifiers

Interferometric Optical Wavelength Converters (IOWCs) provide wavelength conversion functionality at high bit rates, and give low chip and enhanced extinction ratio compared with Cross-Gain wavelength converters. In paper, a numerical simulation is conducted to assess the noise performance of IOWC and its potential for cascading. The details of the experiment and the results obtained are presented.

A closely integrated digital image capture device for embedded applications

A modular image capture system with close integration to CCD cameras has been developed. The aim is to produce a system capable of integrating CCD sensor, image capture and image processing into a single compact unit. This close integration provides a direct mapping between CCD pixels and digital image pixels. The system has been interfaced to a digital signal processor board for the development and control of image processing tasks. These have included characterization and enhancement of noisy images from an intensified camera and measurement to subpixel resolutions. A highly compact form of the image capture system is in an advanced stage of development. This consists of a single FPGA device and a single VRAM providing a two chip image capturing system capable of being integrated into a CCD camera. A miniature compact PC has been developed using a novel modular interconnection technique, providing a processing unit in a three dimensional format highly suited to integration into a CCD camera unit. Work is under way to interface the compact capture system to the PC using this interconnection technique, combining CCD sensor, image capture and image processing into a single compact unit. ©2005 Copyright SPIE - The International Society for Optical Engineering.

A fully integrated 660 MHz low-swing energy-recycling DC-DC converter

A fully integrated 0.18 μm DC-DC buck converter using a low-swing "stacked driver" configuration is reported in this paper. A high switching frequency of 660 MHz reduces filter components to fit on chip, but this suffers from high switching losses. These losses are reduced using: 1) low-swing drivers; 2) supply stacking; and 3) introducing a charge transfer path to deliver excess charge from the positive metal-oxide semiconductor drive chain to the load, thereby recycling the charge. The working prototype circuit converts 2.2 to 0.75-1.0 V at 40-55 mA. Design and simulation of an improved circuit is also included that further improves the efficiency by enhancing the charge recycling path, providing automated zero voltage switching (ZVS) operation, and synchronizing the half-swing gating signals. © 2009 IEEE.

A packaging technique for silicon MEMS strain sensors on steel

A packaging technique suited to applying MEMS strain sensors realized on a silicon chip to a steel flat surface is described. The method is based on adhesive bonding of the silicon chip rear surface on steel using two types of glue normally used for standard piezoresistive strain sensors (Mbond200/ 600), using direct wire bonding of the chip to a Printed Circuit Board, also fixed on steel. In order to protect the sensor from the external environment, and to improve the MEMS performance, the silicon chip is encapsulated with a metal cap hermetically sealed-off under vacuum condition with a vacuum adhesive in which the bonding wires are also protected from possible damage. In order to evaluate the mechanical coupling of the silicon chip with the bar and thestress transfer extent to the silicon surface, commercial strain sensors have been applied on the chip glued on a steel bar in alaboratory setup able to generate strain by inflection, yielding a stress transfer around 70% from steel to silicon. © 2008 IEEE.

Soft turn-on of NPT IGBT under Active Voltage Control

In this paper the soft turn-on of NPT IGBT under Active Voltage Control (AVC) is presented. The AVC technique is able to control the IGBT switching trajectory according to a pre-defined reference signal generated by a FPGA chip. By applying a special designed reference signal at turn-on, the IGBT turn-on current overshoot and diode recovery can be optimized. Experiments of soft turn-on with different reference signal are presented in this paper. This technique can be used to reduce the switching stress on the device and on other components of the circuit. © 2011 IEEE.

A high temperature SOI CMOS NO2 sensor

For more than 20 years researchers have been interested in developing micro-gas sensors based on silicon technology. Most of the reported devices are based on micro-hotplates, however they use materials that are not CMOS compatible, and therefore are not suitable for large volume manufacturing. Furthermore, they do not allow the circuitry to be integrated on to the chip. CMOS compatible devices have been previously reported. However, these use polysilicon as the heater material, which has long term stability problems at high temperatures. Here we present low power, low cost SOI CMOS NO2 sensors, based on high stability single crystal silicon P+ micro-heaters platforms, capable of measuring gas concentrations down to 0.1 ppm. We have integrated a thin tungsten molybdenum oxide layer as a sensing material with a foundry-standard SOI CMOS micro-hotplate and tested this to NO2. We believe these devices have the potential for use as robust, very low power consumption, low cost gas sensors. © 2011 American Institute of Physics.

Guided growth of neurons and glia using microfabricated patterns of parylene-C on a SiO2 background.

This paper describes a simple technique for the patterning of glia and neurons. The integration of neuronal patterning to Multi-Electrode Arrays (MEAs), planar patch clamp and silicon based 'lab on a chip' technologies necessitates the development of a microfabrication-compatible method, which will be reliable and easy to implement. In this study a highly consistent, straightforward and cost effective cell patterning scheme has been developed. It is based on two common ingredients: the polymer parylene-C and horse serum. Parylene-C is deposited and photo-lithographically patterned on silicon oxide (SiO(2)) surfaces. Subsequently, the patterns are activated via immersion in horse serum. Compared to non-activated controls, cells on the treated samples exhibited a significantly higher conformity to underlying parylene stripes. The immersion time of the patterns was reduced from 24 to 3h without compromising the technique. X-ray photoelectron spectroscopy (XPS) analysis of parylene and SiO(2) surfaces before and after immersion in horse serum and gel based eluant analysis suggests that the quantity and conformation of proteins on the parylene and SiO(2) substrates might be responsible for inducing glial and neuronal patterning.

A hot channel

This paper studies on-chip communication with non-ideal heat sinks. A channel model is proposed where the variance of the additive noise depends on the weighted sum of the past channel input powers. It is shown that, depending on the weights, the capacity can be either bounded or unbounded in the input power. A necessary condition and a sufficient condition for the capacity to be bounded are presented. © 2007 IEEE.

Embedded Model Predictive Control (MPC) using a FPGA

Model Predictive Control (MPC) is increasingly being proposed for application to miniaturized devices, fast and/or embedded systems. A major obstacle to this is its computation time requirement. Continuing our previous studies of implementing constrained MPC on Field Programmable Gate Arrays (FPGA), this paper begins to exploit the possibilities of parallel computation, with the aim of speeding up the MPC implementation. Simulation studies on a realistic example show that it is possible to implement constrained MPC on an FPGA chip with a 25MHz clock and achieve MPC implementation rates comparable to those achievable on a Pentium 3.0 GHz PC. Copyright © 2007 International Federation of Automatic Control All Rights Reserved.

SoC energy savings = reduce+reuse+recycle: A case study using a 660MHz DC-DC converter with integrated output filter

This paper advocates 'reduce, reuse, recycle' as a complete energy savings strategy. While reduction has been common to date, there is growing need to emphasize reuse and recycling as well. We design a DC-DC buck converter to demonstrate the 3 techniques: reduce with low-swing and zero voltage switching (ZVS), reuse with supply stacking, and recycle with regulated delivery of excess energy to the output load. The efficiency gained from these 3 techniques helps offset the loss of operating drivers at very high switching frequencies which are needed to move the output filter completely on-chip. A prototype was fabricated in 0.18μm CMOS, operates at 660MHz, and converts 2.2V to 0.75-1.0V at ∼50mA.1 © 2008 IEEE.

Energy recovery from high-frequency clocks using DC-DC converters

Large digital chips use a significant amount of energy to distribute a multi-GHz clock. By discharging the clock network to ground every cycle, the energy stored in this large capacitor is wasted. Instead, the energy can be recovered using an on-chip DC-DC converter. This paper investigates the integration of two DC-DC converter topologies, boost and buck-boost, with a high-speed clock driver. The high operating frequency significantly shrinks the required size of the L and C components so they can be placed on-chip; typical converters place them off-chip. The clock driver and DC-DC converter are able to share the entire tapered buffer chain, including the widest drive transistors in the final stage. To achieve voltage regulation, the clock duty cycle must be modulated; implying only single-edge-triggered flops should be used. However, this minor drawback is eclipsed by the benefits: by recovering energy from the clock, the output power can actually exceed the additional power needed to operate the converter circuitry, resulting in an effective efficiency greater than 100%. Furthermore, the converter output can be used to operate additional power-saving features like low-voltage islands or body bias voltages. ©2008 IEEE.

A 4 GHz non-resonant clock driver with inductor-assisted energy return to power grid

Power consumption of a multi-GHz local clock driver is reduced by returning energy stored in the clock-tree load capacitance back to the on-chip power-distribution grid. We call this type of return energy recycling. To achieve a nearly square clock waveform, the energy is transferred in a non-resonant way using an on-chip inductor in a configuration resembling a full-bridge DC-DC converter. A zero-voltage switching technique is implemented in the clock driver to reduce dynamic power loss associated with the high switching frequencies. A prototype implemented in 90 nm CMOS shows a power savings of 35% at 4 GHz. The area needed for the inductor in this new clock driver is about 6% of a local clock region. © 2006 IEEE.