958 resultados para PIN diodes


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In this work we studied the properties of absorption and emission line shape of layer-by-layer (LBL) poly(p-phenylene vinylene) (PPV) on indium-tin oxide (ITO) electrode. To minimize the PPV thermal conversion effects during the polymer processing, we used a less aggressive leaving group in the precursor polymer; minimizing electrode degradation. LBL ITO/PPV films showed the same absorption and emission line shape compared with LBL PPV films deposited on non-metallic substrates (glass). With this analysis we indirectly observe the decrease in the ITO degradation. Atomic force microscopy (AFM) technique was used to analyze quantitatively the microscopic morphology of the film surface. Results indicated that the substrate topology is not affected, to a large extent, by the use of dodecylbenzensulfonate (DBS) ion. (C) 2008 Elsevier B.V. All rights reserved.

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This study was addressed to investigate the composition and antifungal activity of essential oils from leaves of Piperaceae species (Piper aduncum, Piper amalago, Piper cernuum, Piper diospyrifolium, Piper crassinervium, Piper gaudichaudianum, Piper solmsianum, Piper regnellii, Piper tuberculatum, Piper umbelata and Peperomia obtusifolia) against Candida albicans, C. parapsilosis, C. krusei and Cryptococcus neoformans. The essential oils from P. aduncum, P. gaudichaudianum and P. solmsianum showed the highest antifungal activity against Cryptococcus neoformans with the MIC of 62.5, 62.5 and 3.9 mg.mL-1, respectively. The oil from P. gaudichaudianum showed activity against C. krusei with MIC of 31.25 mg.mL-1.

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Photoluminescence and electroluminescence of PVK films doped with fac-[ClRe(CO)(3)(bpy)], bpy=2,2`-bipyridine, are investigated. Photoluminescence spectra of spin-coated PVK films (lambda(exc)=290 nm) exhibit a broad band centered at 405 nm. As the concentration of dopant increases, the polymer emission is quenched and a band at 555 nm appears (isosbestic point at 475 nm). In OLEDs with ITO/PEDOT:PSS/PVK/butylPBD/Al architecture doped with fac-[ClRe(CO)(3)(bpy)], the polymer host emission is completely quenched even at the lowest concentration of dopant. The electroluminescence spectra of the devices show that there is an efficient energy transfer from the host to the dopant, which exhibits a very intense emission at 580 nm. (C) 2009 Elsevier B.V. All rights reserved.

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We describe the optical and electrical characterization of a poly(p-phenylenevinylene) derivative: poly(2-dodecanoylsulfanyl-p-phenylenevinylene) (12COS-PPV). The electrical characterization was carried out on devices with the FTO\PEDOT:PSS\12COS-PPV/Al structure. Positive charge carrier mobility mu(h) of similar to 1.0 x 10(-6) cm(2) V(-1) s(-1) and barrier height phi of similar to 0.1 eV for positive charge carrier injection at the PEDOT:PSS/12COS-PPV interface were obtained using a thermionic injection model. FTO\PEDOT:P55\12COS-PPV/Ca devices exhibited green-yellow electroluminescence with maximum emission at lambda = 540 nm.

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The excited-state dynamics of two polyfluorene copolymers, one fully conjugated containing phenylene vinylene units alternated with 9,9`-dihexylfluorenyl groups and the other segmented by -(CH2)(8)- spacer, were studied in dilute solution of different solvents using a picosecond single-photon timing technique. The excited-state dynamics of the segmented copolymer follows the Forster resonant energy-transfer model which describes intrachain energy-transfer kinetics among random oriented chromophores. Energy transfer is confirmed by analysis of fluorescence anisotropy relaxation with the measurement of a short decay component of about 60 ps. The fluorescence decay surface of the fully conjugated copolymer is biexponential with decay times of about 470 and 900 ps, ascribed to deactivation of chain moieties containing trans and cis isomers already in a photostationary condition. Thus, energy transfer is very fast due to the conjugated nature and rigid-rod-like structure of this copolymer chain.

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An overview of the theoretical literature for the last two decades suggests that there is no clear-cut relationship one can pin down between exchange rate volatility and trade flows. Analytical results are based on specific assumptions and only hold in certain cases. Especially, the impact of exchange rate volatility on export and import activity investigated separately leads also to dissimilar conclusions among countries studied. The general presumption is that an increase in exchange rate volatility will have an adverse effect on trade flows and consequently, the overall heath of the world economy. However, neither theoretical models nor empirical studies provide us with a definitive answer, leaving obtained results highly ambiguous and inconsistent (Baum and Caglayan, 2006). We purposed to empirically investigate trade effects of exchange rate fluctuations in Sweden from the perspective of export and import in this research. The data comprises period from January 1993 to December 2006, where export and import volumes are considered from the point of their determinants, including exchange rate volatility, which has been measured through EGARCH model. The results for the case of Sweden show that short run dynamics of volatility negatively associated with both export and import, whereas considered from the case of previous period volatility it exhibits positive relationship. These results are consistent with the most findings of prior studies, where the relationship remained ambiguous.

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The features of non-native speech which distinguish it from native speech are often difficult to pin down. It is possible to be a native speaker of any of a vast number of varieties of English. These varieties each have their phonetic characteristics which allow them to be identified by speakers of the varieties in question and by others. The phonetic differences between the accents represented by these varieties are very great. It is impossible to indicate any particular configuration of vowels in the acoustic vowel space or set of consonant articulations which all native-speaker varieties of English have in common and which non-native speakers do not share. This study considers the vowel quality in a single word by native and non-native speakers.

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Cemented carbide is today the most frequently used drawing die material in steel wire drawing applications. This is mainly due to the possibility to obtain a broad combination of hardness and toughness thus meeting the requirements concerning strength, crack resistance and wear resistance set by the wire drawing process. However, the increasing cost of cemented carbide in combination with the possibility to increase the wear resistance of steel through the deposition of wear resistant CVD and PVD coatings have enhanced the interest to replace cemented carbide drawing dies with CVD and PVD coated steel wire drawing dies. In the present study, the possibility to replace cemented carbide wire drawing dies with CVD and PVD coated steel drawing dies have been investigated by tribological characterisation, i.e. pin-on-disc and scratch testing, in combination with post-test observations of the tribo surfaces using scanning electron microscopy, energy dispersive X-ray spectroscopy and 3D surface profilometry. Based on the results obtained, CVD and PVD coatings aimed to provide improved tribological performance of steel wire drawing dies should display a smooth surface topography, a high wear resistance, a high fracture toughness (i.e. a high cracking and chipping resistance) and intrinsic low friction properties in contact with the wire material. Also, the steel substrate used must display a sufficient load carrying capacity and resistance to thermal softening. Of the CVD and PVD coatings evaluated in the tribological tests, a CVD TiC and a PVD CrC/C coating displayed the most promising results.

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A new test method based on multipass scratch testing has been developed for evaluating the mechanical and tribological properties of thin, hard coatings. The proposed test method uses a pin-on-disc tribometer and during testing a Rockwell C diamond stylus is used as the “pin” and loaded against the rotating coated sample. The influence of normal load on the number of cycles to coating damage is investigated and the resulting coating damage mechanisms are evaluated by posttest scanning electron microscopy. The present study presents the test method by evaluating the performance of Ti0.86Si0.14N, Ti0.34Al0.66N, and (Al0.7Cr0.3)2O3 coatings deposited by cathodic arc evaporation on cemented carbide inserts. The results show that the test method is quick, simple, and reproducible and can preferably be used to obtain relevant data concerning the fatigue, wear, chipping, and spalling characteristics of different coating-substrate composites. The test method can be used as a virtually nondestructive test and, for example, be used to evaluate the fatigue and wear resistance as well as the cohesive and adhesive interfacial strength of coated cemented carbide inserts prior to cutting tests.

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Artigo apresentado na Intercom 2007

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Usamos uma série de ADRs de países da América Latina para replicar o estudo de Easley, Hvidkjaer e O’Hara (2002) sobre o efeito da negociação com informação diferenciada nos retornos dos ativos financeiros. Estimamos a probabilidade de negociação com informação diferenciada (PIN) e testamos a existência de um risco informacional sistemático em um modelo de apreçamento do tipo Fama-French. O principal resultado encontrado foi que o PIN médio dos ADRs latino americanos é maior que o PIN médio das empresas dos Estados Unidos. Entretanto, não conseguimos estabelecer uma relação clara entre o retorno dos ADRs e a sua respectiva probabilidade de negociação com informação diferenciada, sugerindo que a tecnologia de apreçamento adota não é especialmente adequada.

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Electronic applications are currently developed under the reuse-based paradigm. This design methodology presents several advantages for the reduction of the design complexity, but brings new challenges for the test of the final circuit. The access to embedded cores, the integration of several test methods, and the optimization of the several cost factors are just a few of the several problems that need to be tackled during test planning. Within this context, this thesis proposes two test planning approaches that aim at reducing the test costs of a core-based system by means of hardware reuse and integration of the test planning into the design flow. The first approach considers systems whose cores are connected directly or through a functional bus. The test planning method consists of a comprehensive model that includes the definition of a multi-mode access mechanism inside the chip and a search algorithm for the exploration of the design space. The access mechanism model considers the reuse of functional connections as well as partial test buses, cores transparency, and other bypass modes. The test schedule is defined in conjunction with the access mechanism so that good trade-offs among the costs of pins, area, and test time can be sought. Furthermore, system power constraints are also considered. This expansion of concerns makes it possible an efficient, yet fine-grained search, in the huge design space of a reuse-based environment. Experimental results clearly show the variety of trade-offs that can be explored using the proposed model, and its effectiveness on optimizing the system test plan. Networks-on-chip are likely to become the main communication platform of systemson- chip. Thus, the second approach presented in this work proposes the reuse of the on-chip network for the test of the cores embedded into the systems that use this communication platform. A power-aware test scheduling algorithm aiming at exploiting the network characteristics to minimize the system test time is presented. The reuse strategy is evaluated considering a number of system configurations, such as different positions of the cores in the network, power consumption constraints and number of interfaces with the tester. Experimental results show that the parallelization capability of the network can be exploited to reduce the system test time, whereas area and pin overhead are strongly minimized. In this manuscript, the main problems of the test of core-based systems are firstly identified and the current solutions are discussed. The problems being tackled by this thesis are then listed and the test planning approaches are detailed. Both test planning techniques are validated for the recently released ITC’02 SoC Test Benchmarks, and further compared to other test planning methods of the literature. This comparison confirms the efficiency of the proposed methods.

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This thesis presents the study and development of fault-tolerant techniques for programmable architectures, the well-known Field Programmable Gate Arrays (FPGAs), customizable by SRAM. FPGAs are becoming more valuable for space applications because of the high density, high performance, reduced development cost and re-programmability. In particular, SRAM-based FPGAs are very valuable for remote missions because of the possibility of being reprogrammed by the user as many times as necessary in a very short period. SRAM-based FPGA and micro-controllers represent a wide range of components in space applications, and as a result will be the focus of this work, more specifically the Virtex® family from Xilinx and the architecture of the 8051 micro-controller from Intel. The Triple Modular Redundancy (TMR) with voters is a common high-level technique to protect ASICs against single event upset (SEU) and it can also be applied to FPGAs. The TMR technique was first tested in the Virtex® FPGA architecture by using a small design based on counters. Faults were injected in all sensitive parts of the FPGA and a detailed analysis of the effect of a fault in a TMR design synthesized in the Virtex® platform was performed. Results from fault injection and from a radiation ground test facility showed the efficiency of the TMR for the related case study circuit. Although TMR has showed a high reliability, this technique presents some limitations, such as area overhead, three times more input and output pins and, consequently, a significant increase in power dissipation. Aiming to reduce TMR costs and improve reliability, an innovative high-level technique for designing fault-tolerant systems in SRAM-based FPGAs was developed, without modification in the FPGA architecture. This technique combines time and hardware redundancy to reduce overhead and to ensure reliability. It is based on duplication with comparison and concurrent error detection. The new technique proposed in this work was specifically developed for FPGAs to cope with transient faults in the user combinational and sequential logic, while also reducing pin count, area and power dissipation. The methodology was validated by fault injection experiments in an emulation board. The thesis presents comparison results in fault coverage, area and performance between the discussed techniques.

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The work is to undertake a review of the control system's internal disciplinary Military Police of Amazonas (PMAM) as a way to identify factors that deserve to be modified or improved before the current social situation that is presented to our Public Military Force. For this purpose discussing the elements motivating and purpose of disciplinary punishment to the question 'Why punish?'. Then were the legal aspects of legal and disciplinary reprimand the legislation in force. It was subsequently approached the concept of police activity in Brazil and its peculiarities, moving then to examine the main figures of our state correctional compared with other states of the country. Before closing, we analyze the data Search Field watching the view of commanders and commanded the respect of the disciplinary system now in military force.

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o trabalho tem como base uma revisão de literatura sobre o tema Governo Eletrônico, estando seu foco voltado para a sua utilização nas 27 assembléias legislativas estaduais do Brasil, no que diz respeito a sua utilização como ferramenta de transparência pública. Mais especificamente, a presente dissertação buscou mensurar o nível de transparência nos portais eletrônicos dessas assembléias legislativas. Para tal desiderato, foi necessário realizar uma pesquisa bibliográfica sobre o tema, que serviu de suporte literário para o devido embasamento das formulações e conclusões que foram apresentadas no decorrer do estudo. A mensuração do grau de transparência dos portais eletrônicos dos legislativos estaduais foi realizada a partir da aplicação de um método de mensuração de transparência eletrônica, com as devidas adaptações, a qual é utilizada pela organização não governamental, Monitor Legislativo, para a monitoração dos portais eletrônicos do legislativo do México, tendo como base a lei de transparência pública e acesso a informações públicas governamentais, hoje em vigor naquele país. Assim, o modelo levou em consideração a disponibilização de informações sobre: função administrativa; controle interno; trabalho legislativo; trabalho das comissões; concessões, permissões e contratos; arquivo histórico e serviços bibliotecários; e controles externos. A mensuração foi feita item a item, já apresentando um quadro da transparência por item. Não obstante, no final do trabalho foi apresentado um ranking geral da transparência eletrônica, no qual foram dispostas todas as assembléias legislativas estaduais com suas respectivas notas e nível de transparência correspondente. Por fim, os resultados da pesquisa foram correlacionados a outras variáveis, com o intuito de verificar se havia algum grau de relação entre as variáveis analisadas e a transparência eletrônica.