Hardware basado en FPGA para síntesis de audio mediante muestras grabadas y control MIDI

El objetivo de este proyecto es desarrollar una plataforma hardware capaz de sintetizar sonidos a partir de fragmentos grabados, y de ser controlado mediante un dispositivo MIDI. Para ello se utilizará: - una placa de prototipado que incluye un dispositivo programable (FPGA) y un CODEC para la grabación/reproducción de audio digital. - un teclado MIDI.

FTT-MA: A Flexible Time-Triggered Middleware Architecture for Time Sensitive, Resource-Aware AmI Systems

There is an increasing number of Ambient Intelligence (AmI) systems that are time-sensitive and resource-aware. From healthcare to building and even home/office automation, it is now common to find systems combining interactive and sensing multimedia traffic with relatively simple sensors and actuators (door locks, presence detectors, RFIDs, HVAC, information panels, etc.). Many of these are today known as Cyber-Physical Systems (CPS). Quite frequently, these systems must be capable of (1) prioritizing different traffic flows (process data, alarms, non-critical data, etc.), (2) synchronizing actions in several distributed devices and, to certain degree, (3) easing resource management (e.g., detecting faulty nodes, managing battery levels, handling overloads, etc.). This work presents FTT-MA, a high-level middleware architecture aimed at easing the design, deployment and operation of such AmI systems. FTT-MA ensures that both functional and non-functional aspects of the applications are met even during reconfiguration stages. The paper also proposes a methodology, together with a design tool, to create this kind of systems. Finally, a sample case study is presented that illustrates the use of the middleware and the methodology proposed in the paper.

High-Strength Composite Fibers: Realizing True Potential of Carbon Nanotubes in Polymer Matrix through Continuous Reticulate Architecture and Molecular Level Couplings

Carbon nanotubes have unprecedented mechanical properties as defect-free nanoscale building blocks, but their potential has not been fully realized in composite materials due to weakness at the interfaces. Here we demonstrate that through load-transfer-favored three-dimensional architecture and molecular level couplings with polymer chains, true potential of CNTs can be realized in composites as Initially envisioned. Composite fibers with reticulate nanotube architectures show order of magnitude improvement in strength compared to randomly dispersed short CNT reinforced composites reported before. The molecular level couplings between nanotubes and polymer chains results in drastic differences in the properties of thermoset and thermoplastic composite fibers, which indicate that conventional macroscopic composite theory falls to explain the overall hybrid behavior at nanoscale.

Adaptive Scalable SVD Unit for Fast Processing of Large LSE Problems

Singular Value Decomposition (SVD) is a key linear algebraic operation in many scientific and engineering applications. In particular, many computational intelligence systems rely on machine learning methods involving high dimensionality datasets that have to be fast processed for real-time adaptability. In this paper we describe a practical FPGA (Field Programmable Gate Array) implementation of a SVD processor for accelerating the solution of large LSE problems. The design approach has been comprehensive, from the algorithmic refinement to the numerical analysis to the customization for an efficient hardware realization. The processing scheme rests on an adaptive vector rotation evaluator for error regularization that enhances convergence speed with no penalty on the solution accuracy. The proposed architecture, which follows a data transfer scheme, is scalable and based on the interconnection of simple rotations units, which allows for a trade-off between occupied area and processing acceleration in the final implementation. This permits the SVD processor to be implemented both on low-cost and highend FPGAs, according to the final application requirements.

Dense, efficient chip-to-chip communication at the extremes of computing

The scalability of CMOS technology has driven computation into a diverse range of applications across the power consumption, performance and size spectra. Communication is a necessary adjunct to computation, and whether this is to push data from node-to-node in a high-performance computing cluster or from the receiver of wireless link to a neural stimulator in a biomedical implant, interconnect can take up a significant portion of the overall system power budget. Although a single interconnect methodology cannot address such a broad range of systems efficiently, there are a number of key design concepts that enable good interconnect design in the age of highly-scaled CMOS: an emphasis on highly-digital approaches to solving ‘analog’ problems, hardware sharing between links as well as between different functions (such as equalization and synchronization) in the same link, and adaptive hardware that changes its operating parameters to mitigate not only variation in the fabrication of the link, but also link conditions that change over time. These concepts are demonstrated through the use of two design examples, at the extremes of the power and performance spectra.

A novel all-digital clock and data recovery technique for high-performance, high density interconnect has been developed. Two independently adjustable clock phases are generated from a delay line calibrated to 2 UI. One clock phase is placed in the middle of the eye to recover the data, while the other is swept across the delay line. The samples produced by the two clocks are compared to generate eye information, which is used to determine the best phase for data recovery. The functions of the two clocks are swapped after the data phase is updated; this ping-pong action allows an infinite delay range without the use of a PLL or DLL. The scheme's generalized sampling and retiming architecture is used in a sharing technique that saves power and area in high-density interconnect. The eye information generated is also useful for tuning an adaptive equalizer, circumventing the need for dedicated adaptation hardware.

On the other side of the performance/power spectra, a capacitive proximity interconnect has been developed to support 3D integration of biomedical implants. In order to integrate more functionality while staying within size limits, implant electronics can be embedded onto a foldable parylene (‘origami’) substrate. Many of the ICs in an origami implant will be placed face-to-face with each other, so wireless proximity interconnect can be used to increase communication density while decreasing implant size, as well as facilitate a modular approach to implant design, where pre-fabricated parylene-and-IC modules are assembled together on-demand to make custom implants. Such an interconnect needs to be able to sense and adapt to changes in alignment. The proposed array uses a TDC-like structure to realize both communication and alignment sensing within the same set of plates, increasing communication density and eliminating the need to infer link quality from a separate alignment block. In order to distinguish the communication plates from the nearby ground plane, a stimulus is applied to the transmitter plate, which is rectified at the receiver to bias a delay generation block. This delay is in turn converted into a digital word using a TDC, providing alignment information.

Self-healing Techniques for RF and mm-Wave Transmitters and Receivers

With continuing advances in CMOS technology, feature sizes of modern Silicon chip-sets have gone down drastically over the past decade. In addition to desktops and laptop processors, a vast majority of these chips are also being deployed in mobile communication devices like smart-phones and tablets, where multiple radio-frequency integrated circuits (RFICs) must be integrated into one device to cater to a wide variety of applications such as Wi-Fi, Bluetooth, NFC, wireless charging, etc. While a small feature size enables higher integration levels leading to billions of transistors co-existing on a single chip, it also makes these Silicon ICs more susceptible to variations. A part of these variations can be attributed to the manufacturing process itself, particularly due to the stringent dimensional tolerances associated with the lithographic steps in modern processes. Additionally, RF or millimeter-wave communication chip-sets are subject to another type of variation caused by dynamic changes in the operating environment. Another bottleneck in the development of high performance RF/mm-wave Silicon ICs is the lack of accurate analog/high-frequency models in nanometer CMOS processes. This can be primarily attributed to the fact that most cutting edge processes are geared towards digital system implementation and as such there is little model-to-hardware correlation at RF frequencies.

All these issues have significantly degraded yield of high performance mm-wave and RF CMOS systems which often require multiple trial-and-error based Silicon validations, thereby incurring additional production costs. This dissertation proposes a low overhead technique which attempts to counter the detrimental effects of these variations, thereby improving both performance and yield of chips post fabrication in a systematic way. The key idea behind this approach is to dynamically sense the performance of the system, identify when a problem has occurred, and then actuate it back to its desired performance level through an intelligent on-chip optimization algorithm. We term this technique as self-healing drawing inspiration from nature's own way of healing the body against adverse environmental effects. To effectively demonstrate the efficacy of self-healing in CMOS systems, several representative examples are designed, fabricated, and measured against a variety of operating conditions.

We demonstrate a high-power mm-wave segmented power mixer array based transmitter architecture that is capable of generating high-speed and non-constant envelope modulations at higher efficiencies compared to existing conventional designs. We then incorporate several sensors and actuators into the design and demonstrate closed-loop healing against a wide variety of non-ideal operating conditions. We also demonstrate fully-integrated self-healing in the context of another mm-wave power amplifier, where measurements were performed across several chips, showing significant improvements in performance as well as reduced variability in the presence of process variations and load impedance mismatch, as well as catastrophic transistor failure. Finally, on the receiver side, a closed-loop self-healing phase synthesis scheme is demonstrated in conjunction with a wide-band voltage controlled oscillator to generate phase shifter local oscillator (LO) signals for a phased array receiver. The system is shown to heal against non-idealities in the LO signal generation and distribution, significantly reducing phase errors across a wide range of frequencies.

Isolation of the murine interleukin 2 gene and characterization of its regulatory architecture

Interleukin 2 (IL2) is the primary growth hormone used by mature T cells and this lymphokine plays an important role in the magnification of cell-mediated immune responses. Under normal circumstances its expression is limited to antigen-activated type 1 helper T cells (T_H1) and the ability to transcribe this gene is often regarded as evidence for commitment to this developmental lineage. There is, however, abundant evidence than many non-T_H1 T cells, under appropriate conditions, possess the ability to express this gene. Of paramount interest in the study of T-cell development is the mechanisms by which differentiating thymocytes are endowed with particular combinations of cell surface proteins and response repertoires. For example, why do most helper T cells express the CD4 differentiation antigen?

As a first step in understanding these developmental processes the gene encoding IL2 was isolated from a mouse genomic library by probing with a conspecific IL2 cDNA. The sequence of the 5' flanking region from + 1 to -2800 was determined and compared to the previously reported human sequence. Extensive identity exists between +1 and -580 (86%) and sites previously shown to be crucial for the proper expression of the human gene are well conserved in both sequence location in the mouse counterpart.

Transient expression assays were used to evaluate the contribution of various genomic sequences to high-level gene expression mediated by a cloned IL2 promoter fragment. Differing lengths of 5' flanking DNA, all terminating in the 5' untranslated region, were linked to a reporter gene, bacterial chloramphenicol acetyltransferase (CAT) and enzyme activity was measured after introduction into IL2-producing cell lines. No CAT was ever detected without stimulation of the recipient cells. A cloned promoter fragment containing only 321 bp of upstream DNA was expressed well in both Jurkat and EL4.El cells. Addition of intragenic or downstream DNA to these 5' IL2-CAT constructs showed that no obvious regulatory regions resided there. However, increasing the extent of 5' DNA from -321 to -2800 revealed several positive and negative regulatory elements. One negative region that was well characterized resided between -750 and -1000 and consisted almost exclusively of alternating purine and pyrimidines. There is no sequence resembling this in the human gene now, but there is evidence that there may have once been.

No region, when deleted, could relax either the stringent induction-dependence on cell-type specificity displayed by this promoter. Reagents that modulated endogenous IL2 expression, such as cAMP, cyclosporin A, and IL1, affected expression of the 5' IL2-CAT constructs also. For a given reagent, expression from all expressible constructs was suppressed or enhanced to the same extent. This suggests that these modulators affect IL2 expression through perturbation of a central inductive signal rather than by summation of the effects of discrete, independently regulated, negative and positive transcription factors.

Visual pattern recognition network: Its training algorithm and its optoelectronic architecture

A visual pattern recognition network and its training algorithm are proposed. The network constructed of a one-layer morphology network and a two-layer modified Hamming net. This visual network can implement invariant pattern recognition with respect to image translation and size projection. After supervised learning takes place, the visual network extracts image features and classifies patterns much the same as living beings do. Moreover we set up its optoelectronic architecture for real-time pattern recognition. (C) 1996 Optical Society of America

Caretta caretta (Loggerhead Sea Turtle). Nest Architecture.

Researchers compared nest architecture in loggerhead sea turtles at natural beaches in Florida, USA and Brazil to determine how similarities and differences in female morphology and reproductive output in these two populations are reflected in the structure of the nest.