Real time fault injection using enhanced OCD -- a performance analysis

Fault injection is frequently used for the verification and validation of dependable systems. When targeting real time microprocessor based systems the process becomes significantly more complex. This paper proposes two complementary solutions to improve real time fault injection campaign execution, both in terms of performance and capabilities. The methodology is based on the use of the on-chip debug mechanisms present in modern electronic devices. The main objective is the injection of faults in microprocessor memory elements with minimum delay and intrusiveness. Different configurations were implemented and compared in terms of performance gain and logic overhead.

Using NEXUS compliant debuggers for real time fault injection on microprocessors

As electronic devices get smaller and more complex, dependability assurance is becoming fundamental for many mission critical computer based systems. This paper presents a case study on the possibility of using the on-chip debug infrastructures present in most current microprocessors to execute real time fault injection campaigns. The proposed methodology is based on a debugger customized for fault injection and designed for maximum flexibility, and consists of injecting bit-flip type faults on memory elements without modifying or halting the target application. The debugger design is easily portable and applicable to different architectures, providing a flexible and efficient mechanism for verifying and validating fault tolerant components.

Compact, frequency reconfigurable, printed monopole antenna

This paper proposes a possible implementation of a compact printed monopole antenna, useful to operate in UMTS and WLAN bands. In order to accomplish that, a miniaturization technique based on the application of chip inductors is used in conjunction with frequency reconfiguration capability. The chip inductors change the impedance response of the monopole, allowing to reduce the resonant frequency. In order to be able to operate the antenna in these two different frequencies, an antenna reconfiguration technique based on PIN diodes is applied. This procedure allows the change of the active form of the antenna leading to a shift in the resonant frequency. The prototype measurements show good agreement with the simulation results.

Acylated cyanoimido-complexes trans-[Mo(NCN){NCN(O)R}(DPPE)(2)]Cl and their reactons with electrophiles: Chemical, electrochemical and theoretical study

Treatment of a dichloromethane solution of trans-[Mo(NCN){NCNC(O)R}(dppe)(2)]Cl [R = Me (1a), Et (1b)] (dppe = Ph2PCH2CH2PPh2) with HBF4, [Et3O][BF4] or EtC(O)Cl gives trans-[Mo(NCN)Cl-(dppe)(2)]X [X = BF4 (2a) or Cl (2b)] and the corresponding acylcyanamides NCN(R')C(O)Et (R' = H, Et or C(O)Et). X-ray diffraction analysis of 2a (X = BF4) reveals a multiple-bond coordination of the cyanoimide ligand. Compounds 1 convert to the bis(cyanoimide) trans-[Mo(NCN)(2)(dppe)(2)] complex upon reaction with an excess of NaOMe (with formation of the respective ester). In an aprotic medium and at a Pt electrode, compounds 1 (R = Me, Et or Ph) undergo a cathodically induced isomerization. Full quantitative kinetic analysis of the voltammetric behaviour is presented and allows the determination of the first-order rate constants and the equilibrium constant of the trans to cis isomerization reaction. The mechanisms of electrophilic addition (protonation) to complexes 1 and the precursor trans[Mo(NCN)(2)(dppe)(2)], as well as the electronic structures, nature of the coordination bonds and electrochemical behaviour of these species are investigated in detail by theoretical methods which indicate that the most probable sites of the proton attack are the oxygen atom of the acyl group and the terminal nitrogen atom, respectively.

Communicación sobre lineas de suministro de energia

Informacion Tcnológica, vol. 11, nº6

Low-voltage low-power CMOS analogue circuits for Gaussian and uniform noise generation

IEEE International Symposium on Circuits and Systems, MAY 25-28, 2003, Bangkok, Thailand. (ISI Web of Science)

A modified debugging infrastructure to assist real time fault injection campaigns

Fault injection is frequently used for the verification and validation of the fault tolerant features of microprocessors. This paper proposes the modification of a common on-chip debugging (OCD) infrastructure to add fault injection capabilities and improve performance. The proposed solution imposes a very low logic overhead and provides a flexible and efficient mechanism for the execution of fault injection campaigns, being applicable to different target system architectures.

Spectroscopic Studies and Characterization of a Novel Electron-Transfer Chain

A novel two-component enzyme system from Escherichia coli involving a flavorubredoxin (FlRd) and its reductase was studied in terms of spectroscopic, redox, and biochemical properties of its constituents. FlRd contains one FMN and one rubredoxin (Rd) center per monomer. To assess the role of the Rd domain, FlRd and a truncated form lacking the Rd domain (FlRd¢Rd), were characterized. FlRd contains 2.9 ( 0.5 iron atoms/subunit, whereas FlRd¢Rd contains 2.1 ( 0.6 iron atoms/subunit. While for FlRd one iron atom corresponds to the Rd center, the other two irons, also present in FlRd¢Rd, are most probably due to a di-iron site. Redox titrations of FlRd using EPR and visible spectroscopies allowed us to determine that the Rd site has a reduction potential of -140 ( 15 mV, whereas the FMN undergoes reduction via a red-semiquinone, at -140 ( 15 mV (Flox/Flsq) and -180 ( 15 mV (Flsq/Flred), at pH 7.6. The Rd site has the lowest potential ever reported for a Rd center, which may be correlated with specific amino acid substitutions close to both cysteine clusters. The gene adjacent to that encoding FlRd was found to code for an FAD-containing protein, (flavo)rubredoxin reductase (FlRd-reductase), which is capable of mediating electron transfer from NADH to DesulfoVibrio gigas Rd as well as to E. coli FlRd. Furthermore, electron donation was found to proceed through the Rd domain of FlRd as the Rd-truncated protein does not react with FlRd-reductase. In vitro, this pathway links NADH oxidation with dioxygen reduction. The possible function of this chain is discussed considering the presence of FlRd homologues in all known genomes of anaerobes and facultative aerobes.

An high-speed parametric ADC and a co-designed mixer for CMOS RF receivers

Dissertação apresentada na faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para a obtenção do grau de Mestre em Engenharia Electrotécnica e de Computadores

Neutral C60 effusive source for atomic collisions with fullerene

Review of scientific instruments, Vol.72, Nº9

ALS-Sence: sistema de aquisição e processamento de electromiogramas para pacientes com ALS

Dissertação para obtenção do grau de Mestre em Engenharia de Eletrónica e Computadores

Comunicações intra- e inter-circuito de componentes especificados com Redes de Petri

Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para obtenção do Grau de Mestre em Engenharia Electrotécnica e de Computadores

Algorithm-oriented design of efficient many-core architectures applied to dense matrix multiplication

Recent integrated circuit technologies have opened the possibility to design parallel architectures with hundreds of cores on a single chip. The design space of these parallel architectures is huge with many architectural options. Exploring the design space gets even more difficult if, beyond performance and area, we also consider extra metrics like performance and area efficiency, where the designer tries to design the architecture with the best performance per chip area and the best sustainable performance. In this paper we present an algorithm-oriented approach to design a many-core architecture. Instead of doing the design space exploration of the many core architecture based on the experimental execution results of a particular benchmark of algorithms, our approach is to make a formal analysis of the algorithms considering the main architectural aspects and to determine how each particular architectural aspect is related to the performance of the architecture when running an algorithm or set of algorithms. The architectural aspects considered include the number of cores, the local memory available in each core, the communication bandwidth between the many-core architecture and the external memory and the memory hierarchy. To exemplify the approach we did a theoretical analysis of a dense matrix multiplication algorithm and determined an equation that relates the number of execution cycles with the architectural parameters. Based on this equation a many-core architecture has been designed. The results obtained indicate that a 100 mm(2) integrated circuit design of the proposed architecture, using a 65 nm technology, is able to achieve 464 GFLOPs (double precision floating-point) for a memory bandwidth of 16 GB/s. This corresponds to a performance efficiency of 71 %. Considering a 45 nm technology, a 100 mm(2) chip attains 833 GFLOPs which corresponds to 84 % of peak performance These figures are better than those obtained by previous many-core architectures, except for the area efficiency which is limited by the lower memory bandwidth considered. The results achieved are also better than those of previous state-of-the-art many-cores architectures designed specifically to achieve high performance for matrix multiplication.

NoC contention analysis using a branch-and-prune algorithm

“Many-core” systems based on a Network-on-Chip (NoC) architecture offer various opportunities in terms of performance and computing capabilities, but at the same time they pose many challenges for the deployment of real-time systems, which must fulfill specific timing requirements at runtime. It is therefore essential to identify, at design time, the parameters that have an impact on the execution time of the tasks deployed on these systems and the upper bounds on the other key parameters. The focus of this work is to determine an upper bound on the traversal time of a packet when it is transmitted over the NoC infrastructure. Towards this aim, we first identify and explore some limitations in the existing recursive-calculus-based approaches to compute the Worst-Case Traversal Time (WCTT) of a packet. Then, we extend the existing model by integrating the characteristics of the tasks that generate the packets. For this extended model, we propose an algorithm called “Branch and Prune” (BP). Our proposed method provides tighter and safe estimates than the existing recursive-calculus-based approaches. Finally, we introduce a more general approach, namely “Branch, Prune and Collapse” (BPC) which offers a configurable parameter that provides a flexible trade-off between the computational complexity and the tightness of the computed estimate. The recursive-calculus methods and BP present two special cases of BPC when a trade-off parameter is 1 or ∞, respectively. Through simulations, we analyze this trade-off, reason about the implications of certain choices, and also provide some case studies to observe the impact of task parameters on the WCTT estimates.

Person Localization Using Sensor Information Fusion

Nowadays the incredible grow of mobile devices market led to the need for location-aware applications. However, sometimes person location is difficult to obtain, since most of these devices only have a GPS (Global Positioning System) chip to retrieve location. In order to suppress this limitation and to provide location everywhere (even where a structured environment doesn’t exist) a wearable inertial navigation system is proposed, which is a convenient way to track people in situations where other localization systems fail. The system combines pedestrian dead reckoning with GPS, using widely available, low-cost and low-power hardware components. The system innovation is the information fusion and the use of probabilistic methods to learn persons gait behavior to correct, in real-time, the drift errors given by the sensors.