Run-Time Scalable Hardware for Reconfigurable Systems

La optimización de parámetros tales como el consumo de potencia, la cantidad de recursos lógicos empleados o la ocupación de memoria ha sido siempre una de las preocupaciones principales a la hora de diseñar sistemas embebidos. Esto es debido a que se trata de sistemas dotados de una cantidad de recursos limitados, y que han sido tradicionalmente empleados para un propósito específico, que permanece invariable a lo largo de toda la vida útil del sistema. Sin embargo, el uso de sistemas embebidos se ha extendido a áreas de aplicación fuera de su ámbito tradicional, caracterizadas por una mayor demanda computacional. Así, por ejemplo, algunos de estos sistemas deben llevar a cabo un intenso procesado de señales multimedia o la transmisión de datos mediante sistemas de comunicaciones de alta capacidad. Por otra parte, las condiciones de operación del sistema pueden variar en tiempo real. Esto sucede, por ejemplo, si su funcionamiento depende de datos medidos por el propio sistema o recibidos a través de la red, de las demandas del usuario en cada momento, o de condiciones internas del propio dispositivo, tales como la duración de la batería. Como consecuencia de la existencia de requisitos de operación dinámicos es necesario ir hacia una gestión dinámica de los recursos del sistema. Si bien el software es inherentemente flexible, no ofrece una potencia computacional tan alta como el hardware. Por lo tanto, el hardware reconfigurable aparece como una solución adecuada para tratar con mayor flexibilidad los requisitos variables dinámicamente en sistemas con alta demanda computacional. La flexibilidad y adaptabilidad del hardware requieren de dispositivos reconfigurables que permitan la modificación de su funcionalidad bajo demanda. En esta tesis se han seleccionado las FPGAs (Field Programmable Gate Arrays) como los dispositivos más apropiados, hoy en día, para implementar sistemas basados en hardware reconfigurable De entre todas las posibilidades existentes para explotar la capacidad de reconfiguración de las FPGAs comerciales, se ha seleccionado la reconfiguración dinámica y parcial. Esta técnica consiste en substituir una parte de la lógica del dispositivo, mientras el resto continúa en funcionamiento. La capacidad de reconfiguración dinámica y parcial de las FPGAs es empleada en esta tesis para tratar con los requisitos de flexibilidad y de capacidad computacional que demandan los dispositivos embebidos. La propuesta principal de esta tesis doctoral es el uso de arquitecturas de procesamiento escalables espacialmente, que son capaces de adaptar su funcionalidad y rendimiento en tiempo real, estableciendo un compromiso entre dichos parámetros y la cantidad de lógica que ocupan en el dispositivo. A esto nos referimos con arquitecturas con huellas escalables. En particular, se propone el uso de arquitecturas altamente paralelas, modulares, regulares y con una alta localidad en sus comunicaciones, para este propósito. El tamaño de dichas arquitecturas puede ser modificado mediante la adición o eliminación de algunos de los módulos que las componen, tanto en una dimensión como en dos. Esta estrategia permite implementar soluciones escalables, sin tener que contar con una versión de las mismas para cada uno de los tamaños posibles de la arquitectura. De esta manera se reduce significativamente el tiempo necesario para modificar su tamaño, así como la cantidad de memoria necesaria para almacenar todos los archivos de configuración. En lugar de proponer arquitecturas para aplicaciones específicas, se ha optado por patrones de procesamiento genéricos, que pueden ser ajustados para solucionar distintos problemas en el estado del arte. A este respecto, se proponen patrones basados en esquemas sistólicos, así como de tipo wavefront. Con el objeto de poder ofrecer una solución integral, se han tratado otros aspectos relacionados con el diseño y el funcionamiento de las arquitecturas, tales como el control del proceso de reconfiguración de la FPGA, la integración de las arquitecturas en el resto del sistema, así como las técnicas necesarias para su implementación. Por lo que respecta a la implementación, se han tratado distintos aspectos de bajo nivel dependientes del dispositivo. Algunas de las propuestas realizadas a este respecto en la presente tesis doctoral son un router que es capaz de garantizar el correcto rutado de los módulos reconfigurables dentro del área destinada para ellos, así como una estrategia para la comunicación entre módulos que no introduce ningún retardo ni necesita emplear recursos configurables del dispositivo. El flujo de diseño propuesto se ha automatizado mediante una herramienta denominada DREAMS. La herramienta se encarga de la modificación de las netlists correspondientes a cada uno de los módulos reconfigurables del sistema, y que han sido generadas previamente mediante herramientas comerciales. Por lo tanto, el flujo propuesto se entiende como una etapa de post-procesamiento, que adapta esas netlists a los requisitos de la reconfiguración dinámica y parcial. Dicha modificación la lleva a cabo la herramienta de una forma completamente automática, por lo que la productividad del proceso de diseño aumenta de forma evidente. Para facilitar dicho proceso, se ha dotado a la herramienta de una interfaz gráfica. El flujo de diseño propuesto, y la herramienta que lo soporta, tienen características específicas para abordar el diseño de las arquitecturas dinámicamente escalables propuestas en esta tesis. Entre ellas está el soporte para el realojamiento de módulos reconfigurables en posiciones del dispositivo distintas a donde el módulo es originalmente implementado, así como la generación de estructuras de comunicación compatibles con la simetría de la arquitectura. El router has sido empleado también en esta tesis para obtener un rutado simétrico entre nets equivalentes. Dicha posibilidad ha sido explotada para aumentar la protección de circuitos con altos requisitos de seguridad, frente a ataques de canal lateral, mediante la implantación de lógica complementaria con rutado idéntico. Para controlar el proceso de reconfiguración de la FPGA, se propone en esta tesis un motor de reconfiguración especialmente adaptado a los requisitos de las arquitecturas dinámicamente escalables. Además de controlar el puerto de reconfiguración, el motor de reconfiguración ha sido dotado de la capacidad de realojar módulos reconfigurables en posiciones arbitrarias del dispositivo, en tiempo real. De esta forma, basta con generar un único bitstream por cada módulo reconfigurable del sistema, independientemente de la posición donde va a ser finalmente reconfigurado. La estrategia seguida para implementar el proceso de realojamiento de módulos es diferente de las propuestas existentes en el estado del arte, pues consiste en la composición de los archivos de configuración en tiempo real. De esta forma se consigue aumentar la velocidad del proceso, mientras que se reduce la longitud de los archivos de configuración parciales a almacenar en el sistema. El motor de reconfiguración soporta módulos reconfigurables con una altura menor que la altura de una región de reloj del dispositivo. Internamente, el motor se encarga de la combinación de los frames que describen el nuevo módulo, con la configuración existente en el dispositivo previamente. El escalado de las arquitecturas de procesamiento propuestas en esta tesis también se puede beneficiar de este mecanismo. Se ha incorporado también un acceso directo a una memoria externa donde se pueden almacenar bitstreams parciales. Para acelerar el proceso de reconfiguración se ha hecho funcionar el ICAP por encima de la máxima frecuencia de reloj aconsejada por el fabricante. Así, en el caso de Virtex-5, aunque la máxima frecuencia del reloj deberían ser 100 MHz, se ha conseguido hacer funcionar el puerto de reconfiguración a frecuencias de operación de hasta 250 MHz, incluyendo el proceso de realojamiento en tiempo real. Se ha previsto la posibilidad de portar el motor de reconfiguración a futuras familias de FPGAs. Por otro lado, el motor de reconfiguración se puede emplear para inyectar fallos en el propio dispositivo hardware, y así ser capaces de evaluar la tolerancia ante los mismos que ofrecen las arquitecturas reconfigurables. Los fallos son emulados mediante la generación de archivos de configuración a los que intencionadamente se les ha introducido un error, de forma que se modifica su funcionalidad. Con el objetivo de comprobar la validez y los beneficios de las arquitecturas propuestas en esta tesis, se han seguido dos líneas principales de aplicación. En primer lugar, se propone su uso como parte de una plataforma adaptativa basada en hardware evolutivo, con capacidad de escalabilidad, adaptabilidad y recuperación ante fallos. En segundo lugar, se ha desarrollado un deblocking filter escalable, adaptado a la codificación de vídeo escalable, como ejemplo de aplicación de las arquitecturas de tipo wavefront propuestas. El hardware evolutivo consiste en el uso de algoritmos evolutivos para diseñar hardware de forma autónoma, explotando la flexibilidad que ofrecen los dispositivos reconfigurables. En este caso, los elementos de procesamiento que componen la arquitectura son seleccionados de una biblioteca de elementos presintetizados, de acuerdo con las decisiones tomadas por el algoritmo evolutivo, en lugar de definir la configuración de las mismas en tiempo de diseño. De esta manera, la configuración del core puede cambiar cuando lo hacen las condiciones del entorno, en tiempo real, por lo que se consigue un control autónomo del proceso de reconfiguración dinámico. Así, el sistema es capaz de optimizar, de forma autónoma, su propia configuración. El hardware evolutivo tiene una capacidad inherente de auto-reparación. Se ha probado que las arquitecturas evolutivas propuestas en esta tesis son tolerantes ante fallos, tanto transitorios, como permanentes y acumulativos. La plataforma evolutiva se ha empleado para implementar filtros de eliminación de ruido. La escalabilidad también ha sido aprovechada en esta aplicación. Las arquitecturas evolutivas escalables permiten la adaptación autónoma de los cores de procesamiento ante fluctuaciones en la cantidad de recursos disponibles en el sistema. Por lo tanto, constituyen un ejemplo de escalabilidad dinámica para conseguir un determinado nivel de calidad, que puede variar en tiempo real. Se han propuesto dos variantes de sistemas escalables evolutivos. El primero consiste en un único core de procesamiento evolutivo, mientras que el segundo está formado por un número variable de arrays de procesamiento. La codificación de vídeo escalable, a diferencia de los codecs no escalables, permite la decodificación de secuencias de vídeo con diferentes niveles de calidad, de resolución temporal o de resolución espacial, descartando la información no deseada. Existen distintos algoritmos que soportan esta característica. En particular, se va a emplear el estándar Scalable Video Coding (SVC), que ha sido propuesto como una extensión de H.264/AVC, ya que este último es ampliamente utilizado tanto en la industria, como a nivel de investigación. Para poder explotar toda la flexibilidad que ofrece el estándar, hay que permitir la adaptación de las características del decodificador en tiempo real. El uso de las arquitecturas dinámicamente escalables es propuesto en esta tesis con este objetivo. El deblocking filter es un algoritmo que tiene como objetivo la mejora de la percepción visual de la imagen reconstruida, mediante el suavizado de los "artefactos" de bloque generados en el lazo del codificador. Se trata de una de las tareas más intensivas en procesamiento de datos de H.264/AVC y de SVC, y además, su carga computacional es altamente dependiente del nivel de escalabilidad seleccionado en el decodificador. Por lo tanto, el deblocking filter ha sido seleccionado como prueba de concepto de la aplicación de las arquitecturas dinámicamente escalables para la compresión de video. La arquitectura propuesta permite añadir o eliminar unidades de computación, siguiendo un esquema de tipo wavefront. La arquitectura ha sido propuesta conjuntamente con un esquema de procesamiento en paralelo del deblocking filter a nivel de macrobloque, de tal forma que cuando se varía del tamaño de la arquitectura, el orden de filtrado de los macrobloques varia de la misma manera. El patrón propuesto se basa en la división del procesamiento de cada macrobloque en dos etapas independientes, que se corresponden con el filtrado horizontal y vertical de los bloques dentro del macrobloque. Las principales contribuciones originales de esta tesis son las siguientes: - El uso de arquitecturas altamente regulares, modulares, paralelas y con una intensa localidad en sus comunicaciones, para implementar cores de procesamiento dinámicamente reconfigurables. - El uso de arquitecturas bidimensionales, en forma de malla, para construir arquitecturas dinámicamente escalables, con una huella escalable. De esta forma, las arquitecturas permiten establecer un compromiso entre el área que ocupan en el dispositivo, y las prestaciones que ofrecen en cada momento. Se proponen plantillas de procesamiento genéricas, de tipo sistólico o wavefront, que pueden ser adaptadas a distintos problemas de procesamiento. - Un flujo de diseño y una herramienta que lo soporta, para el diseño de sistemas reconfigurables dinámicamente, centradas en el diseño de las arquitecturas altamente paralelas, modulares y regulares propuestas en esta tesis. - Un esquema de comunicaciones entre módulos reconfigurables que no introduce ningún retardo ni requiere el uso de recursos lógicos propios. - Un router flexible, capaz de resolver los conflictos de rutado asociados con el diseño de sistemas reconfigurables dinámicamente. - Un algoritmo de optimización para sistemas formados por múltiples cores escalables que optimice, mediante un algoritmo genético, los parámetros de dicho sistema. Se basa en un modelo conocido como el problema de la mochila. - Un motor de reconfiguración adaptado a los requisitos de las arquitecturas altamente regulares y modulares. Combina una alta velocidad de reconfiguración, con la capacidad de realojar módulos en tiempo real, incluyendo el soporte para la reconfiguración de regiones que ocupan menos que una región de reloj, así como la réplica de un módulo reconfigurable en múltiples posiciones del dispositivo. - Un mecanismo de inyección de fallos que, empleando el motor de reconfiguración del sistema, permite evaluar los efectos de fallos permanentes y transitorios en arquitecturas reconfigurables. - La demostración de las posibilidades de las arquitecturas propuestas en esta tesis para la implementación de sistemas de hardware evolutivos, con una alta capacidad de procesamiento de datos. - La implementación de sistemas de hardware evolutivo escalables, que son capaces de tratar con la fluctuación de la cantidad de recursos disponibles en el sistema, de una forma autónoma. - Una estrategia de procesamiento en paralelo para el deblocking filter compatible con los estándares H.264/AVC y SVC que reduce el número de ciclos de macrobloque necesarios para procesar un frame de video. - Una arquitectura dinámicamente escalable que permite la implementación de un nuevo deblocking filter, totalmente compatible con los estándares H.264/AVC y SVC, que explota el paralelismo a nivel de macrobloque. El presente documento se organiza en siete capítulos. En el primero se ofrece una introducción al marco tecnológico de esta tesis, especialmente centrado en la reconfiguración dinámica y parcial de FPGAs. También se motiva la necesidad de las arquitecturas dinámicamente escalables propuestas en esta tesis. En el capítulo 2 se describen las arquitecturas dinámicamente escalables. Dicha descripción incluye la mayor parte de las aportaciones a nivel arquitectural realizadas en esta tesis. Por su parte, el flujo de diseño adaptado a dichas arquitecturas se propone en el capítulo 3. El motor de reconfiguración se propone en el 4, mientras que el uso de dichas arquitecturas para implementar sistemas de hardware evolutivo se aborda en el 5. El deblocking filter escalable se describe en el 6, mientras que las conclusiones finales de esta tesis, así como la descripción del trabajo futuro, son abordadas en el capítulo 7. ABSTRACT The optimization of system parameters, such as power dissipation, the amount of hardware resources and the memory footprint, has been always a main concern when dealing with the design of resource-constrained embedded systems. This situation is even more demanding nowadays. Embedded systems cannot anymore be considered only as specific-purpose computers, designed for a particular functionality that remains unchanged during their lifetime. Differently, embedded systems are now required to deal with more demanding and complex functions, such as multimedia data processing and high-throughput connectivity. In addition, system operation may depend on external data, the user requirements or internal variables of the system, such as the battery life-time. All these conditions may vary at run-time, leading to adaptive scenarios. As a consequence of both the growing computational complexity and the existence of dynamic requirements, dynamic resource management techniques for embedded systems are needed. Software is inherently flexible, but it cannot meet the computing power offered by hardware solutions. Therefore, reconfigurable hardware emerges as a suitable technology to deal with the run-time variable requirements of complex embedded systems. Adaptive hardware requires the use of reconfigurable devices, where its functionality can be modified on demand. In this thesis, Field Programmable Gate Arrays (FPGAs) have been selected as the most appropriate commercial technology existing nowadays to implement adaptive hardware systems. There are different ways of exploiting reconfigurability in reconfigurable devices. Among them is dynamic and partial reconfiguration. This is a technique which consists in substituting part of the FPGA logic on demand, while the rest of the device continues working. The strategy followed in this thesis is to exploit the dynamic and partial reconfiguration of commercial FPGAs to deal with the flexibility and complexity demands of state-of-the-art embedded systems. The proposal of this thesis to deal with run-time variable system conditions is the use of spatially scalable processing hardware IP cores, which are able to adapt their functionality or performance at run-time, trading them off with the amount of logic resources they occupy in the device. This is referred to as a scalable footprint in the context of this thesis. The distinguishing characteristic of the proposed cores is that they rely on highly parallel, modular and regular architectures, arranged in one or two dimensions. These architectures can be scaled by means of the addition or removal of the composing blocks. This strategy avoids implementing a full version of the core for each possible size, with the corresponding benefits in terms of scaling and adaptation time, as well as bitstream storage memory requirements. Instead of providing specific-purpose architectures, generic architectural templates, which can be tuned to solve different problems, are proposed in this thesis. Architectures following both systolic and wavefront templates have been selected. Together with the proposed scalable architectural templates, other issues needed to ensure the proper design and operation of the scalable cores, such as the device reconfiguration control, the run-time management of the architecture and the implementation techniques have been also addressed in this thesis. With regard to the implementation of dynamically reconfigurable architectures, device dependent low-level details are addressed. Some of the aspects covered in this thesis are the area constrained routing for reconfigurable modules, or an inter-module communication strategy which does not introduce either extra delay or logic overhead. The system implementation, from the hardware description to the device configuration bitstream, has been fully automated by modifying the netlists corresponding to each of the system modules, which are previously generated using the vendor tools. This modification is therefore envisaged as a post-processing step. Based on these implementation proposals, a design tool called DREAMS (Dynamically Reconfigurable Embedded and Modular Systems) has been created, including a graphic user interface. The tool has specific features to cope with modular and regular architectures, including the support for module relocation and the inter-module communications scheme based on the symmetry of the architecture. The core of the tool is a custom router, which has been also exploited in this thesis to obtain symmetric routed nets, with the aim of enhancing the protection of critical reconfigurable circuits against side channel attacks. This is achieved by duplicating the logic with an exactly equal routing. In order to control the reconfiguration process of the FPGA, a Reconfiguration Engine suited to the specific requirements set by the proposed architectures was also proposed. Therefore, in addition to controlling the reconfiguration port, the Reconfiguration Engine has been enhanced with the online relocation ability, which allows employing a unique configuration bitstream for all the positions where the module may be placed in the device. Differently to the existing relocating solutions, which are based on bitstream parsers, the proposed approach is based on the online composition of bitstreams. This strategy allows increasing the speed of the process, while the length of partial bitstreams is also reduced. The height of the reconfigurable modules can be lower than the height of a clock region. The Reconfiguration Engine manages the merging process of the new and the existing configuration frames within each clock region. The process of scaling up and down the hardware cores also benefits from this technique. A direct link to an external memory where partial bitstreams can be stored has been also implemented. In order to accelerate the reconfiguration process, the ICAP has been overclocked over the speed reported by the manufacturer. In the case of Virtex-5, even though the maximum frequency of the ICAP is reported to be 100 MHz, valid operations at 250 MHz have been achieved, including the online relocation process. Portability of the reconfiguration solution to today's and probably, future FPGAs, has been also considered. The reconfiguration engine can be also used to inject faults in real hardware devices, and this way being able to evaluate the fault tolerance offered by the reconfigurable architectures. Faults are emulated by introducing partial bitstreams intentionally modified to provide erroneous functionality. To prove the validity and the benefits offered by the proposed architectures, two demonstration application lines have been envisaged. First, scalable architectures have been employed to develop an evolvable hardware platform with adaptability, fault tolerance and scalability properties. Second, they have been used to implement a scalable deblocking filter suited to scalable video coding. Evolvable Hardware is the use of evolutionary algorithms to design hardware in an autonomous way, exploiting the flexibility offered by reconfigurable devices. In this case, processing elements composing the architecture are selected from a presynthesized library of processing elements, according to the decisions taken by the algorithm, instead of being decided at design time. This way, the configuration of the array may change as run-time environmental conditions do, achieving autonomous control of the dynamic reconfiguration process. Thus, the self-optimization property is added to the native self-configurability of the dynamically scalable architectures. In addition, evolvable hardware adaptability inherently offers self-healing features. The proposal has proved to be self-tolerant, since it is able to self-recover from both transient and cumulative permanent faults. The proposed evolvable architecture has been used to implement noise removal image filters. Scalability has been also exploited in this application. Scalable evolvable hardware architectures allow the autonomous adaptation of the processing cores to a fluctuating amount of resources available in the system. Thus, it constitutes an example of the dynamic quality scalability tackled in this thesis. Two variants have been proposed. The first one consists in a single dynamically scalable evolvable core, and the second one contains a variable number of processing cores. Scalable video is a flexible approach for video compression, which offers scalability at different levels. Differently to non-scalable codecs, a scalable video bitstream can be decoded with different levels of quality, spatial or temporal resolutions, by discarding the undesired information. The interest in this technology has been fostered by the development of the Scalable Video Coding (SVC) standard, as an extension of H.264/AVC. In order to exploit all the flexibility offered by the standard, it is necessary to adapt the characteristics of the decoder to the requirements of each client during run-time. The use of dynamically scalable architectures is proposed in this thesis with this aim. The deblocking filter algorithm is the responsible of improving the visual perception of a reconstructed image, by smoothing blocking artifacts generated in the encoding loop. This is one of the most computationally intensive tasks of the standard, and furthermore, it is highly dependent on the selected scalability level in the decoder. Therefore, the deblocking filter has been selected as a proof of concept of the implementation of dynamically scalable architectures for video compression. The proposed architecture allows the run-time addition or removal of computational units working in parallel to change its level of parallelism, following a wavefront computational pattern. Scalable architecture is offered together with a scalable parallelization strategy at the macroblock level, such that when the size of the architecture changes, the macroblock filtering order is modified accordingly. The proposed pattern is based on the division of the macroblock processing into two independent stages, corresponding to the horizontal and vertical filtering of the blocks within the macroblock. The main contributions of this thesis are: - The use of highly parallel, modular, regular and local architectures to implement dynamically reconfigurable processing IP cores, for data intensive applications with flexibility requirements. - The use of two-dimensional mesh-type arrays as architectural templates to build dynamically reconfigurable IP cores, with a scalable footprint. The proposal consists in generic architectural templates, which can be tuned to solve different computational problems. •A design flow and a tool targeting the design of DPR systems, focused on highly parallel, modular and local architectures. - An inter-module communication strategy, which does not introduce delay or area overhead, named Virtual Borders. - A custom and flexible router to solve the routing conflicts as well as the inter-module communication problems, appearing during the design of DPR systems. - An algorithm addressing the optimization of systems composed of multiple scalable cores, which size can be decided individually, to optimize the system parameters. It is based on a model known as the multi-dimensional multi-choice Knapsack problem. - A reconfiguration engine tailored to the requirements of highly regular and modular architectures. It combines a high reconfiguration throughput with run-time module relocation capabilities, including the support for sub-clock reconfigurable regions and the replication in multiple positions. - A fault injection mechanism which takes advantage of the system reconfiguration engine, as well as the modularity of the proposed reconfigurable architectures, to evaluate the effects of transient and permanent faults in these architectures. - The demonstration of the possibilities of the architectures proposed in this thesis to implement evolvable hardware systems, while keeping a high processing throughput. - The implementation of scalable evolvable hardware systems, which are able to adapt to the fluctuation of the amount of resources available in the system, in an autonomous way. - A parallelization strategy for the H.264/AVC and SVC deblocking filter, which reduces the number of macroblock cycles needed to process the whole frame. - A dynamically scalable architecture that permits the implementation of a novel deblocking filter module, fully compliant with the H.264/AVC and SVC standards, which exploits the macroblock level parallelism of the algorithm. This document is organized in seven chapters. In the first one, an introduction to the technology framework of this thesis, specially focused on dynamic and partial reconfiguration, is provided. The need for the dynamically scalable processing architectures proposed in this work is also motivated in this chapter. In chapter 2, dynamically scalable architectures are described. Description includes most of the architectural contributions of this work. The design flow tailored to the scalable architectures, together with the DREAMs tool provided to implement them, are described in chapter 3. The reconfiguration engine is described in chapter 4. The use of the proposed scalable archtieectures to implement evolvable hardware systems is described in chapter 5, while the scalable deblocking filter is described in chapter 6. Final conclusions of this thesis, and the description of future work, are addressed in chapter 7.

A 2D computational parametric analysis of the sheltering effect of fences on a railway vehicle standing on a bridge and experiencing crosswinds

In a crosswind scenario, the risk of high-speed trains overturning increases when they run on viaducts since the aerodynamic loads are higher than on the ground. In order to increase safety, vehicles are sheltered by fences that are installed on the viaduct to reduce the loads experienced by the train. Windbreaks can be designed to have different heights, and with or without eaves on the top. In this paper, a parametric study with a total of 12 fence designs was carried out using a two-dimensional model of a train standing on a viaduct. To asses the relative effectiveness of sheltering devices, tests were done in a wind tunnel with a scaled model at a Reynolds number of 1 × 105, and the train’s aerodynamic coefficients were measured. Experimental results were compared with those predicted by Unsteady Reynolds-averaged Navier-Stokes (URANS) simulations of flow, showing that a computational model is able to satisfactorily predict the trend of the aerodynamic coefficients. In a second set of tests, the Reynolds number was increased to 12 × 106 (at a free flow air velocity of 30 m/s) in order to simulate strong wind conditions. The aerodynamic coefficients showed a similar trend for both Reynolds numbers; however, their numerical value changed enough to indicate that simulations at the lower Reynolds number do not provide all required information. Furthermore, the variation of coefficients in the simulations allowed an explanation of how fences modified the flow around the vehicle to be proposed. This made it clear why increasing fence height reduced all the coefficients but adding an eave had an effect mainly on the lift force coefficient. Finally, by analysing the time signals it was possible to clarify the influence of the Reynolds number on the peak-to-peak amplitude, the time period and the Strouhal number.

Comparative study about the use of two and three-dimensional methods in surface finishing characterization

The increasing number of works related to the surface texture characterization based on 3D information, makes convenient rethinking traditional methods based on two-dimensional measurements from profiles. This work compares results between measurements obtained using two and three-dimensional methods. It uses three kinds of data sources: reference surfaces, randomly generated surfaces and measured. Preliminary results are presented. These results must be completed trying to cover a wider number of possibilities according to the manufacturing process and the measurement instrumentation since results can vary quite significantly between them.

Providing 3D video services: the challenge from 2D to 3DTV quality of experience

Recently, three-dimensional (3D) video has decisively burst onto the entertainment industry scene, and has arrived in households even before the standardization process has been completed. 3D television (3DTV) adoption and deployment can be seen as a major leap in television history, similar to previous transitions from black and white (B&W) to color, from analog to digital television (TV), and from standard definition to high definition. In this paper, we analyze current 3D video technology trends in order to define a taxonomy of the availability and possible introduction of 3D-based services. We also propose an audiovisual network services architecture which provides a smooth transition from two-dimensional (2D) to 3DTV in an Internet Protocol (IP)-based scenario. Based on subjective assessment tests, we also analyze those factors which will influence the quality of experience in those 3D video services, focusing on effects of both coding and transmission errors. In addition, examples of the application of the architecture and results of assessment tests are provided.

Real-time determination of airspace wind speed field based on FDR = Determinación en tiempo real del campo de velocidad del viento basado en registradores de datos de vuelo

El estudio del comportamiento de la atmósfera ha resultado de especial importancia tanto en el programa SESAR como en NextGen, en los que la gestión actual del tránsito aéreo (ATM) está experimentando una profunda transformación hacia nuevos paradigmas tanto en Europa como en los EE.UU., respectivamente, para el guiado y seguimiento de las aeronaves en la realización de rutas más eficientes y con mayor precisión. La incertidumbre es una característica fundamental de los fenómenos meteorológicos que se transfiere a la separación de las aeronaves, las trayectorias de vuelo libres de conflictos y a la planificación de vuelos. En este sentido, el viento es un factor clave en cuanto a la predicción de la futura posición de la aeronave, por lo que tener un conocimiento más profundo y preciso de campo de viento reducirá las incertidumbres del ATC. El objetivo de esta tesis es el desarrollo de una nueva técnica operativa y útil destinada a proporcionar de forma adecuada y directa el campo de viento atmosférico en tiempo real, basada en datos de a bordo de la aeronave, con el fin de mejorar la predicción de las trayectorias de las aeronaves. Para lograr este objetivo se ha realizado el siguiente trabajo. Se han descrito y analizado los diferentes sistemas de la aeronave que proporcionan las variables necesarias para obtener la velocidad del viento, así como de las capacidades que permiten la presentación de esta información para sus aplicaciones en la gestión del tráfico aéreo. Se ha explorado el uso de aeronaves como los sensores de viento en un área terminal para la estimación del viento en tiempo real con el fin de mejorar la predicción de las trayectorias de aeronaves. Se han desarrollado métodos computacionalmente eficientes para estimar las componentes horizontales de la velocidad del viento a partir de las velocidades de las aeronaves (VGS, VCAS/VTAS), la presión y datos de temperatura. Estos datos de viento se han utilizado para estimar el campo de viento en tiempo real utilizando un sistema de procesamiento de datos a través de un método de mínima varianza. Por último, se ha evaluado la exactitud de este procedimiento para que esta información sea útil para el control del tráfico aéreo. La información inicial proviene de una muestra de datos de Registradores de Datos de Vuelo (FDR) de aviones que aterrizaron en el aeropuerto Madrid-Barajas. Se dispuso de datos de ciertas aeronaves durante un periodo de más de tres meses que se emplearon para calcular el vector viento en cada punto del espacio aéreo. Se utilizó un modelo matemático basado en diferentes métodos de interpolación para obtener los vectores de viento en áreas sin datos disponibles. Se han utilizado tres escenarios concretos para validar dos métodos de interpolación: uno de dos dimensiones que trabaja con ambas componentes horizontales de forma independiente, y otro basado en el uso de una variable compleja que relaciona ambas componentes. Esos métodos se han probado en diferentes escenarios con resultados dispares. Esta metodología se ha aplicado en un prototipo de herramienta en MATLAB © para analizar automáticamente los datos de FDR y determinar el campo vectorial del viento que encuentra la aeronave al volar en el espacio aéreo en estudio. Finalmente se han obtenido las condiciones requeridas y la precisión de los resultados para este modelo. El método desarrollado podría utilizar los datos de los aviones comerciales como inputs utilizando los datos actualmente disponibles y la capacidad computacional, para proporcionárselos a los sistemas ATM donde se podría ejecutar el método propuesto. Estas velocidades del viento calculadas, o bien la velocidad respecto al suelo y la velocidad verdadera, se podrían difundir, por ejemplo, a través del sistema de direccionamiento e informe para comunicaciones de aeronaves (ACARS), mensajes de ADS-B o Modo S. Esta nueva fuente ayudaría a actualizar la información del viento suministrada en los productos aeronáuticos meteorológicos (PAM), informes meteorológicos de aeródromos (AIRMET), e información meteorológica significativa (SIGMET). ABSTRACT The study of the atmosphere behaviour is been of particular importance both in SESAR and NextGen programs, where the current air traffic management (ATM) system is undergoing a profound transformation to the new paradigms both in Europe and the USA, respectively, to guide and track aircraft more precisely on more efficient routes. Uncertainty is a fundamental characteristic of weather phenomena which is transferred to separation assurance, flight path de-confliction and flight planning applications. In this respect, the wind is a key factor regarding the prediction of the future position of the aircraft, so that having a deeper and accurate knowledge of wind field will reduce ATC uncertainties. The purpose of this thesis is to develop a new and operationally useful technique intended to provide adequate and direct real-time atmospheric winds fields based on on-board aircraft data, in order to improve aircraft trajectory prediction. In order to achieve this objective the following work has been accomplished. The different sources in the aircraft systems that provide the variables needed to derivate the wind velocity have been described and analysed, as well as the capabilities which allow presenting this information for air traffic management applications. The use of aircraft as wind sensors in a terminal area for real-time wind estimation in order to improve aircraft trajectory prediction has been explored. Computationally efficient methods have been developed to estimate horizontal wind components from aircraft velocities (VGS, VCAS/VTAS), pressure, and temperature data. These wind data were utilized to estimate a real-time wind field using a data processing approach through a minimum variance method. Finally, the accuracy of this procedure has been evaluated for this information to be useful to air traffic control. The initial information comes from a Flight Data Recorder (FDR) sample of aircraft landing in Madrid-Barajas Airport. Data available for more than three months were exploited in order to derive the wind vector field in each point of the airspace. Mathematical model based on different interpolation methods were used in order to obtain wind vectors in void areas. Three particular scenarios were employed to test two interpolation methods: a two-dimensional one that works with both horizontal components in an independent way, and also a complex variable formulation that links both components. Those methods were tested using various scenarios with dissimilar results. This methodology has been implemented in a prototype tool in MATLAB © in order to automatically analyse FDR and determine the wind vector field that aircraft encounter when flying in the studied airspace. Required conditions and accuracy of the results were derived for this model. The method developed could be fed by commercial aircraft utilizing their currently available data sources and computational capabilities, and providing them to ATM system where the proposed method could be run. Computed wind velocities, or ground and true airspeeds, would then be broadcasted, for example, via the Aircraft Communication Addressing and Reporting System (ACARS), ADS-B out messages, or Mode S. This new source would help updating the wind information furnished in meteorological aeronautical products (PAM), meteorological aerodrome reports (AIRMET), and significant meteorological information (SIGMET).

Estudio de las distribuciones tensionales y de las resistencias de los rellenos de pasta de la mina subterránea de Aguas Teñidas (Huelva)

This thesis presents the study carried out at an underground mine to understand the stress distribution in the paste fills and to calculate the stability of the paste walls in the primary and secondary stopes. The mine is operated using sublevel stopes and fan blasting. The primary and secondary stopes are 20m wide, 30m high and between 20 and 60m long. Three-dimensional numerical models designed with the FLAC 3D software programme are used to study the distribution of the vertical stresses in the paste walls exposed in the primary and secondary stopes, and their evolution as the mining advance increases. The numerical models have demonstrated that an arc-like effect is produced in the paste fills of the primary stopes, that is, those which have either lateral walls in mineral or rock. This effect relieves the vertical stresses and increases the stability of the exposed paste wall fill. From the study, it is deduced that in this type of stope, the fill stability can be calculated using the formula established by Mitchell, (Mitchell, Olsen, and Smith 1982, 14-28). Based on the results of the numerical models, in the 30m high secondary stopes, the arc effect starts to be evident only in paste walls with a width/height ratio lower than 0.7. 3-D calculations show that the use of Mitchell formula may be risky when estimating the fill stability in secondary stopes. Therefore, in these cases, the traditional two-dimensional method for calculating the stability of vertical slopes on cohesive saturated soils in the short term should be used. However this method may give conservative results for paste walls in secondary stopes with a width/height ratio below 0.5. RESUMEN Esta Tesis presenta el estudio realizado en la mina subterránea de Aguas Teñidas (Huelva, España) para comprender la distribución de tensiones en los rellenos de pasta y calcular la estabilidad de las paredes de pasta en las cámaras primarias y secundarias. El método de explotación utilizado en esta mina es el de cámaras con subniveles y voladura en abanico. Las cámaras primarias y secundarias tienen una anchura de 20 m, una altura de 30 m y una longitud variable entre 20 y 60 m. Mediante modelos numéricos tridimensionales realizados con el programa FLAC 3D se ha estudiado la distribución de las tensiones verticales en las paredes de pasta que quedan expuestas en las cámaras primarias y secundarias, y su evolución a medida que aumenta la superficie explotada. La modelización numérica ha puesto de manifiesto que se produce efecto arco en los rellenos de pasta de las cámaras primarias, o sea, aquellas que tienen ambos hastiales en mineral o en roca. Este efecto aligera las tensiones verticales y aumenta la estabilidad del relleno de la pared de pasta expuesta. De acuerdo con los resultados de los modelos numéricos, en las cámaras secundarias de 30 m de alto, el efecto arco empieza a manifestarse solamente en las paredes de pasta de relación anchura/altura menor de 0,7. Los cálculos realizados en tres dimensiones indican que la fórmula de Mitchell (Mitchell, Olsen, y Smith 1982, 14-28) puede resultar arriesgada para estimar la estabilidad del relleno en este tipo de cámaras. Por consiguiente, se recomienda utilizar en estos casos el método que tradicionalmente se ha empleado para calcular la estabilidad de taludes verticales en suelos cohesivos a corto plazo, en dos dimensiones. Aunque este método puede resultar conservador para paredes de pasta de cámaras secundarias con una relación anchura/altura inferior a 0,5. Para usar relleno de pasta para el sostenimiento en minería subterránea hay que tener en cuenta el cálculo de los parámetros de diseño, optimización de la mezcla, cualidades de bombeo y la operación de transporte al interior de la mina. Los gastos de ésta operación minera son importantes ya que pueden representar hasta de 20%.

NMR scalar couplings across Watson–Crick base pair hydrogen bonds in DNA observed by transverse relaxation-optimized spectroscopy

This paper describes the NMR observation of 15N—15N and 1H—15N scalar couplings across the hydrogen bonds in Watson–Crick base pairs in a DNA duplex, hJNN and hJHN. These couplings represent new parameters of interest for both structural studies of DNA and theoretical investigations into the nature of the hydrogen bonds. Two dimensional [15N,1H]-transverse relaxation-optimized spectroscopy (TROSY) with a 15N-labeled 14-mer DNA duplex was used to measure hJNN, which is in the range 6–7 Hz, and the two-dimensional hJNN-correlation-[15N,1H]-TROSY experiment was used to correlate the chemical shifts of pairs of hydrogen bond-related 15N spins and to observe, for the first time, hJHN scalar couplings, with values in the range 2–3.6 Hz. TROSY-based studies of scalar couplings across hydrogen bonds should be applicable for large molecular sizes, including protein-bound nucleic acids.

Adjoint modular Galois representations and their Selmer groups

In the last 15 years, many class number formulas and main conjectures have been proven. Here, we discuss such formulas on the Selmer groups of the three-dimensional adjoint representation ad(φ) of a two-dimensional modular Galois representation φ. We start with the p-adic Galois representation φ0 of a modular elliptic curve E and present a formula expressing in terms of L(1, ad(φ0)) the intersection number of the elliptic curve E and the complementary abelian variety inside the Jacobian of the modular curve. Then we explain how one can deduce a formula for the order of the Selmer group Sel(ad(φ0)) from the proof of Wiles of the Shimura–Taniyama conjecture. After that, we generalize the formula in an Iwasawa theoretic setting of one and two variables. Here the first variable, T, is the weight variable of the universal p-ordinary Hecke algebra, and the second variable is the cyclotomic variable S. In the one-variable case, we let φ denote the p-ordinary Galois representation with values in GL2(Zp[[T]]) lifting φ0, and the characteristic power series of the Selmer group Sel(ad(φ)) is given by a p-adic L-function interpolating L(1, ad(φk)) for weight k + 2 specialization φk of φ. In the two-variable case, we state a main conjecture on the characteristic power series in Zp[[T, S]] of Sel(ad(φ) ⊗ ν−1), where ν is the universal cyclotomic character with values in Zp[[S]]. Finally, we describe our recent results toward the proof of the conjecture and a possible strategy of proving the main conjecture using p-adic Siegel modular forms.

Three-dimensional structure of a cysteine-rich repeat from the low-density lipoprotein receptor.

The low-density lipoprotein (LDL) receptor plays a central role in mammalian cholesterol metabolism, clearing lipoproteins which bear apolipoproteins E and B-100 from plasma. Mutations in this molecule are associated with familial hypercholesterolemia, a condition which leads to an elevated plasma cholesterol concentration and accelerated atherosclerosis. The N-terminal segment of the LDL receptor contains a heptad of cysteine-rich repeats that bind the lipoproteins. Similar repeats are present in related receptors, including the very low-density lipoprotein receptor and the LDL receptor-related protein/alpha 2-macroglobulin receptor, and in proteins which are functionally unrelated, such as the C9 component of complement. The first repeat of the human LDL receptor has been expressed in Escherichia coli as a glutathione S-transferase fusion protein, and the cleaved and purified receptor module has been shown to fold to a single, fully oxidized form that is recognized by the monoclonal antibody IgG-C7 in the presence of calcium ions. The three-dimensional structure of this module has been determined by two-dimensional NMR spectroscopy and shown to consist of a beta-hairpin structure, followed by a series of beta turns. Many of the side chains of the acidic residues, including the highly conserved Ser-Asp-Glu triad, are clustered on one face of the module. To our knowledge, this structure has not previously been described in any other protein and may represent a structural paradigm both for the other modules in the LDL receptor and for the homologous domains of several other proteins. Calcium ions had only minor effects on the CD spectrum and no effect on the 1H NMR spectrum of the repeat, suggesting that they induce no significant conformational change.

Tight-Binding Approximations in 1D and 2D Coupled-Cavity Photonic Crystal Structures

Light confinement and controlling an optical field has numerous applications in the field of telecommunications for optical signals processing. When the wavelength of the electromagnetic field is on the order of the period of a photonic microstructure, the field undergoes reflection, refraction, and coherent scattering. This produces photonic bandgaps, forbidden frequency regions or spectral stop bands where light cannot exist. Dielectric perturbations that break the perfect periodicity of these structures produce what is analogous to an impurity state in the bandgap of a semiconductor. The defect modes that exist at discrete frequencies within the photonic bandgap are spatially localized about the cavity-defects in the photonic crystal. In this thesis the properties of two tight-binding approximations (TBAs) are investigated in one-dimensional and two-dimensional coupled-cavity photonic crystal structures We require an efficient and simple approach that ensures the continuity of the electromagnetic field across dielectric interfaces in complex structures. In this thesis we develop \textrm{E} -- and \textrm{D} --TBAs to calculate the modes in finite 1D and 2D two-defect coupled-cavity photonic crystal structures. In the \textrm{E} -- and \textrm{D} --TBAs we expand the coupled-cavity \overrightarrow{E} --modes in terms of the individual \overrightarrow{E} -- and \overrightarrow{D} --modes, respectively. We investigate the dependence of the defect modes, their frequencies and quality factors on the relative placement of the defects in the photonic crystal structures. We then elucidate the differences between the two TBA formulations, and describe the conditions under which these formulations may be more robust when encountering a dielectric perturbation. Our 1D analysis showed that the 1D modes were sensitive to the structure geometry. The antisymmetric \textrm{D} mode amplitudes show that the \textrm{D} --TBA did not capture the correct (tangential \overrightarrow{E} --field) boundary conditions. However, the \textrm{D} --TBA did not yield significantly poorer results compared to the \textrm{E} --TBA. Our 2D analysis reveals that the \textrm{E} -- and \textrm{D} --TBAs produced nearly identical mode profiles for every structure. Plots of the relative difference between the \textrm{E} and \textrm{D} mode amplitudes show that the \textrm{D} --TBA did capture the correct (normal \overrightarrow{E} --field) boundary conditions. We found that the 2D TBA CC mode calculations were 125-150 times faster than an FDTD calculation for the same two-defect PCS. Notwithstanding this efficiency, the appropriateness of either TBA was found to depend on the geometry of the structure and the mode(s), i.e. whether or not the mode has a large normal or tangential component.

Numerical investigation of seawater intrusion at Gooburrum, Bundaberg, Queensland, Australia

Seawater intrusion in coastal agricultural areas due to groundwater abstraction is a major environmental problem along the northeastern coast of Australia. Management options are being explored using numerical modelling, however, questions remain concerning the appropriate level of sophistication in models, choice of seaward boundary conditions, and how to accommodate heterogeneity and data uncertainty. The choice of seaward boundary condition is important since it affects the amount of salt transported into the aquifers and forms the focus of the present study. The impact of this boundary condition is illustrated for the seawater-intrusion problem in the Gooburrum aquifers, which occur within Tertiary sedimentary strata. A two-dimensional variable-density groundwater and solute-transport model was constructed using the computer code 2DFEMFAT (Cheng et al. 1998). The code was tested against an experiment for a steady-state freshwater-saltwater interface and against the Elder (Elder 1967) free-convection problem. Numerical simulations show that the imposition of the commonly-used equivalent hydrostatic freshwater heads, combined with a constant salt concentration at the seaward boundary, results in overestimated seawater intrusion in the lower Gooburrum aquifer. Since the imposition of this boundary condition allows water flow across the boundary, which subsequently takes salt into the aquifer, a careful check is essential to estimate whether too much mass of salt is introduced.

Three-dimensional simulation of the rolling of a saturated fibro-porous media

This paper describes recent advances made in computational modelling of the sugar cane liquid extraction process. The saturated fibro-porous material is rolled between circumferentially grooved rolls, which enhance frictional grip and provide a low-resistance path for liquid flow during the extraction process. Previously reported two-dimensional (2D) computational models, account for the large deformation of the porous material by solving the fully coupled governing fibre stress and fluid-flow equations using finite element techniques. While the 2D simulations provide much insight into the overarching cause-effect relationships, predictions of mechanical quantities such as roll separating force and particularly torque as a function of roll speed and degree of compression are not satisfactory for industrial use. It is considered that the unsatisfactory response in roll torque prediction may be due to the stress levels that exist between the groove tips and roots which have been largely neglected in the geometrically simplified 2D model. This paper gives results for both two- and three-dimensional finite element models and highlights their strengths and weaknesses in predicting key milling parameters. (c) 2005 Elsevier B.V. All rights reserved.

Reactive processing of polymers: structural characterization of products by 1H and 13C NMR spectroscopy for glycidyl methacrylate grafting onto EPR in the absence and presence of a reactive comonomer

Grafted GMA on EPR samples were prepared in a Thermo-Haake internal mixer by free radical melt grafting reactions in the absence (conventional system; EPR-g-GMA(CONV)) and presence of the reactive comonomer divinyl benzene, DVB (EPR-g-GMA(DVB)). The GMA-homopolymer (poly-GMA), a major side reaction product in the conventional system, was almost completely absent in the DVB-containing system, the latter also resulted in a much higher level of GMA grafting. A comprehensive microstructure analysis of the formed poly-GMA was performed based on one-dimensional H-1 and C-13 NMR spectroscopy and the complete spectral assignments were supported by two-dimensional NMR techniques based on long range two and three bond order carbon-proton couplings from HMBC (Heteronuclear Multiple Bond Coherence) and that of one bond carbon-proton couplings from HSQC (Heteronuclear Single Quantum Coherence), as well as the use of Distortionless Enhancement by Polarization Transfer (DEPT) NMR spectroscopy. The unambiguous analysis of the stereochemical configuration of poly-GMA was further used to help understand the microstructures of the GMA-grafts obtained in the two different free radical melt grafting reactions, the conventional and comonomer-containing systems. In the grafted GMA, in the conventional system (EPR-g-GMA(CONV)), the methylene protons of the GMA were found to be sensitive to tetrad configurational sequences and the results showed that 56% of the GMA sequence in the graft is in atactic configuration and 42% is in syndiotactic configuration whereas the poly-GMA was predominantly syndiotactic. The differences in the microstructures of the graft in the conventional EPR-g-GMA(CONV) and the DVB-containing (EPR-g-GMA(DVB)) systems is also reported (C) 2009 Elsevier Ltd. All rights reserved.

A 2D [FeII-bistetrazole] coordination polymer exhibiting spin-crossover properties

The reaction of 1,3-bis(tetrazol-1-yl)-2-propanol (btzpol) with Fe(BF4)2 · 6H2O in acetonitrile yields the remarkable 2D coordination polymer [FeII(btzpol)1.8(btzpol-OBF3)1.2](BF4)0.8 · (H2O)0.8(CH3CN) (1). This compound has been structurally characterized using an X-ray single-crystal synchrotron radiation source. The iron(II) centers are bridged by means of double btzpol bridges along the c direction, and by single btzpol bridges along the b direction. The reaction of part of the ligand with the counterion has forced the compound to crystallize in this extended two dimensional structure. The compound shows spin-transition properties, both induced by temperature and light, with T½ = 112 K and T(LIESST) = 46 K, respectively. The relaxation of the metastable high-spin state created by irradiation is exponential, following an Arrhenius type behavior at high temperature, and dominated by a temperature independent tunneling process at lower temperatures.

Regarding the benefit of zero-dimensional noise

Baker and Meese (2012) (B&M) provided an empirically driven criticism of the use of two-dimensional (2D) pixel noise in equivalent noise (EN) experiments. Their main objection was that in addition to injecting variability into the contrast detecting mechanisms, 2D noise also invokes gain control processes from a widely tuned contrast gain pool (e.g., Foley, 1994). B&M also developed a zero-dimensional (0D) noise paradigm in which all of the variance is concentrated in the mechanisms involved in the detection process. They showed that this form of noise conformed much more closely to expectations than did a 2D variant.