Short-channel polymer field-effect-transistor fabrication using spin-coating-induced edge template and ink-jet printing

A method to fabricate polymer field-effect transistors with submicron channel lengths is described. A thin polymer film is spin coated on a prepatterned resist with a low resolution to create a thickness contrast in the overcoated polymer layer. After plasma and solvent etching, a submicron-sized line structure, which templates the contour of the prepattern, is obtained. A further lift-off process is applied to define source-drain electrodes of transistors. With a combination of ink-jet printing, transistors with channel length down to 400 nm have been fabricated by this method. We show that drive current density increases as expected, while the on/off current ratio 106 is achieved. © 2005 American Institute of Physics.

Soil conditioning under London

The CTRL Contract 220 covered 7.5km twin-bore tunnels excavated between late 2002 and early 2004 from Stratford Box to St Pancras station in Central London. To ensure efficient machine operation as well as the transport and disposal of soil, soil conditioning treatments were applied. Specifically, the foam injection ratio (FIR) and the polymer injection ratio (PIR) (injected volume of foam and polymer solution expressed as a percentage of the excavated soil volume) were employed. It was found that carefully selected soil conditioning allowed chamber pressures of 200kPa or more to be accurately controlled in the stiff London Clay and to an extent, in the very stiff clays of the Lambeth Group. Average FIRs of 50% and PIRs of 7 and 9% were used in the Thanet Sand and in the Lambeth Group Clays. In contrast, much lower quantities of foam were used in the London Clay.

Self-aligned high-resolution printed polymer transistors

A process to fabricate solution-processable thin-film transistors (TFTs) with a one-step self-aligned definition of the dimensions in all functional layers is demonstrated. The TFT-channel, semiconductor materials, and effective gate dimention of different layers are determined by a one-step imprint process and the subsequent pattern transfer without the need for multiple patterning and mask alignment. The process is compatible with fabrication of large-scale circuits. Copyright © 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.