963 resultados para Hardware


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Training for receive antenna selection (AS) differs from that for conventional multiple antenna systems because of the limited hardware usage inherent in AS. We analyze and optimize the performance of a novel energy-efficient training method tailored for receive AS. In it, the transmitter sends not only pilots that enable the selection process, but also an extra pilot that leads to accurate channel estimates for the selected antenna that actually receives data. For time-varying channels, we propose a novel antenna selection rule and prove that it minimizes the symbol error probability (SEP). We also derive closed-form expressions for the SEP of MPSK, and show that the considered training method is significantly more energy-efficient than the conventional AS training method.

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We present an open-source, realtime, embedded implementation of a foot-mounted, zero-velocity-update-aided inertial navigation system. The implementation includes both hardware design and software, uses off-the-shelf components and assembly methods, and features a standard USB interface. The software is written in C and can easily be modified to run user implemented algorithms. The hardware design and the software are released under permissive open-source licenses and production files, source code, documentation, and further resources are available at www.openshoe.org. The reproduction cost for a single unit is below $800, with the inertial measurement unit making up the bulk ($700). The form factor of the implementation is small enough for it to be integrated in the sole of a shoe. A performance evaluation of the system shows a position errors for short trajectories (<;100 [m]) of ± 0.2-1% of the traveled distance, depending on the shape of trajectory.

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The Radio Interference (RI) from electric power transmission line hardware, if not controlled, poses serious electromagnetic interference to system in the vicinity. The present work mainly concerns with the RI from the insulator string along with the associated line hardware. The laboratory testing for the RI levels are carried out through the measurement of the conducted radio interference levels. However such measurements do not really locate the coronating point, as well as, the mode of corona. At the same time experience shows that it is rather difficult to locate the coronating points by mere inspection. After a thorough look into the intricacies of the problem, it is ascertained that the measurement of associated ground end currents could give a better picture of the prevailing corona modes and their intensities. A study on the same is attempted in the present work. Various intricacies of the problem,features of ground end current pulses and its correlation with RI are dealt with. Owing to the complexity of such experimental investigations, the study made is not fully complete nevertheless it seems to be first of its kind.

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In the underlay mode of cognitive radio, secondary users are allowed to transmit when the primary is transmitting, but under tight interference constraints that protect the primary. However, these constraints limit the secondary system performance. Antenna selection (AS)-based multiple antenna techniques, which exploit spatial diversity with less hardware, help improve secondary system performance. We develop a novel and optimal transmit AS rule that minimizes the symbol error probability (SEP) of an average interference-constrained multiple-input-single-output secondary system that operates in the underlay mode. We show that the optimal rule is a non-linear function of the power gain of the channel from the secondary transmit antenna to the primary receiver and from the secondary transmit antenna to the secondary receive antenna. We also propose a simpler, tractable variant of the optimal rule that performs as well as the optimal rule. We then analyze its SEP with L transmit antennas, and extensively benchmark it with several heuristic selection rules proposed in the literature. We also enhance these rules in order to provide a fair comparison, and derive new expressions for their SEPs. The results bring out new inter-relationships between the various rules, and show that the optimal rule can significantly reduce the SEP.

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Classical control and one cycle control of current are popular methods used to modulate pulses in active rectifiers for ac-dc power conversion. One cycle control has lower control complexity and can be implemented using linear analog circuits when compared with the classical approach. However, it also suffers from problems such as instability and offsets in current that is severe at light load conditions. A control strategy for bidirectional boost rectifiers based on one cycle control of charge is proposed for that overcomes these limitations. The integral of sensed current, which represents charge, is compared with a non-linear carrier, which is modified for ac-dc power conversion. This generates the gating signals for the switching devices. The modifications required for the control law governing one cycle control of charge is derived in the paper. Detailed simulation studies are carried out to compare one cycle control of current with the proposed method for ac-dc power conversion, which are validated on a laboratory hardware prototype.

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This paper presents an analysis and comparison between two circuit topologies of the 3-phase, 3-level unity power factor (Vienna) rectifier on the basis of packaging issues and semiconductor power losses. The analysis indicates the suitability of one particular circuit variant due to restrictions on switching frequency at higher power levels. A comparison is also done between hysteresis and carrier based PWM strategies for current control of the rectifier, along with experimental evaluation of the control strategies on a hardware prototype of the rectifier. The comparison indicates that the carrier based modulation strategy is better suited for use with higher order filters that are utilized in high power applications.

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In this paper we present a hardware-software hybrid technique for modular multiplication over large binary fields. The technique involves application of Karatsuba-Ofman algorithm for polynomial multiplication and a novel technique for reduction. The proposed reduction technique is based on the popular repeated multiplication technique and Barrett reduction. We propose a new design of a parallel polynomial multiplier that serves as a hardware accelerator for large field multiplications. We show that the proposed reduction technique, accelerated using the modified polynomial multiplier, achieves significantly higher performance compared to a purely software technique and other hybrid techniques. We also show that the hybrid accelerated approach to modular field multiplication is significantly faster than the Montgomery algorithm based integrated multiplication approach.

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It is well known that extremely long low-density parity-check (LDPC) codes perform exceptionally well for error correction applications, short-length codes are preferable in practical applications. However, short-length LDPC codes suffer from performance degradation owing to graph-based impairments such as short cycles, trapping sets and stopping sets and so on in the bipartite graph of the LDPC matrix. In particular, performance degradation at moderate to high E-b/N-0 is caused by the oscillations in bit node a posteriori probabilities induced by short cycles and trapping sets in bipartite graphs. In this study, a computationally efficient algorithm is proposed to improve the performance of short-length LDPC codes at moderate to high E-b/N-0. This algorithm makes use of the information generated by the belief propagation (BP) algorithm in previous iterations before a decoding failure occurs. Using this information, a reliability-based estimation is performed on each bit node to supplement the BP algorithm. The proposed algorithm gives an appreciable coding gain as compared with BP decoding for LDPC codes of a code rate equal to or less than 1/2 rate coding. The coding gains are modest to significant in the case of optimised (for bipartite graph conditioning) regular LDPC codes, whereas the coding gains are huge in the case of unoptimised codes. Hence, this algorithm is useful for relaxing some stringent constraints on the graphical structure of the LDPC code and for developing hardware-friendly designs.

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We address the problem of sampling and reconstruction of two-dimensional (2-D) finite-rate-of-innovation (FRI) signals. We propose a three-channel sampling method for efficiently solving the problem. We consider the sampling of a stream of 2-D Dirac impulses and a sum of 2-D unit-step functions. We propose a 2-D causal exponential function as the sampling kernel. By causality in 2-D, we mean that the function has its support restricted to the first quadrant. The advantage of using a multichannel sampling method with causal exponential sampling kernel is that standard annihilating filter or root-finding algorithms are not required. Further, the proposed method has inexpensive hardware implementation and is numerically stable as the number of Dirac impulses increases.

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Wavelength-division multiplexing (WDM) technology, by which multiple optical channels can be simultaneously transmitted at different wavelengths through a single optical fiber, is a useful means of making full use of the low-loss characteristics of optical fibers over a wide-wavelength region. The present day multifunction RADARs with multiple transmit receive modules requires various kinds of signal distribution for real time operation. If the signal distribution can be achieved through optical networks by using Wavelength Division Multiplexing (WDM) methods, it results in a distribution scheme with less hardware complexity and leads to the reduction in the weight of the antenna arrays In addition, being an Optical network it is free from Electromagnetic interference which is a crucial requirement in an array environment. This paper discusses about the analysis performed on various WDM components of distribution optical network for radar applications. The analysis is performed by considering the feasible constant gain regions of Erbium doped fiber amplifier (EDFA) in Matlab environment. This will help the user in the selection of suitable components for WDM based optical distribution networks.

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The following paper presents a Powerline Communication (PLC) Method for grid interfaced inverters, for smart grid application. The PLC method is based on the concept of the composite vector which involves multiple components rotating at different harmonic frequencies. The pulsed information is modulated on the fundamental component of the grid current as a specific repeating sequence of a particular harmonic. The principle of communication is same as that of power flow, thus reducing the complexity. The power flow and information exchange are simultaneously accomplished by the interfacing inverters based on current programmed vector control, thus eliminating the need for dedicated hardware. Simulation results have been shown for inter-inverter communication, both under ideal and distorted conditions, using various harmonic modulating signals.

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Each new generation of GPUs vastly increases the resources available to GPGPU programs. GPU programming models (like CUDA) were designed to scale to use these resources. However, we find that CUDA programs actually do not scale to utilize all available resources, with over 30% of resources going unused on average for programs of the Parboil2 suite that we used in our work. Current GPUs therefore allow concurrent execution of kernels to improve utilization. In this work, we study concurrent execution of GPU kernels using multiprogram workloads on current NVIDIA Fermi GPUs. On two-program workloads from the Parboil2 benchmark suite we find concurrent execution is often no better than serialized execution. We identify that the lack of control over resource allocation to kernels is a major serialization bottleneck. We propose transformations that convert CUDA kernels into elastic kernels which permit fine-grained control over their resource usage. We then propose several elastic-kernel aware concurrency policies that offer significantly better performance and concurrency compared to the current CUDA policy. We evaluate our proposals on real hardware using multiprogrammed workloads constructed from benchmarks in the Parboil 2 suite. On average, our proposals increase system throughput (STP) by 1.21x and improve the average normalized turnaround time (ANTT) by 3.73x for two-program workloads when compared to the current CUDA concurrency implementation.

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Transmit antenna selection (AS) has been adopted in contemporary wideband wireless standards such as Long Term Evolution (LTE). We analyze a comprehensive new model for AS that captures several key features about its operation in wideband orthogonal frequency division multiple access (OFDMA) systems. These include the use of channel-aware frequency-domain scheduling (FDS) in conjunction with AS, the hardware constraint that a user must transmit using the same antenna over all its assigned subcarriers, and the scheduling constraint that the subcarriers assigned to a user must be contiguous. The model also captures the novel dual pilot training scheme that is used in LTE, in which a coarse system bandwidth-wide sounding reference signal is used to acquire relatively noisy channel state information (CSI) for AS and FDS, and a dense narrow-band demodulation reference signal is used to acquire accurate CSI for data demodulation. We analyze the symbol error probability when AS is done in conjunction with the channel-unaware, but fair, round-robin scheduling and with channel-aware greedy FDS. Our results quantify how effective joint AS-FDS is in dispersive environments, the interactions between the above features, and the ability of the user to lower SRS power with minimal performance degradation.

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The presence of software bloat in large flexible software systems can hurt energy efficiency. However, identifying and mitigating bloat is fairly effort intensive. To enable such efforts to be directed where there is a substantial potential for energy savings, we investigate the impact of bloat on power consumption under different situations. We conduct the first systematic experimental study of the joint power-performance implications of bloat across a range of hardware and software configurations on modern server platforms. The study employs controlled experiments to expose different effects of a common type of Java runtime bloat, excess temporary objects, in the context of the SPECPower_ssj2008 workload. We introduce the notion of equi-performance power reduction to characterize the impact, in addition to peak power comparisons. The results show a wide variation in energy savings from bloat reduction across these configurations. Energy efficiency benefits at peak performance tend to be most pronounced when bloat affects a performance bottleneck and non-bloated resources have low energy-proportionality. Equi-performance power savings are highest when bloated resources have a high degree of energy proportionality. We develop an analytical model that establishes a general relation between resource pressure caused by bloat and its energy efficiency impact under different conditions of resource bottlenecks and energy proportionality. Applying the model to different "what-if" scenarios, we predict the impact of bloat reduction and corroborate these predictions with empirical observations. Our work shows that the prevalent software-only view of bloat is inadequate for assessing its power-performance impact and instead provides a full systems approach for reasoning about its implications.

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In this work, first a Fortran code is developed for three dimensional linear elastostatics using constant boundary elements; the code is based on a MATLAB code developed by the author earlier. Next, the code is parallelized using BLACS, MPI, and ScaLAPACK. Later, the parallelized code is used to demonstrate the usefulness of the Boundary Element Method (BEM) as applied to the realtime computational simulation of biological organs, while focusing on the speed and accuracy offered by BEM. A computer cluster is used in this part of the work. The commercial software package ANSYS is used to obtain the `exact' solution against which the solution from BEM is compared; analytical solutions, wherever available, are also used to establish the accuracy of BEM. A pig liver is the biological organ considered. Next, instead of the computer cluster, a Graphics Processing Unit (GPU) is used as the parallel hardware. Results indicate that BEM is an interesting choice for the simulation of biological organs. Although the use of BEM for the simulation of biological organs is not new, the results presented in the present study are not found elsewhere in the literature. Also, a serial MATLAB code, and both serial and parallel versions of a Fortran code, which can solve three dimensional (3D) linear elastostatic problems using constant boundary elements, are provided as supplementary files that can be freely downloaded.