Investigating routes toward atomic layer deposition of silicon carbide: Ab initio screening of potential silicon and carbon precursors

Silicon carbide (SiC) is a promising material for electronics due to its hardness, and ability to carry high currents and high operating temperature. SiC films are currently deposited using chemical vapor deposition (CVD) at high temperatures 1500–1600 °C. However, there is a need to deposit SiC-based films on the surface of high aspect ratio features at low temperatures. One of the most precise thin film deposition techniques on high-aspect-ratio surfaces that operates at low temperatures is atomic layer deposition (ALD). However, there are currently no known methods for ALD of SiC. Herein, the authors present a first-principles thermodynamic analysis so as to screen different precursor combinations for SiC thin films. The authors do this by calculating the Gibbs energy ΔGΔG of the reaction using density functional theory and including the effects of pressure and temperature. This theoretical model was validated for existing chemical reactions in CVD of SiC at 1000 °C. The precursors disilane (Si2H6), silane (SiH4), or monochlorosilane (SiH3Cl) with ethyne (C2H2), carbontetrachloride (CCl4), or trichloromethane (CHCl3) were predicted to be the most promising for ALD of SiC at 400 °C.

Silicon Promotes Exodermal Casparian Band Formation in Si-Accumulating and Si-Excluding Species by Forming Phenol Complexes

We studied the effect of Silicon (Si) on Casparian band (CB) development, chemical composition of the exodermal CB and Si deposition across the root in the Si accumulators rice and maize and the Si non-accumulator onion. Plants were cultivated in nutrient solution with and without Si supply. The CB development was determined in stained root cross-sections. The outer part of the roots containing the exodermis was isolated after enzymatic treatment. The exodermal suberin was transesterified with MeOH/BF3 and the chemical composition was measured using gas chromatography-mass spectroscopy (GC-MS) and flame ionization detector (GC-FID). Laser ablation-inductively coupled plasma-mass spectroscopy (LA-ICP-MS) was used to determine the Si deposition across root cross sections. Si promoted CB formation in the roots of Si-accumulator and Si non-accumulator species. The exodermal suberin was decreased in rice and maize due to decreased amounts of aromatic suberin fractions. Si did not affect the concentration of lignin and lignin-like polymers in the outer part of rice, maize and onion roots. The highest Si depositions were found in the tissues containing CB. These data along with literature were used to suggest a mechanism how Si promotes the CB development by forming complexes with phenols.

Growth and application of planar III-V semiconductor nanowires grown with MOCVD

The semiconductor nanowire has been widely studied over the past decade and identified as a promising nanotechnology building block with application in photonics and electronics. The flexible bottom-up approach to nanowire growth allows for straightforward fabrication of complex 1D nanostructures with interesting optical, electrical, and mechanical properties. III-V nanowires in particular are useful because of their direct bandgap, high carrier mobility, and ability to form heterojunctions and have been used to make devices such as light-emitting diodes, lasers, and field-effect transistors. However, crystal defects are widely reported for III-V nanowires when grown in the common out-of-plane <111>B direction. Furthermore, commercialization of nanowires has been limited by the difficulty of assembling nanowires with predetermined position and alignment on a wafer-scale. In this thesis, planar III-V nanowires are introduced as a low-defect and integratable nanotechnology building block grown with metalorganic chemical vapor deposition. Planar GaAs nanowires grown with gold seed particles self-align along the <110> direction on the (001) GaAs substrate. Transmission electron microscopy reveals that planar GaAs nanowires are nearly free of crystal defects and grow laterally and epitaxially on the substrate surface. The nanowire morphology is shown to be primarily controlled through growth temperature and an ideal growth window of 470 +\- 10 °C is identified for planar GaAs nanowires. Extension of the planar growth mode to other materials is demonstrated through growth of planar InAs nanowires. Using a sacrificial layer, the transfer of planar GaAs nanowires onto silicon substrates with control over the alignment and position is presented. A metal-semiconductor field-effect transistor fabricated with a planar GaAs nanowire shows bulk-like low-field electron transport characteristics with high mobility. The aligned planar geometry and excellent material quality of planar III-V nanowires may lead to highly integrated III-V nanophotonics and nanoelectronics.

Effects of silicon treatment and inoculation with Fusarium oxysporum f. sp. vasinfectum on cellular defences in root tissues of two cotton cultivars

BACKGROUND AND AIMS: Silicon has been shown to enhance the resistance of plants to fungal and bacterial pathogens. Here, the effect of potassium silicate was assessed on two cotton (Gossypium hirsutum) cultivars subsequently inoculated with Fusarium oxysporum f. sp. vasinfectum (Fov). Sicot 189 is moderately resistant whilst Sicot F-1 is the second most resistant commercial cultivar presently available in Australia. METHODS: Transmission and light microscopy were used to compare cellular modifications in root cells after these different treatments. The accumulation of phenolic compounds and lignin was measured. KEY RESULTS: Cellular alterations including the deposition of electron-dense material, degradation of fungal hyphae and occlusion of endodermal cells were more rapidly induced and more intense in endodermal and vascular regions of Sicot F-1 plants supplied with potassium silicate followed by inoculation with Fov than in similarly treated Sicot 189 plants or in silicate-treated plants of either cultivar not inoculated with Fov. Significantly more phenolic compounds were present at 7 d post-infection (dpi) in root extracts of Sicot F-1 plants treated with potassium silicate followed by inoculation with Fov compared with plants from all other treatments. The lignin concentration at 3 dpi in root material from Sicot F-1 treated with potassium silicate and inoculated with Fov was significantly higher than that from water-treated and inoculated plants. CONCLUSIONS: This study demonstrates that silicon treatment can affect cellular defence responses in cotton roots subsequently inoculated with Fov, particularly in Sicot F-1, a cultivar with greater inherent resistance to this pathogen. This suggests that silicon may interact with or initiate defence pathways faster in this cultivar than in the less resistant cultivar.

Analysis methods for meso- and macroporous silicon etching baths

Analysis methods for electrochemical etching baths consisting of various concentrations of hydrofluoric acid (HF) and an additional organic surface wetting agent are presented. These electrolytes are used for the formation of meso- and macroporous silicon. Monitoring the etching bath composition requires at least one method each for the determination of the HF concentration and the organic content of the bath. However, it is a precondition that the analysis equipment withstands the aggressive HF. Titration and a fluoride ion-selective electrode are used for the determination of the HF and a cuvette test method for the analysis of the organic content, respectively. The most suitable analysis method is identified depending on the components in the electrolyte with the focus on capability of resistance against the aggressive HF.

Contactless Spectral-Dependent Measurement of Bulk Lifetime and Surface Recombination Velocity in Silicon Photovoltaic Materials

Charge carrier lifetime measurements in bulk or unfinished photovoltaic (PV) materials allow for a more accurate estimate of power conversion efficiency in completed solar cells. In this work, carrier lifetimes in PV- grade silicon wafers are obtained by way of quasi-steady state photoconductance measurements. These measurements use a contactless RF system coupled with varying narrow spectrum input LEDs, ranging in wavelength from 460 nm to 1030 nm. Spectral dependent lifetime measurements allow for determination of bulk and surface properties of the material, including the intrinsic bulk lifetime and the surface recombination velocity. The effective lifetimes are fit to an analytical physics-based model to determine the desired parameters. Passivated and non-passivated samples are both studied and are shown to have good agreement with the theoretical model.

The development of planar high-K/III-V p-channel MOSFETs for post-silicon CMOS

Conventional Si complementary-metal-oxide-semiconductor (CMOS) scaling is fast approaching its limits. The extension of the logic device roadmap for future enhancements in transistor performance requires non-Si materials and new device architectures. III-V materials, due to their superior electron transport properties, are well poised to replace Si as the channel material beyond the 10nm technology node to mitigate the performance loss of Si transistors from further reductions in supply voltage to minimise power dissipation in logic circuits. However several key challenges, including a high quality dielectric/III-V gate stack, a low-resistance source/drain (S/D) technology, heterointegration onto a Si platform and a viable III-V p-metal-oxide-semiconductor field-effect-transistor (MOSFET), need to be addressed before III-Vs can be employed in CMOS. This Thesis specifically addressed the development and demonstration of planar III-V p-MOSFETs, to complement the n-MOSFET, thereby enabling an all III-V CMOS technology to be realised. This work explored the application of InGaAs and InGaSb material systems as the channel, in conjunction with Al2O3/metal gate stacks, for p-MOSFET development based on the buried-channel flatband device architecture. The body of work undertaken comprised material development, process module development and integration into a robust fabrication flow for the demonstration of p-channel devices. The parameter space in the design of the device layer structure, based around the III-V channel/barrier material options of In_x≥0.53Ga_1-xAs/In_0.52Al_0.48As and In_x≥0.1Ga_1-xSb/AlSb, was systematically examined to improve hole channel transport. A mobility of 433 cm²/Vs, the highest room temperature hole mobility of any InGaAs quantum-well channel reported to date, was obtained for the In_0.85Ga_0.15As (2.1% strain) structure. S/D ohmic contacts were developed based on thermally annealed Au/Zn/Au metallisation and validated using transmission line model test structures. The effects of metallisation thickness, diffusion barriers and de-oxidation conditions were examined. Contacts to InGaSb-channel structures were found to be sensitive to de-oxidation conditions. A fabrication process, based on a lithographically-aligned double ohmic patterning approach, was realised for deep submicron gate-to-source/drain gap (L_side) scaling to minimise the access resistance, thereby mitigating the effects of parasitic S/D series resistance on transistor performance. The developed process yielded gaps as small as 20nm. For high-k integration on GaSb, ex-situ ammonium sulphide ((NH₄)₂S) treatments, in the range 1%-22%, for 10min at 295K were systematically explored for improving the electrical properties of the Al₂O₃/GaSb interface. Electrical and physical characterisation indicated the 1% treatment to be most effective with interface trap densities in the range of 4 - 10×10¹²cm^-2eV^-1 in the lower half of the bandgap. An extended study, comprising additional immersion times at each sulphide concentration, was further undertaken to determine the surface roughness and the etching nature of the treatments on GaSb. A number of p-MOSFETs based on III-V-channels with the most promising hole transport and integration of the developed process modules were successfully demonstrated in this work. Although the non-inverted InGaAs-channel devices showed good current modulation and switch-off characteristics, several aspects of performance were non-ideal; depletion-mode operation, modest drive current (I_d,sat=1.14mA/mm), double peaked transconductance (g_m=1.06mS/mm), high subthreshold swing (SS=301mV/dec) and high on-resistance (R_on=845kΩ.μm). Despite demonstrating substantial improvement in the on-state metrics of I_d,sat (11×), g_m (5.5×) and R_on (5.6×), inverted devices did not switch-off. Scaling gate-to-source/drain gap (L_side) from 1μm down to 70nm improved I_d,sat (72.4mA/mm) by a factor of 3.6 and gm (25.8mS/mm) by a factor of 4.1 in inverted InGaAs-channel devices. Well-controlled current modulation and good saturation behaviour was observed for InGaSb-channel devices. In the on-state In_0.3Ga_0.7Sb-channel (I_d,sat=49.4mA/mm, g_m=12.3mS/mm, R_on=31.7kΩ.μm) and In_0.4Ga_0.6Sb-channel (I_d,sat=38mA/mm, g_m=11.9mS/mm, R_on=73.5kΩ.μm) devices outperformed the InGaAs-channel devices. However the devices could not be switched off. These findings indicate that III-V p-MOSFETs based on InGaSb as opposed to InGaAs channels are more suited as the p-channel option for post-Si CMOS.

Deposition of Intrinsic a-Si:H by ECR-CVD to Passivate the Crystalline Silicon Heterointerface in HIT Solar Cells

We have deposited intrinsic amorphous silicon (a-Si:H) using the electron cyclotron resonance (ECR) chemical vapor deposition technique in order to analyze the a-Si:H/c-Si heterointerface and assess the possible application in heterojunction with intrinsic thin layer (HIT) solar cells. Physical characterization of the deposited films shows that the hydrogen content is in the 15-30% range, depending on deposition temperature. The optical bandgap value is always comprised within the range 1.9- 2.2 eV. Minority carrier lifetime measurements performed on the heterostructures reach high values up to 1.3 ms, indicating a well-passivated a-Si:H/c-Si heterointerface for deposition temperatures as low as 100°C. In addition, we prove that the metal-oxide- semiconductor conductance method to obtain interface trap distribution can be applied to the a-Si:H/c-Si heterointerface, since the intrinsic a-Si:H layer behaves as an insulator at low or negative bias. Values for the minimum of D_it as low as 8 × 10^10 cm^2 · eV^-1 were obtained for our samples, pointing to good surface passivation properties of ECR-deposited a-Si:H for HIT solar cell applications.

Limitations of high pressure sputtering for amorphous silicon deposition

Amorphous silicon thin films were deposited using the high pressure sputtering (HPS) technique to study the influence of deposition parameters on film composition, presence of impurities, atomic bonding characteristics and optical properties. An optical emission spectroscopy (OES) system has been used to identify the different species present in the plasma in order to obtain appropriate conditions to deposit high purity films. Composition measurements in agreement with the OES information showed impurities which critically depend on the deposition rate and on the gas pressure. We prove that films deposited at the highest RF power and 3.4 × 10^−2 mbar, exhibit properties as good as the ones of the films deposited by other more standard techniques.

Room temperature photo-response of titanium supersaturated silicon at energies over the bandgap

Silicon samples were implanted with high Ti doses and subsequently processed with the pulsed-laser melting technique. The electronic transport properties in the 15–300 K range and the room temperature spectral photoresponse at energies over the bandgap were measured. Samples with Ti concentration below the insulator-metal (I-M) transition limit showed a progressive reduction of the carrier lifetime in the implanted layer as Ti dose is increased. However, when the Ti concentration exceeded this limit, an extraordinary recovery of the photoresponse was measured. This result supports the theory of intermediate band materials and is of utmost relevance for photovoltaic cells and Si-based detectors.

Holistic Design In High-Speed Optical Interconnects

Integrated circuit scaling has enabled a huge growth in processing capability, which necessitates a corresponding increase in inter-chip communication bandwidth. As bandwidth requirements for chip-to-chip interconnection scale, deficiencies of electrical channels become more apparent. Optical links present a viable alternative due to their low frequency-dependent loss and higher bandwidth density in the form of wavelength division multiplexing. As integrated photonics and bonding technologies are maturing, commercialization of hybrid-integrated optical links are becoming a reality. Increasing silicon integration leads to better performance in optical links but necessitates a corresponding co-design strategy in both electronics and photonics. In this light, holistic design of high-speed optical links with an in-depth understanding of photonics and state-of-the-art electronics brings their performance to unprecedented levels. This thesis presents developments in high-speed optical links by co-designing and co-integrating the primary elements of an optical link: receiver, transmitter, and clocking.

In the first part of this thesis a 3D-integrated CMOS/Silicon-photonic receiver will be presented. The electronic chip features a novel design that employs a low-bandwidth TIA front-end, double-sampling and equalization through dynamic offset modulation. Measured results show -14.9dBm of sensitivity and energy efficiency of 170fJ/b at 25Gb/s. The same receiver front-end is also used to implement source-synchronous 4-channel WDM-based parallel optical receiver. Quadrature ILO-based clocking is employed for synchronization and a novel frequency-tracking method that exploits the dynamics of IL in a quadrature ring oscillator to increase the effective locking range. An adaptive body-biasing circuit is designed to maintain the per-bit-energy consumption constant across wide data-rates. The prototype measurements indicate a record-low power consumption of 153fJ/b at 32Gb/s. The receiver sensitivity is measured to be -8.8dBm at 32Gb/s.

Next, on the optical transmitter side, three new techniques will be presented. First one is a differential ring modulator that breaks the optical bandwidth/quality factor trade-off known to limit the speed of high-Q ring modulators. This structure maintains a constant energy in the ring to avoid pattern-dependent power droop. As a first proof of concept, a prototype has been fabricated and measured up to 10Gb/s. The second technique is thermal stabilization of micro-ring resonator modulators through direct measurement of temperature using a monolithic PTAT temperature sensor. The measured temperature is used in a feedback loop to adjust the thermal tuner of the ring. A prototype is fabricated and a closed-loop feedback system is demonstrated to operate at 20Gb/s in the presence of temperature fluctuations. The third technique is a switched-capacitor based pre-emphasis technique designed to extend the inherently low bandwidth of carrier injection micro-ring modulators. A measured prototype of the optical transmitter achieves energy efficiency of 342fJ/bit at 10Gb/s and the wavelength stabilization circuit based on the monolithic PTAT sensor consumes 0.29mW.

Lastly, a first-order frequency synthesizer that is suitable for high-speed on-chip clock generation will be discussed. The proposed design features an architecture combining an LC quadrature VCO, two sample-and-holds, a PI, digital coarse-tuning, and rotational frequency detection for fine-tuning. In addition to an electrical reference clock, as an extra feature, the prototype chip is capable of receiving a low jitter optical reference clock generated by a high-repetition-rate mode-locked laser. The output clock at 8GHz has an integrated RMS jitter of 490fs, peak-to-peak periodic jitter of 2.06ps, and total RMS jitter of 680fs. The reference spurs are measured to be –64.3dB below the carrier frequency. At 8GHz the system consumes 2.49mW from a 1V supply.

Electrical characterization of CVD diamond-n(+) silicon junctions

The electrical characteristics of CVD-diamond/n(+)-Si heterojunction devices are reported. Below 250 K the diodes show an unusual inversion of their rectification properties. This behavior is attributed to an enhanced tunneling component due to interface states, which change their occupation with the applied bias. The temperature dependence of the loss tangent shows two relaxation processes with different activation energies. These processes are likely related with two parallel charge transport mechanisms, one through the diamond grain, and the other through the grain boundary. (C) 2001 Elsevier Science B.V. Ah rights reserved.