Using test infrastructures for (remote) online evaluation of the sensitivity to SEUs of FPGAs

This paper proposes an online mechanism that can evaluate the sensitivity of single event upsets (SEUs) of field programmable gate arrays (FPGAs). The online detection mechanism cyclically reads and compares the values form the external and internal configuration memories, taking into account the mask information. This remote detection method also signals any mismatch as a result of a SEU that affects both used and not-used FPGA parts, which maximizes the monitored area. By utilizing an external, Web-accessible controller that is connected to the test infrastructure, the possibility of running the same operation in a remote manner is enabled. Moreover, the need for a local memory to store the mask values is also eliminated.

A comparative analysis of fault injection methods via enhanced on-chip debug infrastructures

On-chip debug (OCD) features are frequently available in modern microprocessors. Their contribution to shorten the time-to-market justifies the industry investment in this area, where a number of competing or complementary proposals are available or under development, e.g. NEXUS, CJTAG, IJTAG. The controllability and observability features provided by OCD infrastructures provide a valuable toolbox that can be used well beyond the debugging arena, improving the return on investment rate by diluting its cost across a wider spectrum of application areas. This paper discusses the use of OCD features for validating fault tolerant architectures, and in particular the efficiency of various fault injection methods provided by enhanced OCD infrastructures. The reference data for our comparative study was captured on a workbench comprising the 32-bit Freescale MPC-565 microprocessor, an iSYSTEM IC3000 debugger (iTracePro version) and the Winidea 2005 debugging package. All enhanced OCD infrastructures were implemented in VHDL and the results were obtained by simulation within the same fault injection environment. The focus of this paper is on the comparative analysis of the experimental results obtained for various OCD configurations and debugging scenarios.

Real time fault injection using a modified debugging infrastructure

Dependability is a critical factor in computer systems, requiring high quality validation & verification procedures in the development stage. At the same time, digital devices are getting smaller and access to their internal signals and registers is increasingly complex, requiring innovative debugging methodologies. To address this issue, most recent microprocessors include an on-chip debug (OCD) infrastructure to facilitate common debugging operations. This paper proposes an enhanced OCD infrastructure with the objective of supporting the verification of fault-tolerant mechanisms through fault injection campaigns. This upgraded on-chip debug and fault injection (OCD-FI) infrastructure provides an efficient fault injection mechanism with improved capabilities and dynamic behavior. Preliminary results show that this solution provides flexibility in terms of fault triggering and allows high speed real-time fault injection in memory elements

Real time fault injection using enhanced OCD -- a performance analysis

Fault injection is frequently used for the verification and validation of dependable systems. When targeting real time microprocessor based systems the process becomes significantly more complex. This paper proposes two complementary solutions to improve real time fault injection campaign execution, both in terms of performance and capabilities. The methodology is based on the use of the on-chip debug mechanisms present in modern electronic devices. The main objective is the injection of faults in microprocessor memory elements with minimum delay and intrusiveness. Different configurations were implemented and compared in terms of performance gain and logic overhead.

Using NEXUS compliant debuggers for real time fault injection on microprocessors

As electronic devices get smaller and more complex, dependability assurance is becoming fundamental for many mission critical computer based systems. This paper presents a case study on the possibility of using the on-chip debug infrastructures present in most current microprocessors to execute real time fault injection campaigns. The proposed methodology is based on a debugger customized for fault injection and designed for maximum flexibility, and consists of injecting bit-flip type faults on memory elements without modifying or halting the target application. The debugger design is easily portable and applicable to different architectures, providing a flexible and efficient mechanism for verifying and validating fault tolerant components.

Reverse problem-based learning - a case study with a Braille machine

Engineering Education includes not only teaching theoretical fundamental concepts but also its verification during practical lessons in laboratories. The usual strategies to carry out this action are frequently based on Problem Based Learning, starting from a given state and proceeding forward to a target state. The possibility or the effectiveness of this procedure depends on previous states and if the present state was caused or resulted from earlier ones. This often happens in engineering education when the achieved results do not match the desired ones, e.g. when programming code is being developed or when the cause of the wrong behavior of an electronic circuit is being identified. It is thus important to also prepare students to proceed in the reverse way, i.e. given a start state generate the explanation or even the principles that underlie it. Later on, this sort of skills will be important. For instance, to a doctor making a patient?s story or to an engineer discovering the source of a malfunction. This learning methodology presents pedagogical advantages besides the enhanced preparation of students to their future work. The work presented on his document describes an automation project developed by a group of students in an engineering polytechnic school laboratory. The main objective was to improve the performance of a Braille machine. However, in a scenario of Reverse Problem-Based learning, students had first to discover and characterize the entire machine's function before being allowed (and being able) to propose a solution for the existing problem.

Adapting remote labs to learning scenarios: case studies using VISIR and RemotElectLab

Remote laboratories are an emergent technological and pedagogical tool at all education levels, and their widespread use is an important part of their own improvement and evolution. This paper describes several issues encountered on laboratorial classes, on higher education courses, when using remote laboratories based on PXI systems, either using the VISIR system or an alternate in-house solution. Three main issues are presented and explained, all reported by teachers, that gave support to students' use of remote laboratories. The first issue deals with the need to allow students to select the actual place where an ammeter is to be inserted on electric circuits, even incorrectly, therefore emulating real-world difficulties. The second one deals with problems with timing when several measurements are required at short intervals, as in the discharge cycle of a capacitor. In addition, the last issue deals with the use of a multimeter in dc mode when reading ac values, a use that collides with the lab settings. All scenarios are presented and discussed, including the solution found for each case. The conclusion derived from the described work is that the remote laboratories area is an expanding field, where practical use leads to improvement and evolution of the available solutions, requiring a strict cooperation and information-sharing between all actors, i.e., developers, teachers, and students.

IX International conference on Remote Engineering and Virtual instrumentation REV 2012

THE ninth edition of the International Conference on Remote Engineering and Virtual Instrumentation (REV) [1] was held at the Faculty of Engineering of the University of Deusto, Bilbao (Spain), from the 4th to the 6th of July, 2012. A world-class research community in the subject of remote and virtual laboratories joined the event.

Using the TRAILER tool for managing informal learning in academic and professional contexts: the learner perspective

Informal Learning plays an important role in everyone's life and yet we often are unaware of it. The need to keep track of the knowledge acquired through informal learning is increasing as its sources become increasingly diverse. This paper presents a study on a tool developed to help keeping track of learners' informal learning, both within academic and professional contexts, This tool, developed within the European Commission funded TRAILER project, will further integrate the improvements suggested by users during the piloting phase. The two studied contexts were similar regarding the importance and perception of Informal Learning, but differed concerning tool usage. The overall idea of managing one's informal learning was well accepted and welcomed, which validated the emerging need for a tool with this purpose.

Managing informal learning in engineering contexts: the learners' perspective

According to recent studies, informal learning accounts for more than 75% of our continuous learning through life. However, the awareness of this learning, its benefits and its potential is still not very clear. In engineering contexts, informal learning could play an invaluable role helping students or employees to engage with peers and also with more experience colleagues, exchanging ideas and discussing problems. This work presents an initial set of results of the piloting phase of a project (TRAILER) where an innovative service based on Information & Communication Technologies was developed in order to aid the collection and visibility of informal learning. This set of results concerns engineering contexts (academic and business), from the learners' perspective. The major idea that emerged from these piloting trials was that it represented a good way of collecting, recording and sharing informal learning that otherwise could easily be forgotten. Several benefits were reported between the two communities such as being helpful in managing competences and human resources within an institution.

A mobile robot platform for open learning based on serious games and remote laboratories

Within the pedagogical community, Serious Games have arisen as a viable alternative to traditional course-based learning materials. Until now, they have been based strictly on software solutions. Meanwhile, research into Remote Laboratories has shown that they are a viable, low-cost solution for experimentation in an engineering context, providing uninterrupted access, low-maintenance requirements, and a heightened sense of reality when compared to simulations. This paper will propose a solution where both approaches are combined to deliver a Remote Laboratory-based Serious Game for use in engineering and school education. The platform for this system is the WebLab-Deusto Framework, already well-tested within the remote laboratory context, and based on open standards. The laboratory allows users to control a mobile robot in a labyrinth environment and take part in an interactive game where they must locate and correctly answer several questions, the subject of which can be adapted to educators' needs. It also integrates the Google Blockly graphical programming language, allowing students to learn basic programming and logic principles without needing to understand complex syntax.

Análise exploratória de critérios de implementação de uma rede viária em áreas de montanha

Dissertação apresentada como requisito parcial para obtenção do grau de Mestre em Ciência e Sistemas de Informação Geográfica

A system verification strategy based on the BST infrastructure

A good verification strategy should bring near the simulation and real functioning environments. In this paper we describe a system-level co-verification strategy that uses a common flow for functional simulation, timing simulation and functional debug. This last step requires using a BST infrastructure, now widely available on commercial devices, specially on FPGAs with medium/large pin-counts.

Board-level prototype validation: a built-in controller and extended BST architecture

Prototype validation is a major concern in modern electronic product design and development. Simulation, structural test, functional and timing debug are all forming parts of the validation process, although very often addressed as dissociated tasks. In this paper we describe an integrated approach to board-level prototype validation, based on a set of mandatory/optional BST instructions and a built-in controller for debug and test, that addresses the late mentioned tasks as inherent parts of a whole process

From design-for-test to design-for-debug-and-test: analysis of requirements and limitations for 1149.1

The increasing complexity of VLSI circuits and the reduced accessibility of modern packaging and mounting technologies restrict the usefulness of conventional in-circuit debugging tools, such as in-circuit emulators for microprocessors and microcontrollers. However, this same trend enables the development of more complex products, which in turn require more powerful debugging tools. These conflicting demands could be met if the standard scan test infrastructures now common in most complex components were able to match the debugging requirements of design verification and prototype validation. This paper analyses the main debug requirements in the design of microprocessor-based applications and the feasibility of their implementation using the mandatory, optional and additional operating modes of the standard IEEE 1149.1 test infrastructure.