Parametric and structural self-adaptation of embedded systems using evolvable hardware

Los sistemas empotrados han sido concebidos tradicionalmente como sistemas de procesamiento específicos que realizan una tarea fija durante toda su vida útil. Para cumplir con requisitos estrictos de coste, tamaño y peso, el equipo de diseño debe optimizar su funcionamiento para condiciones muy específicas. Sin embargo, la demanda de mayor versatilidad, un funcionamiento más inteligente y, en definitiva, una mayor capacidad de procesamiento comenzaron a chocar con estas limitaciones, agravado por la incertidumbre asociada a entornos de operación cada vez más dinámicos donde comenzaban a ser desplegados progresivamente. Esto trajo como resultado una necesidad creciente de que los sistemas pudieran responder por si solos a eventos inesperados en tiempo diseño tales como: cambios en las características de los datos de entrada y el entorno del sistema en general; cambios en la propia plataforma de cómputo, por ejemplo debido a fallos o defectos de fabricación; y cambios en las propias especificaciones funcionales causados por unos objetivos del sistema dinámicos y cambiantes. Como consecuencia, la complejidad del sistema aumenta, pero a cambio se habilita progresivamente una capacidad de adaptación autónoma sin intervención humana a lo largo de la vida útil, permitiendo que tomen sus propias decisiones en tiempo de ejecución. Éstos sistemas se conocen, en general, como sistemas auto-adaptativos y tienen, entre otras características, las de auto-configuración, auto-optimización y auto-reparación. Típicamente, la parte soft de un sistema es mayoritariamente la única utilizada para proporcionar algunas capacidades de adaptación a un sistema. Sin embargo, la proporción rendimiento/potencia en dispositivos software como microprocesadores en muchas ocasiones no es adecuada para sistemas empotrados. En este escenario, el aumento resultante en la complejidad de las aplicaciones está siendo abordado parcialmente mediante un aumento en la complejidad de los dispositivos en forma de multi/many-cores; pero desafortunadamente, esto hace que el consumo de potencia también aumente. Además, la mejora en metodologías de diseño no ha sido acorde como para poder utilizar toda la capacidad de cómputo disponible proporcionada por los núcleos. Por todo ello, no se están satisfaciendo adecuadamente las demandas de cómputo que imponen las nuevas aplicaciones. La solución tradicional para mejorar la proporción rendimiento/potencia ha sido el cambio a unas especificaciones hardware, principalmente usando ASICs. Sin embargo, los costes de un ASIC son altamente prohibitivos excepto en algunos casos de producción en masa y además la naturaleza estática de su estructura complica la solución a las necesidades de adaptación. Los avances en tecnologías de fabricación han hecho que la FPGA, una vez lenta y pequeña, usada como glue logic en sistemas mayores, haya crecido hasta convertirse en un dispositivo de cómputo reconfigurable de gran potencia, con una cantidad enorme de recursos lógicos computacionales y cores hardware empotrados de procesamiento de señal y de propósito general. Sus capacidades de reconfiguración han permitido combinar la flexibilidad propia del software con el rendimiento del procesamiento en hardware, lo que tiene la potencialidad de provocar un cambio de paradigma en arquitectura de computadores, pues el hardware no puede ya ser considerado más como estático. El motivo es que como en el caso de las FPGAs basadas en tecnología SRAM, la reconfiguración parcial dinámica (DPR, Dynamic Partial Reconfiguration) es posible. Esto significa que se puede modificar (reconfigurar) un subconjunto de los recursos computacionales en tiempo de ejecución mientras el resto permanecen activos. Además, este proceso de reconfiguración puede ser ejecutado internamente por el propio dispositivo. El avance tecnológico en dispositivos hardware reconfigurables se encuentra recogido bajo el campo conocido como Computación Reconfigurable (RC, Reconfigurable Computing). Uno de los campos de aplicación más exóticos y menos convencionales que ha posibilitado la computación reconfigurable es el conocido como Hardware Evolutivo (EHW, Evolvable Hardware), en el cual se encuentra enmarcada esta tesis. La idea principal del concepto consiste en convertir hardware que es adaptable a través de reconfiguración en una entidad evolutiva sujeta a las fuerzas de un proceso evolutivo inspirado en el de las especies biológicas naturales, que guía la dirección del cambio. Es una aplicación más del campo de la Computación Evolutiva (EC, Evolutionary Computation), que comprende una serie de algoritmos de optimización global conocidos como Algoritmos Evolutivos (EA, Evolutionary Algorithms), y que son considerados como algoritmos universales de resolución de problemas. En analogía al proceso biológico de la evolución, en el hardware evolutivo el sujeto de la evolución es una población de circuitos que intenta adaptarse a su entorno mediante una adecuación progresiva generación tras generación. Los individuos pasan a ser configuraciones de circuitos en forma de bitstreams caracterizados por descripciones de circuitos reconfigurables. Seleccionando aquellos que se comportan mejor, es decir, que tienen una mejor adecuación (o fitness) después de ser evaluados, y usándolos como padres de la siguiente generación, el algoritmo evolutivo crea una nueva población hija usando operadores genéticos como la mutación y la recombinación. Según se van sucediendo generaciones, se espera que la población en conjunto se aproxime a la solución óptima al problema de encontrar una configuración del circuito adecuada que satisfaga las especificaciones. El estado de la tecnología de reconfiguración después de que la familia de FPGAs XC6200 de Xilinx fuera retirada y reemplazada por las familias Virtex a finales de los 90, supuso un gran obstáculo para el avance en hardware evolutivo; formatos de bitstream cerrados (no conocidos públicamente); dependencia de herramientas del fabricante con soporte limitado de DPR; una velocidad de reconfiguración lenta; y el hecho de que modificaciones aleatorias del bitstream pudieran resultar peligrosas para la integridad del dispositivo, son algunas de estas razones. Sin embargo, una propuesta a principios de los años 2000 permitió mantener la investigación en el campo mientras la tecnología de DPR continuaba madurando, el Circuito Virtual Reconfigurable (VRC, Virtual Reconfigurable Circuit). En esencia, un VRC en una FPGA es una capa virtual que actúa como un circuito reconfigurable de aplicación específica sobre la estructura nativa de la FPGA que reduce la complejidad del proceso reconfiguración y aumenta su velocidad (comparada con la reconfiguración nativa). Es un array de nodos computacionales especificados usando descripciones HDL estándar que define recursos reconfigurables ad-hoc: multiplexores de rutado y un conjunto de elementos de procesamiento configurables, cada uno de los cuales tiene implementadas todas las funciones requeridas, que pueden seleccionarse a través de multiplexores tal y como ocurre en una ALU de un microprocesador. Un registro grande actúa como memoria de configuración, por lo que la reconfiguración del VRC es muy rápida ya que tan sólo implica la escritura de este registro, el cual controla las señales de selección del conjunto de multiplexores. Sin embargo, esta capa virtual provoca: un incremento de área debido a la implementación simultánea de cada función en cada nodo del array más los multiplexores y un aumento del retardo debido a los multiplexores, reduciendo la frecuencia de funcionamiento máxima. La naturaleza del hardware evolutivo, capaz de optimizar su propio comportamiento computacional, le convierten en un buen candidato para avanzar en la investigación sobre sistemas auto-adaptativos. Combinar un sustrato de cómputo auto-reconfigurable capaz de ser modificado dinámicamente en tiempo de ejecución con un algoritmo empotrado que proporcione una dirección de cambio, puede ayudar a satisfacer los requisitos de adaptación autónoma de sistemas empotrados basados en FPGA. La propuesta principal de esta tesis está por tanto dirigida a contribuir a la auto-adaptación del hardware de procesamiento de sistemas empotrados basados en FPGA mediante hardware evolutivo. Esto se ha abordado considerando que el comportamiento computacional de un sistema puede ser modificado cambiando cualquiera de sus dos partes constitutivas: una estructura hard subyacente y un conjunto de parámetros soft. De esta distinción, se derivan dos lineas de trabajo. Por un lado, auto-adaptación paramétrica, y por otro auto-adaptación estructural. El objetivo perseguido en el caso de la auto-adaptación paramétrica es la implementación de técnicas de optimización evolutiva complejas en sistemas empotrados con recursos limitados para la adaptación paramétrica online de circuitos de procesamiento de señal. La aplicación seleccionada como prueba de concepto es la optimización para tipos muy específicos de imágenes de los coeficientes de los filtros de transformadas wavelet discretas (DWT, DiscreteWavelet Transform), orientada a la compresión de imágenes. Por tanto, el objetivo requerido de la evolución es una compresión adaptativa y más eficiente comparada con los procedimientos estándar. El principal reto radica en reducir la necesidad de recursos de supercomputación para el proceso de optimización propuesto en trabajos previos, de modo que se adecúe para la ejecución en sistemas empotrados. En cuanto a la auto-adaptación estructural, el objetivo de la tesis es la implementación de circuitos auto-adaptativos en sistemas evolutivos basados en FPGA mediante un uso eficiente de sus capacidades de reconfiguración nativas. En este caso, la prueba de concepto es la evolución de tareas de procesamiento de imagen tales como el filtrado de tipos desconocidos y cambiantes de ruido y la detección de bordes en la imagen. En general, el objetivo es la evolución en tiempo de ejecución de tareas de procesamiento de imagen desconocidas en tiempo de diseño (dentro de un cierto grado de complejidad). En este caso, el objetivo de la propuesta es la incorporación de DPR en EHW para evolucionar la arquitectura de un array sistólico adaptable mediante reconfiguración cuya capacidad de evolución no había sido estudiada previamente. Para conseguir los dos objetivos mencionados, esta tesis propone originalmente una plataforma evolutiva que integra un motor de adaptación (AE, Adaptation Engine), un motor de reconfiguración (RE, Reconfiguration Engine) y un motor computacional (CE, Computing Engine) adaptable. El el caso de adaptación paramétrica, la plataforma propuesta está caracterizada por: • un CE caracterizado por un núcleo de procesamiento hardware de DWT adaptable mediante registros reconfigurables que contienen los coeficientes de los filtros wavelet • un algoritmo evolutivo como AE que busca filtros wavelet candidatos a través de un proceso de optimización paramétrica desarrollado específicamente para sistemas caracterizados por recursos de procesamiento limitados • un nuevo operador de mutación simplificado para el algoritmo evolutivo utilizado, que junto con un mecanismo de evaluación rápida de filtros wavelet candidatos derivado de la literatura actual, asegura la viabilidad de la búsqueda evolutiva asociada a la adaptación de wavelets. En el caso de adaptación estructural, la plataforma propuesta toma la forma de: • un CE basado en una plantilla de array sistólico reconfigurable de 2 dimensiones compuesto de nodos de procesamiento reconfigurables • un algoritmo evolutivo como AE que busca configuraciones candidatas del array usando un conjunto de funcionalidades de procesamiento para los nodos disponible en una biblioteca accesible en tiempo de ejecución • un RE hardware que explota la capacidad de reconfiguración nativa de las FPGAs haciendo un uso eficiente de los recursos reconfigurables del dispositivo para cambiar el comportamiento del CE en tiempo de ejecución • una biblioteca de elementos de procesamiento reconfigurables caracterizada por bitstreams parciales independientes de la posición, usados como el conjunto de configuraciones disponibles para los nodos de procesamiento del array Las contribuciones principales de esta tesis se pueden resumir en la siguiente lista: • Una plataforma evolutiva basada en FPGA para la auto-adaptación paramétrica y estructural de sistemas empotrados compuesta por un motor computacional (CE), un motor de adaptación (AE) evolutivo y un motor de reconfiguración (RE). Esta plataforma se ha desarrollado y particularizado para los casos de auto-adaptación paramétrica y estructural. • En cuanto a la auto-adaptación paramétrica, las contribuciones principales son: – Un motor computacional adaptable mediante registros que permite la adaptación paramétrica de los coeficientes de una implementación hardware adaptativa de un núcleo de DWT. – Un motor de adaptación basado en un algoritmo evolutivo desarrollado específicamente para optimización numérica, aplicada a los coeficientes de filtros wavelet en sistemas empotrados con recursos limitados. – Un núcleo IP de DWT auto-adaptativo en tiempo de ejecución para sistemas empotrados que permite la optimización online del rendimiento de la transformada para compresión de imágenes en entornos específicos de despliegue, caracterizados por tipos diferentes de señal de entrada. – Un modelo software y una implementación hardware de una herramienta para la construcción evolutiva automática de transformadas wavelet específicas. • Por último, en cuanto a la auto-adaptación estructural, las contribuciones principales son: – Un motor computacional adaptable mediante reconfiguración nativa de FPGAs caracterizado por una plantilla de array sistólico en dos dimensiones de nodos de procesamiento reconfigurables. Es posible mapear diferentes tareas de cómputo en el array usando una biblioteca de elementos sencillos de procesamiento reconfigurables. – Definición de una biblioteca de elementos de procesamiento apropiada para la síntesis autónoma en tiempo de ejecución de diferentes tareas de procesamiento de imagen. – Incorporación eficiente de la reconfiguración parcial dinámica (DPR) en sistemas de hardware evolutivo, superando los principales inconvenientes de propuestas previas como los circuitos reconfigurables virtuales (VRCs). En este trabajo también se comparan originalmente los detalles de implementación de ambas propuestas. – Una plataforma tolerante a fallos, auto-curativa, que permite la recuperación funcional online en entornos peligrosos. La plataforma ha sido caracterizada desde una perspectiva de tolerancia a fallos: se proponen modelos de fallo a nivel de CLB y de elemento de procesamiento, y usando el motor de reconfiguración, se hace un análisis sistemático de fallos para un fallo en cada elemento de procesamiento y para dos fallos acumulados. – Una plataforma con calidad de filtrado dinámica que permite la adaptación online a tipos de ruido diferentes y diferentes comportamientos computacionales teniendo en cuenta los recursos de procesamiento disponibles. Por un lado, se evolucionan filtros con comportamientos no destructivos, que permiten esquemas de filtrado en cascada escalables; y por otro, también se evolucionan filtros escalables teniendo en cuenta requisitos computacionales de filtrado cambiantes dinámicamente. Este documento está organizado en cuatro partes y nueve capítulos. La primera parte contiene el capítulo 1, una introducción y motivación sobre este trabajo de tesis. A continuación, el marco de referencia en el que se enmarca esta tesis se analiza en la segunda parte: el capítulo 2 contiene una introducción a los conceptos de auto-adaptación y computación autonómica (autonomic computing) como un campo de investigación más general que el muy específico de este trabajo; el capítulo 3 introduce la computación evolutiva como la técnica para dirigir la adaptación; el capítulo 4 analiza las plataformas de computación reconfigurables como la tecnología para albergar hardware auto-adaptativo; y finalmente, el capítulo 5 define, clasifica y hace un sondeo del campo del hardware evolutivo. Seguidamente, la tercera parte de este trabajo contiene la propuesta, desarrollo y resultados obtenidos: mientras que el capítulo 6 contiene una declaración de los objetivos de la tesis y la descripción de la propuesta en su conjunto, los capítulos 7 y 8 abordan la auto-adaptación paramétrica y estructural, respectivamente. Finalmente, el capítulo 9 de la parte 4 concluye el trabajo y describe caminos de investigación futuros. ABSTRACT Embedded systems have traditionally been conceived to be specific-purpose computers with one, fixed computational task for their whole lifetime. Stringent requirements in terms of cost, size and weight forced designers to highly optimise their operation for very specific conditions. However, demands for versatility, more intelligent behaviour and, in summary, an increased computing capability began to clash with these limitations, intensified by the uncertainty associated to the more dynamic operating environments where they were progressively being deployed. This brought as a result an increasing need for systems to respond by themselves to unexpected events at design time, such as: changes in input data characteristics and system environment in general; changes in the computing platform itself, e.g., due to faults and fabrication defects; and changes in functional specifications caused by dynamically changing system objectives. As a consequence, systems complexity is increasing, but in turn, autonomous lifetime adaptation without human intervention is being progressively enabled, allowing them to take their own decisions at run-time. This type of systems is known, in general, as selfadaptive, and are able, among others, of self-configuration, self-optimisation and self-repair. Traditionally, the soft part of a system has mostly been so far the only place to provide systems with some degree of adaptation capabilities. However, the performance to power ratios of software driven devices like microprocessors are not adequate for embedded systems in many situations. In this scenario, the resulting rise in applications complexity is being partly addressed by rising devices complexity in the form of multi and many core devices; but sadly, this keeps on increasing power consumption. Besides, design methodologies have not been improved accordingly to completely leverage the available computational power from all these cores. Altogether, these factors make that the computing demands new applications pose are not being wholly satisfied. The traditional solution to improve performance to power ratios has been the switch to hardware driven specifications, mainly using ASICs. However, their costs are highly prohibitive except for some mass production cases and besidesthe static nature of its structure complicates the solution to the adaptation needs. The advancements in fabrication technologies have made that the once slow, small FPGA used as glue logic in bigger systems, had grown to be a very powerful, reconfigurable computing device with a vast amount of computational logic resources and embedded, hardened signal and general purpose processing cores. Its reconfiguration capabilities have enabled software-like flexibility to be combined with hardware-like computing performance, which has the potential to cause a paradigm shift in computer architecture since hardware cannot be considered as static anymore. This is so, since, as is the case with SRAMbased FPGAs, Dynamic Partial Reconfiguration (DPR) is possible. This means that subsets of the FPGA computational resources can now be changed (reconfigured) at run-time while the rest remains active. Besides, this reconfiguration process can be triggered internally by the device itself. This technological boost in reconfigurable hardware devices is actually covered under the field known as Reconfigurable Computing. One of the most exotic fields of application that Reconfigurable Computing has enabled is the known as Evolvable Hardware (EHW), in which this dissertation is framed. The main idea behind the concept is turning hardware that is adaptable through reconfiguration into an evolvable entity subject to the forces of an evolutionary process, inspired by that of natural, biological species, that guides the direction of change. It is yet another application of the field of Evolutionary Computation (EC), which comprises a set of global optimisation algorithms known as Evolutionary Algorithms (EAs), considered as universal problem solvers. In analogy to the biological process of evolution, in EHW the subject of evolution is a population of circuits that tries to get adapted to its surrounding environment by progressively getting better fitted to it generation after generation. Individuals become circuit configurations representing bitstreams that feature reconfigurable circuit descriptions. By selecting those that behave better, i.e., with a higher fitness value after being evaluated, and using them as parents of the following generation, the EA creates a new offspring population by using so called genetic operators like mutation and recombination. As generations succeed one another, the whole population is expected to approach to the optimum solution to the problem of finding an adequate circuit configuration that fulfils system objectives. The state of reconfiguration technology after Xilinx XC6200 FPGA family was discontinued and replaced by Virtex families in the late 90s, was a major obstacle for advancements in EHW; closed (non publicly known) bitstream formats; dependence on manufacturer tools with highly limiting support of DPR; slow speed of reconfiguration; and random bitstream modifications being potentially hazardous for device integrity, are some of these reasons. However, a proposal in the first 2000s allowed to keep investigating in this field while DPR technology kept maturing, the Virtual Reconfigurable Circuit (VRC). In essence, a VRC in an FPGA is a virtual layer acting as an application specific reconfigurable circuit on top of an FPGA fabric that reduces the complexity of the reconfiguration process and increases its speed (compared to native reconfiguration). It is an array of computational nodes specified using standard HDL descriptions that define ad-hoc reconfigurable resources; routing multiplexers and a set of configurable processing elements, each one containing all the required functions, which are selectable through functionality multiplexers as in microprocessor ALUs. A large register acts as configuration memory, so VRC reconfiguration is very fast given it only involves writing this register, which drives the selection signals of the set of multiplexers. However, large overheads are introduced by this virtual layer; an area overhead due to the simultaneous implementation of every function in every node of the array plus the multiplexers, and a delay overhead due to the multiplexers, which also reduces maximum frequency of operation. The very nature of Evolvable Hardware, able to optimise its own computational behaviour, makes it a good candidate to advance research in self-adaptive systems. Combining a selfreconfigurable computing substrate able to be dynamically changed at run-time with an embedded algorithm that provides a direction for change, can help fulfilling requirements for autonomous lifetime adaptation of FPGA-based embedded systems. The main proposal of this thesis is hence directed to contribute to autonomous self-adaptation of the underlying computational hardware of FPGA-based embedded systems by means of Evolvable Hardware. This is tackled by considering that the computational behaviour of a system can be modified by changing any of its two constituent parts: an underlying hard structure and a set of soft parameters. Two main lines of work derive from this distinction. On one side, parametric self-adaptation and, on the other side, structural self-adaptation. The goal pursued in the case of parametric self-adaptation is the implementation of complex evolutionary optimisation techniques in resource constrained embedded systems for online parameter adaptation of signal processing circuits. The application selected as proof of concept is the optimisation of Discrete Wavelet Transforms (DWT) filters coefficients for very specific types of images, oriented to image compression. Hence, adaptive and improved compression efficiency, as compared to standard techniques, is the required goal of evolution. The main quest lies in reducing the supercomputing resources reported in previous works for the optimisation process in order to make it suitable for embedded systems. Regarding structural self-adaptation, the thesis goal is the implementation of self-adaptive circuits in FPGA-based evolvable systems through an efficient use of native reconfiguration capabilities. In this case, evolution of image processing tasks such as filtering of unknown and changing types of noise and edge detection are the selected proofs of concept. In general, evolving unknown image processing behaviours (within a certain complexity range) at design time is the required goal. In this case, the mission of the proposal is the incorporation of DPR in EHW to evolve a systolic array architecture adaptable through reconfiguration whose evolvability had not been previously checked. In order to achieve the two stated goals, this thesis originally proposes an evolvable platform that integrates an Adaptation Engine (AE), a Reconfiguration Engine (RE) and an adaptable Computing Engine (CE). In the case of parametric adaptation, the proposed platform is characterised by: • a CE featuring a DWT hardware processing core adaptable through reconfigurable registers that holds wavelet filters coefficients • an evolutionary algorithm as AE that searches for candidate wavelet filters through a parametric optimisation process specifically developed for systems featured by scarce computing resources • a new, simplified mutation operator for the selected EA, that together with a fast evaluation mechanism of candidate wavelet filters derived from existing literature, assures the feasibility of the evolutionary search involved in wavelets adaptation In the case of structural adaptation, the platform proposal takes the form of: • a CE based on a reconfigurable 2D systolic array template composed of reconfigurable processing nodes • an evolutionary algorithm as AE that searches for candidate configurations of the array using a set of computational functionalities for the nodes available in a run time accessible library • a hardware RE that exploits native DPR capabilities of FPGAs and makes an efficient use of the available reconfigurable resources of the device to change the behaviour of the CE at run time • a library of reconfigurable processing elements featured by position-independent partial bitstreams used as the set of available configurations for the processing nodes of the array Main contributions of this thesis can be summarised in the following list. • An FPGA-based evolvable platform for parametric and structural self-adaptation of embedded systems composed of a Computing Engine, an evolutionary Adaptation Engine and a Reconfiguration Engine. This platform is further developed and tailored for both parametric and structural self-adaptation. • Regarding parametric self-adaptation, main contributions are: – A CE adaptable through reconfigurable registers that enables parametric adaptation of the coefficients of an adaptive hardware implementation of a DWT core. – An AE based on an Evolutionary Algorithm specifically developed for numerical optimisation applied to wavelet filter coefficients in resource constrained embedded systems. – A run-time self-adaptive DWT IP core for embedded systems that allows for online optimisation of transform performance for image compression for specific deployment environments characterised by different types of input signals. – A software model and hardware implementation of a tool for the automatic, evolutionary construction of custom wavelet transforms. • Lastly, regarding structural self-adaptation, main contributions are: – A CE adaptable through native FPGA fabric reconfiguration featured by a two dimensional systolic array template of reconfigurable processing nodes. Different processing behaviours can be automatically mapped in the array by using a library of simple reconfigurable processing elements. – Definition of a library of such processing elements suited for autonomous runtime synthesis of different image processing tasks. – Efficient incorporation of DPR in EHW systems, overcoming main drawbacks from the previous approach of virtual reconfigurable circuits. Implementation details for both approaches are also originally compared in this work. – A fault tolerant, self-healing platform that enables online functional recovery in hazardous environments. The platform has been characterised from a fault tolerance perspective: fault models at FPGA CLB level and processing elements level are proposed, and using the RE, a systematic fault analysis for one fault in every processing element and for two accumulated faults is done. – A dynamic filtering quality platform that permits on-line adaptation to different types of noise and different computing behaviours considering the available computing resources. On one side, non-destructive filters are evolved, enabling scalable cascaded filtering schemes; and on the other, size-scalable filters are also evolved considering dynamically changing computational filtering requirements. This dissertation is organized in four parts and nine chapters. First part contains chapter 1, the introduction to and motivation of this PhD work. Following, the reference framework in which this dissertation is framed is analysed in the second part: chapter 2 features an introduction to the notions of self-adaptation and autonomic computing as a more general research field to the very specific one of this work; chapter 3 introduces evolutionary computation as the technique to drive adaptation; chapter 4 analyses platforms for reconfigurable computing as the technology to hold self-adaptive hardware; and finally chapter 5 defines, classifies and surveys the field of Evolvable Hardware. Third part of the work follows, which contains the proposal, development and results obtained: while chapter 6 contains an statement of the thesis goals and the description of the proposal as a whole, chapters 7 and 8 address parametric and structural self-adaptation, respectively. Finally, chapter 9 in part 4 concludes the work and describes future research paths.

Trust and Privacy Solutions Based on Holistic Service Requirements

The products and services designed for Smart Cities provide the necessary tools to improve the management of modern cities in a more efficient way. These tools need to gather citizens’ information about their activity, preferences, habits, etc. opening up the possibility of tracking them. Thus, privacy and security policies must be developed in order to satisfy and manage the legislative heterogeneity surrounding the services provided and comply with the laws of the country where they are provided. This paper presents one of the possible solutions to manage this heterogeneity, bearing in mind these types of networks, such as Wireless Sensor Networks, have important resource limitations. A knowledge and ontology management system is proposed to facilitate the collaboration between the business, legal and technological areas. This will ease the implementation of adequate specific security and privacy policies for a given service. All these security and privacy policies are based on the information provided by the deployed platforms and by expert system processing.

Multiphase Design and Control Techniques Applied to a Forward Micro-Inverter

En la última década la potencia instalada de energía solar fotovoltaica ha crecido una media de un 49% anual y se espera que alcance el 16%del consumo energético mundial en el año 2050. La mayor parte de estas instalaciones se corresponden con sistemas conectados a la red eléctrica y un amplio porcentaje de ellas son instalaciones domésticas o en edificios. En el mercado ya existen diferentes arquitecturas para este tipo de instalaciones, entre las que se encuentras los módulos AC. Un módulo AC consiste en un inversor, también conocido como micro-inversor, que se monta en la parte trasera de un panel o módulo fotovoltaico. Esta tecnología ofrece modularidad, redundancia y la extracción de la máxima potencia de cada panel solar de la instalación. Además, la expansión de esta tecnología posibilitará una reducción de costes asociados a las economías de escala y a la posibilidad de que el propio usuario pueda componer su propio sistema. Sin embargo, el micro-inversor debe ser capaz de proporcionar una ganancia de tensión adecuada para conectar el panel solar directamente a la red, mientras mantiene un rendimiento aceptable en un amplio rango de potencias. Asimismo, los estándares de conexión a red deber ser satisfechos y el tamaño y el tiempo de vida del micro-inversor son factores que han de tenerse siempre en cuenta. En esta tesis se propone un micro-inversor derivado de la topología “forward” controlado en el límite entre los modos de conducción continuo y discontinuo (BCM por sus siglas en inglés). El transformador de la topología propuesta mantiene la misma estructura que en el convertidor “forward” clásico y la utilización de interruptores bidireccionales en el secundario permite la conexión directa del inversor a la red. Asimismo el método de control elegido permite obtener factor de potencia cercano a la unidad con una implementación sencilla. En la tesis se presenta el principio de funcionamiento y los principales aspectos del diseño del micro-inversor propuesto. Con la idea de mantener una solución sencilla y de bajo coste, se ha seleccionado un controlador analógico que está originalmente pensado para controlar un corrector del factor de potencia en el mismo modo de conducción que el micro-inversor “forward”. La tesis presenta las principales modificaciones necesarias, con especial atención a la detección del cruce por cero de la corriente (ZCD por sus siglas en inglés) y la compatibilidad del controlador con la inclusión de un algoritmo de búsqueda del punto de máxima potencia (MPPT por sus siglas en inglés). Los resultados experimentales muestran las limitaciones de la implementación elegida e identifican al transformador como el principal contribuyente a las pérdidas del micro-inversor. El principal objetivo de esta tesis es contribuir a la aplicación de técnicas de control y diseño de sistemas multifase en micro-inversores fotovoltaicos. En esta tesis se van a considerar dos configuraciones multifase diferentes aplicadas al micro-inversor “forward” propuesto. La primera consiste en una variación con conexión paralelo-serie que permite la utilización de transformadores con una relación de vueltas baja, y por tanto bien acoplados, para conseguir una ganancia de tensión adecuada con un mejor rendimiento. Esta configuración emplea el mismo control BCM cuando la potencia extraída del panel solar es máxima. Este método de control implica que la frecuencia de conmutación se incrementa considerablemente cuando la potencia decrece, lo que compromete el rendimiento. Por lo tanto y con la intención de mantener unos bueno niveles de rendimiento ponderado, el micro-inversor funciona en modo de conducción discontinuo (DCM, por sus siglas en inglés) cuando la potencia extraía del panel solar es menor que la máxima. La segunda configuración multifase considerada en esta tesis es la aplicación de la técnica de paralelo con entrelazado. Además se han considerado dos técnicas diferentes para decidir el número de fases activas: dependiendo de la potencia continua extraída del panel solar y dependiendo de la potencia instantánea demandada por el micro-inversor. La aplicación de estas técnicas es interesante en los sistemas fotovoltaicos conectados a la red eléctrica por la posibilidad que brindan de obtener un rendimiento prácticamente plano en un amplio rango de potencia. Las configuraciones con entrelazado se controlan en DCM para evitar la necesidad de un control de corriente, lo que es importante cuando el número de fases es alto. Los núcleos adecuados para todas las configuraciones multifase consideradas se seleccionan usando el producto de áreas. Una vez seleccionados los núcleos se ha realizado un diseño detallado de cada uno de los transformadores. Con la información obtenida de los diseños y los resultados de simulación, se puede analizar el impacto que el número de transformadores utilizados tiene en el tamaño y el rendimiento de las distintas configuraciones. Los resultados de este análisis, presentado en esta tesis, se utilizan posteriormente para comparar las distintas configuraciones. Muchas otras topologías se han presentado en la literatura para abordar los diferentes aspectos a considerar en los micro-inversores, que han sido presentados anteriormente. La mayoría de estas topologías utilizan un transformador de alta frecuencia para solventar el salto de tensión y evitar problemas de seguridad y de puesta a tierra. En cualquier caso, es interesante evaluar si topologías sin aislamiento galvánico son aptas para su utilización como micro-inversores. En esta tesis se presenta una revisión de inversores con capacidad de elevar tensión, que se comparan bajo las mismas especificaciones. El objetivo es proporcionar la información necesaria para valorar si estas topologías son aplicables en los módulos AC. Las principales contribuciones de esta tesis son: • La aplicación del control BCM a un convertidor “forward” para obtener un micro-inversor de una etapa sencillo y de bajo coste. • La modificación de dicho micro-inversor con conexión paralelo-series de transformadores que permite reducir la corriente de los semiconductores y una ganancia de tensión adecuada con transformadores altamente acoplados. • La aplicación de técnicas de entrelazado y decisión de apagado de fases en la puesta en paralelo del micro-inversor “forward”. • El análisis y la comparación del efecto en el tamaño y el rendimiento del incremento del número de transformadores en las diferentes configuraciones multifase. • La eliminación de las medidas y los lazos de control de corriente en las topologías multifase con la utilización del modo de conducción discontinuo y un algoritmo MPPT sin necesidad de medida de corriente. • La recopilación y comparación bajo las mismas especificaciones de topologías inversoras con capacidad de elevar tensión, que pueden ser adecuadas para la utilización como micro-inversores. Esta tesis está estructurada en seis capítulos. El capítulo 1 presenta el marco en que se desarrolla la tesis así como el alcance de la misma. En el capítulo 2 se recopilan las topologías existentes de micro-invesores con aislamiento y aquellas sin aislamiento cuya implementación en un módulo AC es factible. Asimismo se presenta la comparación entre estas topologías bajo las mismas especificaciones. El capítulo 3 se centra en el micro-inversor “forward” que se propone originalmente en esta tesis. La aplicación de las técnicas multifase se aborda en los capítulos 4 y 5, en los que se presentan los análisis en función del número de transformadores. El capítulo está orientado a la propuesta paralelo-serie mientras que la configuración con entrelazado se analiza en el capítulo 5. Por último, en el capítulo 6 se presentan las contribuciones de esta tesis y los trabajos futuros. ABSTRACT In the last decade the photovoltaic (PV) installed power increased with an average growth of 49% per year and it is expected to cover the 16% of the global electricity consumption by 2050. Most of the installed PV power corresponds to grid-connected systems, with a significant percentage of residential installations. In these PV systems, the inverter is essential since it is the responsible of transferring into the grid the extracted power from the PV modules. Several architectures have been proposed for grid-connected residential PV systems, including the AC-module technology. An AC-module consists of an inverter, also known as micro-inverter, which is attached to a PV module. The AC-module technology offers modularity, redundancy and individual MPPT of each module. In addition, the expansion of this technology will enable the possibility of economies of scale of mass market and “plug and play” for the user, thus reducing the overall cost of the installation. However, the micro-inverter must be able to provide the required voltage boost to interface a low voltage PV module to the grid while keeping an acceptable efficiency in a wide power range. Furthermore, the quality standards must be satisfied and size and lifetime of the solutions must be always considered. In this thesis a single-stage forward micro-inverter with boundary mode operation is proposed to address the micro-inverter requirements. The transformer in the proposed topology remains as in the classic forward converter and bidirectional switches in the secondary side allows direct connection to the grid. In addition the selected control strategy allows high power factor current with a simple implementation. The operation of the topology is presented and the main design issues are introduced. With the intention to propose a simple and low-cost solution, an analog controller for a PFC operated in boundary mode is utilized. The main necessary modifications are discussed, with the focus on the zero current detection (ZCD) and the compatibility of the controller with a MPPT algorithm. The experimental results show the limitations of the selected analog controller implementation and the transformer is identified as a main losses contributor. The main objective of this thesis is to contribute in the application of control and design multiphase techniques to the PV micro-inverters. Two different multiphase configurations have been applied to the forward micro-inverter proposed in this thesis. The first one consists of a parallel-series connected variation which enables the use of low turns ratio, i.e. well coupled, transformers to achieve a proper voltage boost with an improved performance. This multiphase configuration implements BCM control at maximum load however. With this control method the switching frequency increases significantly for light load operation, thus jeopardizing the efficiency. Therefore, in order to keep acceptable weighted efficiency levels, DCM operation is selected for low power conditions. The second multiphase variation considered in this thesis is the interleaved configuration with two different phase shedding techniques: depending on the DC power extracted from the PV panel, and depending on the demanded instantaneous power. The application of interleaving techniques is interesting in PV grid-connected inverters for the possibility of flat efficiency behavior in a wide power range. The interleaved variations of the proposed forward micro-inverter are operated in DCM to avoid the current loop, which is important when the number of phases is large. The adequate transformer cores for all the multiphase configurations are selected according to the area product parameter and a detailed design of each required transformer is developed. With this information and simulation results, the impact in size and efficiency of the number of transformer used can be assessed. The considered multiphase topologies are compared in this thesis according to the results of the introduced analysis. Several other topological solutions have been proposed to solve the mentioned concerns in AC-module application. The most of these solutions use a high frequency transformer to boost the voltage and avoid grounding and safety issues. However, it is of interest to assess if the non-isolated topologies are suitable for AC-module application. In this thesis a review of transformerless step-up inverters is presented. The compiled topologies are compared using a set benchmark to provide the necessary information to assess whether non-isolated topologies are suitable for AC-module application. The main contributions of this thesis are: • The application of the boundary mode control with constant off-time to a forward converter, to obtain a simple and low-cost single-stage forward micro-inverter. • A modification of the forward micro-inverter with primary-parallel secondary-series connected transformers to reduce the current stress and improve the voltage gain with highly coupled transformers. •The application of the interleaved configuration with different phase shedding strategies to the proposed forward micro-inverter. • An analysis and comparison of the influence in size and efficiency of increasing the number of transformers in the parallel-series and interleaved multiphase configurations. • Elimination of the current loop and current measurements in the multiphase topologies by adopting DCM operation and a current sensorless MPPT. • A compilation and comparison with the same specifications of suitable non-isolated step-up inverters. This thesis is organized in six chapters. In Chapter 1 the background of single-phase PV-connected systems is discussed and the scope of the thesis is defined. Chapter 2 compiles the existing solutions for isolated micro-inverters and transformerless step-up inverters suitable for AC-module application. In addition, the most convenient non-isolated inverters are compared using a defined benchmark. Chapter 3 focuses on the originally proposed single-stage forward micro-inverter. The application of multiphase techniques is addressed in Chapter 4 and Chapter 5, and the impact in different parameters of increasing the number of phases is analyzed. In Chapter 4 an original primary-parallel secondary-series variation of the forward micro-inverter is presented, while Chapter 5 focuses on the application of the interleaved configuration. Finally, Chapter 6 discusses the contributions of the thesis and the future work.

Diseño de filtros helicoidales de altas prestaciones

El objetivo de este proyecto es el estudio detallado y fabricación de los filtros de cavidades con resonadores helicoidales. Este proyecto está motivado por el hecho de que es una tecnología cada vez más presente en el mercado y su uso resulta muy ´útil en aplicaciones donde se requiere que los componentes sean de tamaño reducido. Esto se debe a que las cavidades helicoidales son de las que presentan menor tamaño para una frecuencia dada. La estructura del proyecto se va a dividir en tres grandes bloques. El primero es el estudio teórico de esta tecnología. En la introducción se verán los principales usos de estos dispositivos, dando ejemplos comerciales, para luego poder compararlos con el prototipo que se ha construido. A continuación, en los primeros capítulos, se detallará la geometría de los resonadores, las ecuaciones que deben aplicarse para calcular las dimensiones y los elementos de diseño. Se comentarán algunas modificaciones opcionales que se pueden aplicar al filtro en el caso de que se requieran especificaciones especiales para la aplicación para la que esté destinado el dispositivo. En segundo lugar se procederá a diseñar modelos de filtros helicoidales para distintas bandas de frecuencia, con el programa de diseño CST Microwave Studio. Estos serán ajustados y parametrizados con el fin de obtener unos requerimientos que serán fijados previamente. Y por ´ultimo se mostrará como ha sido el proceso de prototipado del filtro de tres cavidades para la banda de FM que se ha llevado a cabo y estarán plasmadas las medidas que se han realizado para determinar las características que tiene el prototipo. Este proyecto está planteado como un manual para que el interesado en la fabricación de este tipo de filtros pueda afrontar el diseño desde el inicio y ser capaz de construir un prototipo que cumpla con las características que sean requeridas. ABSTRACT. The main purpose of this project is the detailed study of helical resonator filters and their manufacturing. This technology is increasingly present in the market, and its use is very convenient in applications where it is required for the components to be of reduced size. This is due to helical resonators being smaller than conventional cavity filters for a given frequency. The projects structure will be divided into three sections. First, the theoretical study of this technology will be presented. In the introduction, the main uses of these devices will be shown and commercial examples will be given, which can then be compared with the built prototype. Afterwards, in the first chapters, the geometry of the resonators, the required equations to calculate their dimensions and the design elements will be detailed. Some optional modifications that can be applied to the filter in the case of special specifications will be discussed. Second, some models of helical filters will be designed for different frequency bands, using the design software CST Microwave Studio. These will be adjusted and parameterized in order to meet requirements that will be set previously. Finally, the development of the prototyping process of a three cavities filter for the FM band will be shown, and the measurements that were made to determine the prototypes features will be reflected. This project is designed as a handbook; the individual concerned in the manufacture of these filters should be able to follow the design process from the start and build a prototype that has the required characteristics.

Structural requirements for 5-HT2A and 5-HT1A serotonin receptor potentiation by the biologically active lipid oleamide

Oleamide is an endogenous fatty acid primary amide that possesses sleep-inducing properties in animals and that has been shown to effect serotonergic receptor responses and block gap junction communication. Herein, the potentiation of the 5-HT1A receptor response is disclosed, and a study of the structural features of oleamide required for potentiation of the 5-HT2A and 5-HT1A response to serotonin (5-HT) is described. Of the naturally occurring fatty acids, the primary amide of oleic acid (oleamide) is the most effective at potentiating the 5-HT2A receptor response. The structural features required for activity were found to be highly selective. The presence, position, and stereochemistry of the Δ9-cis double bond is required, and even subtle structural variations reduce or eliminate activity. Secondary or tertiary amides may replace the primary amide but follow a well defined relationship requiring small amide substituents, suggesting that the carboxamide serves as a hydrogen bond acceptor but not donor. Alternative modifications at the carboxamide as well as modifications of the methyl terminus or the hydrocarbon region spanning the carboxamide and double bond typically eliminate activity. A less extensive study of the 5-HT1A potentiation revealed that it is more tolerant and accommodates a wider range of structural modifications. An interesting set of analogs was identified that inhibit rather than potentiate the 5-HT2A, but not the 5-HT1A, receptor response, further suggesting that such analogs may permit the selective modulation of serotonin receptor subtypes and even have opposing effects on the different subtypes.

Full Bridge MMC Converter Optimal Design to HVDC Operational Requirements

This project is funded by RTE, Paris, France

Requirements for heme and thiols for the nonenzymatic modification of nitrotyrosine

Peroxynitrite-dependent formation of nitrotyrosine has been associated with inactivation of various enzymes and proteins possessing functionally important tyrosines. We have previously reported an enzymatic activity modifying the nitrotyrosine residues in nitrated proteins. Here we are describing a nonenzymatic reduction of nitrotyrosine to aminotyrosine, which depends on heme and thiols. Various heme-containing proteins can mediate the reaction, although the reaction also is catalyzed by heme. The reaction is most effective when vicinal thiols are used as reducing agents, although ascorbic acid also can replace thiols with lesser efficiency. The reaction could be inhibited by (z)-1-[2-(2-aminoethyl)-N-(2-ammonioethyl)amino]diazen-1-ium-1, but not other tested NO donors. HPLC with electrochemical detection analysis of the reaction identified aminotyrosine as the only reaction product. The reduction of nitrotyrosine was most effective at a pH close to physiological and was markedly decreased in acidic conditions. Various nitrophenol compounds also were modified in this reaction. Understanding the mechanism of this reaction could help define the enzymatic modification of nitrotyrosine-containing proteins. Furthermore, this also could assist in understanding the role of nitrotyrosine formation and reversal in the regulation of various proteins containing nitrotyrosine. It also could help define the role of nitric oxide and other reactive species in various disease states.

From calcium blips to calcium puffs: Theoretical analysis of the requirements for interchannel communication

In the cytoplasm of cells of different types, discrete clusters of inositol 1,4,5-trisphosphate-sensitive Ca2+ channels generate Ca2+ signals of graded size, ranging from blips, which involve the opening of only one channel, to moderately larger puffs, which result from the concerted opening of a few channels in the same cluster. These channel clusters are of unknown size or geometrical characteristics. The aim of this study was to estimate the number of channels and the interchannel distance within such a cluster. Because these characteristics are not attainable experimentally, we performed computer stochastic simulations of Ca2+ release events. We conclude that, to ensure efficient interchannel communication, as experimentally observed, a typical cluster should contain two or three tens of inositol 1,4,5-trisphosphate-sensitive Ca2+ channels in close contact.

The prion model for [URE3] of yeast: Spontaneous generation and requirements for propagation

The genetic properties of the non-Mendelian element, [URE3], suggest that it is a prion (infectious protein) form of Ure2p, a mediator of nitrogen regulation in Saccharomyces cerevisiae. Into a ure2Δ strain (necessarily lacking [URE3]), we introduced a plasmid overproducing Ure2p. This induced the frequent “spontaneous generation” of [URE3], with properties identical to the original [URE3]. Altering the translational frame only in the prion-inducing domain of URE2 shows that it is Ure2 protein (and not URE2 RNA) that induces appearance of [URE3]. The proteinase K-resistance of Ure2p is unique to [URE3] strains and is not seen in nitrogen regulation of normal strains. The prion-inducing domain of Ure2p (residues 1–65) can propagate [URE3] in the absence of the C-terminal part of the molecule. In contrast, the C-terminal part of Ure2p cannot be converted to the prion (inactive) form without the prion-inducing domain covalently attached. These experiments support the prion model for [URE3] and extend our understanding of its propagation.

Different Tyrosine Autophosphorylation Requirements in Fibroblast Growth Factor Receptor-1 Mediate Urokinase-Type Plasminogen Activator Induction and Mitogenesis

Among the seven tyrosine autophosphorylation sites identified in the intracellular domain of tyrosine kinase fibroblast growth factor receptor-1 (FGFR1), five of them are dispensable for FGFR1-mediated mitogenic signaling. The possibility of dissociating the mitogenic activity of basic FGF (FGF2) from its urokinase-type plasminogen activator (uPA)-inducing capacity both at pharmacological and structural levels prompted us to evaluate the role of these autophosphorylation sites in transducing FGF2-mediated uPA upregulation. To this purpose, L6 myoblasts transfected with either wild-type (wt) or various FGFR1 mutants were evaluated for the capacity to upregulate uPA production by FGF2. uPA was induced in cells transfected with wt-FGFR1, FGFR1-Y463F, -Y585F, -Y730F, -Y766F, or -Y583/585F mutants. In contrast, uPA upregulation was prevented in L6 cells transfected with FGFR1-Y463/583/585/730F mutant (FGFR1–4F) or with FGFR1-Y463/583/585/730/766F mutant (FGFR1–5F) that retained instead a full mitogenic response to FGF2; however, preservation of residue Y730 in FGFR1-Y463/583/585F mutant (FGFR1–3F) and FGFR1-Y463/583/585/766F mutant (FGFR1–4Fbis) allows the receptor to transduce uPA upregulation. Wild-type FGFR1, FGFR1–3F, and FGFR1–4F similarly bind to a 90-kDa tyrosine-phosphorylated protein and activate Shc, extracellular signal-regulated kinase (ERK)2, and JunD after stimulation with FGF2. These data, together with the capacity of the ERK kinase inhibitor PD 098059 to prevent ERK2 activation and uPA upregulation in wt-FGFR1 cells, suggest that signaling through the Ras/Raf-1/ERK kinase/ERK/JunD pathway is necessary but not sufficient for uPA induction in L6 transfectants. Accordingly, FGF2 was able to stimulate ERK1/2 phosphorylation and cell proliferation, but not uPA upregulation, in L6 cells transfected with the FGFR1-Y463/730F mutant, whereas the FGFR1-Y583/585/730F mutant was fully active. We conclude that different tyrosine autophosphorylation requirements in FGFR1 mediate cell proliferation and uPA upregulation induced by FGF2 in L6 cells. In particular, phosphorylation of either Y463 or Y730, dispensable for mitogenic signaling, represents an absolute requirement for FGF2-mediated uPA induction.

New Alleles of the Yeast MPS1 Gene Reveal Multiple Requirements in Spindle Pole Body Duplication

In Saccharomyces cerevisiae, the Mps1p protein kinase is critical for both spindle pole body (SPB) duplication and the mitotic spindle assembly checkpoint. The mps1–1 mutation causes failure early in SPB duplication, and because the spindle assembly checkpoint is also compromised, mps1–1 cells proceed with a monopolar mitosis and rapidly lose viability. Here we report the genetic and molecular characterization of mps1–1 and five new temperature-sensitive alleles of MPS1. Each of the six alleles contains a single point mutation in the region of the gene encoding the protein kinase domain. The mutations affect several residues conserved among protein kinases, most notably the invariant glutamate in subdomain III. In vivo and in vitro kinase activity of the six epitope-tagged mutant proteins varies widely. Only two display appreciable in vitro activity, and interestingly, this activity is not thermolabile under the assay conditions used. While five of the six alleles cause SPB duplication to fail early, yielding cells with a single SPB, mps1–737 cells proceed into SPB duplication and assemble a second SPB that is structurally defective. This phenotype, together with the observation of intragenic complementation between this unique allele and two others, suggests that Mps1p is required for multiple events in SPB duplication.

Amino Acid Sequence Requirements of the Transmembrane and Cytoplasmic Domains of Influenza Virus Hemagglutinin for Viable Membrane Fusion

The amino acid sequence requirements of the transmembrane (TM) domain and cytoplasmic tail (CT) of the hemagglutinin (HA) of influenza virus in membrane fusion have been investigated. Fusion properties of wild-type HA were compared with those of chimeras consisting of the ectodomain of HA and the TM domain and/or CT of polyimmunoglobulin receptor, a nonviral integral membrane protein. The presence of a CT was not required for fusion. But when a TM domain and CT were present, fusion activity was greater when they were derived from the same protein than derived from different proteins. In fact, the chimera with a TM domain of HA and truncated CT of polyimmunoglobulin receptor did not support full fusion, indicating that the two regions are not functionally independent. Despite the fact that there is wide latitude in the sequence of the TM domain that supports fusion, a point mutation of a semiconserved residue within the TM domain of HA inhibited fusion. The ability of a foreign TM domain to support fusion contradicts the hypothesis that a pore is composed solely of fusion proteins and supports the theory that the TM domain creates fusion pores after a stage of hemifusion has been achieved.

Stimulation of β1-Integrin Function by Epidermal Growth Factor and Heregulin-β Has Distinct Requirements for erbB2 but a Similar Dependence on Phosphoinositide 3-OH Kinase

Integrins and growth factor receptors are important participants in cellular adhesion and migration. The EGF receptor (EGFR) family of tyrosine kinases and the β1-integrin adhesion receptors are of particular interest, given the implication for their involvement in the initiation and progression of tumorigenesis. We used adhesion and chemotaxis assays to further elucidate the relationship between these two families of transmembrane signaling molecules. Specifically, we examined integrin-mediated adhesive and migratory characteristics of the metastatic breast carcinoma cell line MDA-MB-435 in response to stimulation with growth factors that bind to and activate the EGFR or erbB3 in these cells. Although ligand engagement of the EGFR stimulated modest β1-dependent increases in cell adhesion and motility, heregulin-β (HRGβ) binding to the erbB3 receptor initiated rapid and potent induction of breast carcinoma cell adhesion and migration and required dimerization of erbB3 with erbB2. Pharmacologic inhibitors of phosphoinositide 3-OH kinase (PI 3-K) or transient expression of dominant negative forms of PI 3-K inhibited both EGF- and HRGβ-mediated adhesion and potently blocked HRGβ- and EGF-induced cell motility. Our results illustrate the critical role of PI 3-K activity in signaling pathways initiated by the EGFR or erbB3 to up-regulate β1-integrin function.

Characterization of Cell–Matrix Adhesion Requirements for the Formation of Fascin Microspikes

Cell adhesion to thrombospondin-1 (TSP-1) correlates with assembly of cell–substratum contact structures that contain fascin microspikes. In this analysis, cell-matrix requirements for assembly of fascin microspikes were examined in detail. In six cell lines, cell spreading on a TSP-1 substratum correlated with expression of fascin protein and formation of fascin microspikes. Microspikes were not formed by H9c2 cells adherent on fibronectin, vitronectin, collagen IV, or platelet factor 4. However, both fascin microspikes and focal contacts were assembled by cells adherent on laminin-1. Using mixed substrata containing different proportions of TSP-1, and fibronectin, fascin microspike formation by H9c2 and C2C12 cells was found to be reduced on substrata containing 25% fibronectin and abolished on substrata containing 75% fibronectin. Adhesion to intermediate mixtures of TSP-1 and fibronectin resulted in coassembly of fascin microspikes and focal contacts, colocalization of fascin with actin stress fiber bundles and altered distributions of β1 integrins, cortical α-actinin, and tropomyosin. In cells adherent on 50% TSP-1:50% fibronectin, GRGDSP peptide treatment decreased focal contact assembly and altered cytoskeletal organization but did not inhibit microspike assembly. Treatment with chondroitin sulfate A or p-nitrophenol β-d-xylopyranoside decreased microspike formation and modified cytoskeletal organization but did not inhibit focal contact formation. In polarized migratory and postmitotic C2C12 cells, fascin microspikes and ruffles were localized at leading edges and TSP matrix deposition was also concentrated in this region. Depletion of matrix TSP by heparin treatment correlated with decreased microspike formation and cell motility. Thus, the balance of adhesive receptors ligated at the cell surface during initial cell–matrix attachment serves to regulate the type of substratum adhesion contact assembled and subsequent cytoskeletal organization. A role for fascin microspikes in cell motile behavior is indicated.

Transfected Drosophila cells as a probe for defining the minimal requirements for stimulating unprimed CD8+ T cells

Stimulation of naive T cells by antigen-presenting cells (APC) is thought to involve two qualitatively different signals: signal one results from T-cell receptor (TCR) recognition of antigenic peptides bound to major histocompatibility complex (MHC) molecules, whereas signal two reflects contact with one or more costimulatory molecules. The requirements for stimulating naive T cells were studied with MHC class I-restricted CD8+ T cells from a T-cell receptor transgenic line, with defined peptides as antigen and transfected Drosophila cells as APC. Three main findings are reported. First, stimulation of naive T cells via signal one alone (MHC plus peptide) was essentially nonimmunogenic; thus T cells cultured with peptides presented by MHC class I-transfected Drosophila APC lacking costimulatory molecules showed little or no change in their surface phenotype. Second, cotransfection of two costimulatory molecules, B7-1 and intercellular adhesion molecule 1 (ICAM-1), converted class I+ Drosophila cells to potent APC capable of inducing strong T-proliferative responses and cytokine (interleukin 2) production. Third, B7-1 and ICAM-1 acted synergistically, indicating that signal two is complex; synergy between B7-1 and ICAM-1 varied from moderate to extreme and was influenced by both the dose and affinity of the peptide used and the parameter of T-cell activation studied. Transfected Drosophila cells are thus a useful tool for examining the minimal APC requirements for naive T cells.