Near-field enhancement for infrared sensor applications

A detailed investigation on planar two dimensional metallodielectric dipole arrays with enhanced near-fields for sensing applications was carried out. Two approaches for enhancing the near-fields and increasing the quality factor were studied. The reactive power stored in the vicinity of the array at resonance increases rapidly with increasing periodicity. Higher quality factors are produced as a result. The excitation of the odd mode in the presence of a perturbation gives rise to a sharp resonance with near-field enhanced by at least an order of magnitude compared to unperturbed arrays. The trade-off between near-field enhancement and thermal losses was also studied, and the effect of supporting dielectric layers on thermal losses and quality factors were examined. Secondary transmissions due to the dielectric alone were found to enhance and reduce cyclically the quality factor as a function of the thickness of the dielectric material. The performance of a perturbed frequency selective surface in sensing nearby materials was investigated. Finally, unperturbed and perturbed arrays working at infrared frequencies were demonstrated experimentally. (C) 2011 Society of Photo-Optical Instrumentation Engineers (SPIE). [DOI: 10.1117/1.3604785]

A Pipeline Interleaved Heterogeneous SIMD Soft Processor Array Architecture for MIMO-OFDM Detection

The most promising way to maintain reliable data transfer across the rapidly fluctuating channels used by next generation multiple-input multiple-output communications schemes is to exploit run-time variable modulation and antenna configurations. This demands that the baseband signal processing architectures employed in the communications terminals must provide low cost and high performance with runtime reconfigurability. We present a softcore-processor based solution to this issue, and show for the first time, that such programmable architectures can enable real-time data operation for cutting-edge standards
such as 802.11n; furthermore, by exploiting deep processing pipelines and interleaved task execution, the cost and performance of these architectures is shown to be on a par with traditional dedicated circuit based solutions. We believe this to be the first such programmable architecture to achieve this, and the combination of implementation efficiency and programmability makes this implementation style the most promising approach for hosting such dynamic architectures.

Effect of weak hydrogen bonding and included solvent on the crystal structure of the square-planar complex trans-Pt{PPh2(C16H15)}(2)Cl-2

Crystallisation of the square-planar complex trans-Pt{PPh2(C16H15)}(2)Cl-2 from dichloromethane-diethyl ether (1:1) affords two different solvates; trans-Pt{PPh2(C16H15)}(2)Cl-2. CH2Cl2 1 and trans-Pt{PPh2(C16H15)}(2)Cl-2. Et2O 2; the CH2Cl2 forms H-bonding interactions with the complex whereas the Et2O participates only in weak van der Waals interactions; these differences arise from the different hydrogen-bonding characteristics of each solvent.

QCA Systolic array design

Quantum-dot Cellular Automata (QCA) technology is a promising potential alternative to CMOS technology. To explore the characteristics of QCA and suitable design methodologies, digital circuit design approaches have been investigated. Due to the inherent wire delay in QCA, pipelined architectures appear to be a particularly suitable design technique. Also, because of the pipeline nature of QCA technology, it is not suitable for complicated control system design. Systolic arrays take advantage of pipelining, parallelism and simple local control. Therefore, an investigation into these architectures in QCA technology is provided in this paper. Two case studies, (a matrix multiplier and a Galois Field multiplier) are designed and analyzed based on both multilayer and coplanar crossings. The performance of these two types of interconnections are compared and it is found that even though coplanar crossings are currently more practical, they tend to occupy a larger design area and incur slightly more delay. A general semi-conductor QCA systolic array design methodology is also proposed. It is found that by applying a systolic array structure in QCA design, significant benefits can be achieved particularly with large systolic arrays, even more so than when applied in CMOS-based technology.