935 resultados para IP traceback


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The success of an ABV IP depends highly on the associated debugging environment. An efficient debugging environment helps the user to find out the exact location of the failure. Moreover, it provides information to the user in a refined detail of abstraction and permit adequate interaction. It has also been realized that adequate visualization support helps in tracking the behavioral aspects of the Design Under Test (DUT). Currently, the debugging tools provide information in the signal level and do not provide any information about the high-level behavior of the DUT. We present a debugging framework that takes the design specification, assertions and the user intent in a simple format and provides detailed information by processing the design trace on-line, or off-line. We also present a visualization framework to ease the debugging procedure. We have experimented with industrial standard on-chip bus protocols that ensure that this utility can be incorporated successfully in the present functional verification flow.

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Continuous advances in VLSI technology have made implementation of very complicated systems possible. Modern System-on -Chips (SoCs) have many processors, IP cores and other functional units. As a result, complete verification of whole systems before implementation is becoming infeasible; hence it is likely that these systems may have some errors after manufacturing. This increases the need to find design errors in chips after fabrication. The main challenge for post-silicon debug is the observability of the internal signals. Post-silicon debug is the problem of determining what's wrong when the fabricated chip of a new design behaves incorrectly. This problem now consumes over half of the overall verification effort on large designs, and the problem is growing worse.Traditional post-silicon debug methods concentrate on functional parts of systems and provide mechanisms to increase the observability of internal state of systems. Those methods may not be sufficient as modern SoCs have lots of blocks (processors, IP cores, etc.) which are communicating with one another and communication is another source of design errors. This tutorial will be provide an insight into various observability enhancement techniques, on chip instrumentation techniques and use of high level models to support the debug process targeting both inside blocks and communication among them. It will also cover the use of formal methods to help debug process.

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This paper proposes a Petri net model for a commercial network processor (Intel iXP architecture) which is a multithreaded multiprocessor architecture. We consider and model three different applications viz., IPv4 forwarding, network address translation, and IP security running on IXP 2400/2850. A salient feature of the Petri net model is its ability to model the application, architecture and their interaction in great detail. The model is validated using the Intel proprietary tool (SDK 3.51 for IXP architecture) over a range of configurations. We conduct a detailed performance evaluation, identify the bottleneck resource, and propose a few architectural extensions and evaluate them in detail.

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In order to improve the tracking and erosion performance of outdoor polymeric silicone rubber (SR) insulators used in HV power transmission lines, micron sized inorganic fillers are usually added to the base SR matrix. In addition, insulators used in high voltage dc transmission lines are designed to have increased creepage distance to mitigate the tracking and erosion problems. ASTM D2303 standard gives a procedure for finding the tracking and erosion resistance of outdoor polymeric insulator weathershed material samples under laboratory conditions for ac voltages. In this paper, inclined plane (IP) tracking and erosion tests similar to ASTM D2303 were conducted under both positive and negative dc voltages for silicone rubber samples filled with micron and nano sized particles to understand the phenomena occurring during such tests. Micron sized Alumina Trihydrate (ATH) and nano sized alumina fillers were added to silicone rubber matrix to improve the resistance to tracking and erosion. The leakage current during the tests and the eroded mass at the end of the tests were monitored. Scanning Electron Microscopy (SEM) and Energy dispersive Xray (EDX) studies were conducted to understand the filler dispersion and the changes in surface morphology in both nanocomposite and microcomposite samples. The results suggest that nanocomposites performed better than microcomposites even for a small filler loading (4%) for both positive and negative dc stresses. It was also seen that the tracking and erosion performance of silicone rubber is better under negative dc as compared to positive dc voltage. EDX studies showed migration of different ions onto the surface of the sample during the IP test under positive dc which has led to an inferior performance as compared to the performance under negative dc.

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Pricing is an effective tool to control congestion and achieve quality of service (QoS) provisioning for multiple differentiated levels of service. In this paper, we consider the problem of pricing for congestion control in the case of a network of nodes with multiple queues and multiple grades of service. We present a closed-loop multi-layered pricing scheme and propose an algorithm for finding the optimal state dependent price levels for individual queues, at each node. This is different from most adaptive pricing schemes in the literature that do not obtain a closed-loop state dependent pricing policy. The method that we propose finds optimal price levels that are functions of the queue lengths at individual queues. Further, we also propose a variant of the above scheme that assigns prices to incoming packets at each node according to a weighted average queue length at that node. This is done to reduce frequent price variations and is in the spirit of the random early detection (RED) mechanism used in TCP/IP networks. We observe in our numerical results a considerable improvement in performance using both of our schemes over that of a recently proposed related scheme in terms of both throughput and delay performance. In particular, our first scheme exhibits a throughput improvement in the range of 67-82% among all routes over the above scheme. (C) 2011 Elsevier B.V. All rights reserved.

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In this paper we study the problem of designing SVM classifiers when the kernel matrix, K, is affected by uncertainty. Specifically K is modeled as a positive affine combination of given positive semi definite kernels, with the coefficients ranging in a norm-bounded uncertainty set. We treat the problem using the Robust Optimization methodology. This reduces the uncertain SVM problem into a deterministic conic quadratic problem which can be solved in principle by a polynomial time Interior Point (IP) algorithm. However, for large-scale classification problems, IP methods become intractable and one has to resort to first-order gradient type methods. The strategy we use here is to reformulate the robust counterpart of the uncertain SVM problem as a saddle point problem and employ a special gradient scheme which works directly on the convex-concave saddle function. The algorithm is a simplified version of a general scheme due to Juditski and Nemirovski (2011). It achieves an O(1/T-2) reduction of the initial error after T iterations. A comprehensive empirical study on both synthetic data and real-world protein structure data sets show that the proposed formulations achieve the desired robustness, and the saddle point based algorithm outperforms the IP method significantly.

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Present study performs the spatial and temporal trend analysis of annual, monthly and seasonal maximum and minimum temperatures (t(max), t(min)) in India. Recent trends in annual, monthly, winter, pre-monsoon, monsoon and post-monsoon extreme temperatures (t(max), t(min)) have been analyzed for three time slots viz. 1901-2003,1948-2003 and 1970-2003. For this purpose, time series of extreme temperatures of India as a whole and seven homogeneous regions, viz. Western Himalaya (WH), Northwest (NW), Northeast (NE), North Central (NC), East coast (EC), West coast (WC) and Interior Peninsula (IP) are considered. Rigorous trend detection analysis has been exercised using variety of non-parametric methods which consider the effect of serial correlation during analysis. During the last three decades minimum temperature trend is present in All India as well as in all temperature homogeneous regions of India either at annual or at any seasonal level (winter, pre-monsoon, monsoon, post-monsoon). Results agree with the earlier observation that the trend in minimum temperature is significant in the last three decades over India (Kothawale et al., 2010). Sequential MK test reveals that most of the trend both in maximum and minimum temperature began after 1970 either in annual or seasonal levels. (C) 2012 Elsevier B.V. All rights reserved.

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There are many wireless sensor network(WSN) applications which require reliable data transfer between the nodes. Several techniques including link level retransmission, error correction methods and hybrid Automatic Repeat re- Quest(ARQ) were introduced into the wireless sensor networks for ensuring reliability. In this paper, we use Automatic reSend request(ASQ) technique with regular acknowledgement to design reliable end-to-end communication protocol, called Adaptive Reliable Transport(ARTP) protocol, for WSNs. Besides ensuring reliability, objective of ARTP protocol is to ensure message stream FIFO at the receiver side instead of the byte stream FIFO used in TCP/IP protocol suite. To realize this objective, a new protocol stack has been used in the ARTP protocol. The ARTP protocol saves energy without affecting the throughput by sending three different types of acknowledgements, viz. ACK, NACK and FNACK with semantics different from that existing in the literature currently and adapting to the network conditions. Additionally, the protocol controls flow based on the receiver's feedback and congestion by holding ACK messages. To the best of our knowledge, there has been little or no attempt to build a receiver controlled regularly acknowledged reliable communication protocol. We have carried out extensive simulation studies of our protocol using Castalia simulator, and the study shows that our protocol performs better than related protocols in wireless/wire line networks, in terms of throughput and energy efficiency.

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TCP attacks are the major problem faced by Mobile Ad hoc Networks (MANETs) due to its limited network and host resources. Attacker traceback is a promising solution which allows a victim to identify the exact location of the attacker and hence enables the victim to take proper countermeasure near attack origins, for forensics and to discourage attackers from launching the attacks. However, attacker traceback in MANET is a challenging problem due to dynamic network topology, limited network and host resources such as memory, bandwidth and battery life. We introduce a novel method of TCP attacker Identification in MANET using the Traffic History - MAITH. Based on the comprehensive evaluation based on simulations, we showed that MAITH can successfully track down the attacker under diverse mobile multi-hop network environment with low communication, computation, and memory overhead.

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The influence of microstructure and texture developed by different modes of hot cross-rolling on in-plane anisotropy (A (IP)) of yield strength, work hardening behavior, and anisotropy of Knoop hardness (KHN) yield locus has been investigated. The A (IP) and work hardening behavior are evaluated by tensile testing at 0 deg, 45 deg, and 90 deg to the rolling direction, while yield loci have been generated by directional KHN measurements. It has been observed that specimens especially in the peak-aged temper, in spite of having a strong, rotated Brass texture, show low A (IP). The results are discussed on the basis of Schmid factor analyses in conjunction with microstructural features, namely grain morphology and precipitation effects. For the specimen having a single-component texture, the yield strength variation as a function of orientation can be rationalized by the Schmid factor analysis of a perfectly textured material behaving as a quasi-single crystal. The work hardening behavior is significantly affected by the presence of solute in the matrix and the state of precipitation rather than texture, while yield loci derived from KHN measurements reiterate the low anisotropy of the materials. Theoretic yield loci calculated from the texture data using the visco-plastic self-consistent model and Hill's anisotropic equation are compared with that obtained experimentally.

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Cells and metabolic products of Bacillus subtilis were used in microbially-induced flocculation and flotation to separate pyrite from galena. Enhanced selective affinity of bacterial cells towards pyrite was observed when compared to galena through adsorption studies. Both extracellular (EP) and intracellular (IP) bacterial proteins were isolated from B. subtilis before and after interaction with the minerals and their profiles established through SDS-PAGE. Protein fractions exhibited significant surface affinity towards galena when compared to pyrite. Presence of galena during bacterial growth promoted increased generation of extracellular proteins, while that of pyrite resulted in enhanced production of exopolysaccharides. Galena surfaces were rendered hydrophobic after bacterial interaction.

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The problem of designing good Space-Time Block Codes (STBCs) with low maximum-likelihood (ML) decoding complexity has gathered much attention in the literature. All the known low ML decoding complexity techniques utilize the same approach of exploiting either the multigroup decodable or the fast-decodable (conditionally multigroup decodable) structure of a code. We refer to this well known technique of decoding STBCs as Conditional ML (CML) decoding. In [1], we introduced a framework to construct ML decoders for STBCs based on the Generalized Distributive Law (GDL) and the Factor-graph based Sum-Product Algorithm, and showed that for two specific families of STBCs, the Toepltiz codes and the Overlapped Alamouti Codes (OACs), the GDL based ML decoders have strictly less complexity than the CML decoders. In this paper, we introduce a `traceback' step to the GDL decoding algorithm of STBCs, which enables roughly 4 times reduction in the complexity of the GDL decoders proposed in [1]. Utilizing this complexity reduction from `traceback', we then show that for any STBC (not just the Toeplitz and Overlapped Alamouti Codes), the GDL decoding complexity is strictly less than the CML decoding complexity. For instance, for any STBC obtained from Cyclic Division Algebras that is not multigroup or conditionally multigroup decodable, the GDL decoder provides approximately 12 times reduction in complexity compared to the CML decoder. Similarly, for the Golden code, which is conditionally multigroup decodable, the GDL decoder is only about half as complex as the CML decoder.

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Alternating Differential Scanning Calorimetric (ADSC) studies on quaternary Ge15Te80-xIn5Agx glasses show the non-reversing enthalpy (Delta H-NR) at T-g to exhibit a broad global minimum in the 8% <= x <= 16% range of Ag, an observation that is taken evidence for existence of an Intermediate Phase (IP) in that range. Glasses at x < 8% are in the flexible phase while those at x > 16% in the stressed-rigid phase. The nature of crystalline phases formed upon crystallization of bulk glasses are elucidated by XRD studies, and reveal presence of Te, GeTe, Ag8GeTe6, AgTe, In2Te3 and In4Te3 phases. These experiments also reveal that the fraction of Ag- bearing phases increases while those of Te- bearing ones decreases with increasing x, suggesting progressive replacement of Te-Te bonds by Ag-Te bonds. (C) 2013 Elsevier Ltd. All rights reserved.

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Micro-Raman studies are conducted on as-quenched and annealed Ge15Te80 -_xIn5Agx glasses to probe the structural network and its evolution with composition. These studies reveal the presence of tetrahedral GeTe4 structural units in as-quenched samples. Specific signatures of the intermediate phase (IP) are observed in the composition dependence of Raman frequencies and corresponding intensities of different modes in the composition range, 8 <= x <= 16. In addition, the Raman peak positions are found to shift with silver doping. Apart from the Raman results, the compositional dependence of density, molar volume and thermal diffusivity, observed in the present study, confirms the presence of the intermediate phase. In thermally annealed samples, a unique variation of Raman wave-numbers in the intermediate region is observed due to the retention of some of the local structure even after the sample is crystallized. The observed Raman peaks are attributed to crystalline tellurium and silver lattice vibrational modes. Based on our present and earlier studies, we propose the occurrence of three thresholds in Ge15Te80 - xIn5Agx glasses, namely percolation of rigidity, percolation of stress and the onset of chemical phase separation on a nanoscale at 8%, 16% and 20% of silver concentration respectively. (C) 2014 Elsevier B.V. All rights reserved.

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The growing number of applications and processing units in modern Multiprocessor Systems-on-Chips (MPSoCs) come along with reduced time to market. Different IP cores can come from different vendors, and their trust levels are also different, but typically they use Network-on-Chip (NoC) as their communication infrastructure. An MPSoC can have multiple Trusted Execution Environments (TEEs). Apart from performance, power, and area research in the field of MPSoC, robust and secure system design is also gaining importance in the research community. To build a secure system, the designer must know beforehand all kinds of attack possibilities for the respective system (MPSoC). In this paper we survey the possible attack scenarios on present-day MPSoCs and investigate a new attack scenario, i.e., router attack targeted toward NoC architecture. We show the validity of this attack by analyzing different present-day NoC architectures and show that they are all vulnerable to this type of attack. By launching a router attack, an attacker can control the whole chip very easily, which makes it a very serious issue. Both routing tables and routing logic-based routers are vulnerable to such attacks. In this paper, we address attacks on routing tables. We propose different monitoring-based countermeasures against routing table-based router attack in an MPSoC having multiple TEEs. Synthesis results show that proposed countermeasures, viz. Runtime-monitor, Restart-monitor, Intermediate manager, and Auditor, occupy areas that are 26.6, 22, 0.2, and 12.2 % of a routing table-based router area. Apart from these, we propose Ejection address checker and Local monitoring module inside a router that cause 3.4 and 10.6 % increase of a router area, respectively. Simulation results are also given, which shows effectiveness of proposed monitoring-based countermeasures.