Low Complexity All-Pass Based Polyphase Decimation Filters for ECG Monitoring

This paper presents a low complexity high efficiency decimation filter which can be employed in EletroCardioGram (ECG) acquisition systems. The decimation filter with a decimation ratio of 128 works along with a third order sigma delta modulator. It is designed in four stages to reduce cost and power consumption. The work reported here provides an efficient approach for the decimation process for high resolution biomedical data conversion applications by employing low complexity two-path all-pass based decimation filters. The performance of the proposed decimation chain was validated by using the MIT-BIH arrhythmia database and comparative simulations were conducted with the state of the art.

An FPGA based decimation filter processor design for real-time continuous-time Σ−Δ modulator performance measurement and evaluation

This paper reports on a Field Programmable Gate Array (FPGA) implementation as well as prototyping for real-time testing of a low complexity high efficiency decimation filter processor which is deployed in conjunction with a custom built low-power jitter insensitive Continuous Time (CT) Sigma-Delta (Σ-Δ) Modulator to measure and assess its performance. The CT Σ-Δ modulator/decimation filter cascade can be used in integrated all-digital microphone interfaces for a variety of applications including mobile phone handsets, wireless handsets as well as other applications requiring all-digital microphones. The work reported here concentrates on the design and implementation as well as prototyping on a Xilinx Spartan 3 FPGA development system and real-time testing of the decimation processing part deploying All-Pass based structures to process the bit stream coming from CT Σ-Δ modulator hence measuring in real-time and fully assessing the modulator's performance.

Design Techniques for Sigmadelta based ADC for Wireless Applications

Analog-to digital Converters (ADC) have an important impact on the overall performance of signal processing system. This research is to explore efficient techniques for the design of sigma-delta ADC,specially for multi-standard wireless tranceivers. In particular, the aim is to develop novel models and algorithms to address this problem and to implement software tools which are avle to assist the designer's decisions in the system-level exploration phase. To this end, this thesis presents a framework of techniques to design sigma-delta analog to digital converters.A2-2-2 reconfigurable sigma-delta modulator is proposed which can meet the design specifications of the three wireless communication standards namely GSM,WCDMA and WLAN. A sigma-delta modulator design tool is developed using the Graphical User Interface Development Environment (GUIDE) In MATLAB.Genetic Algorithm(GA) based search method is introduced to find the optimum value of the scaling coefficients and to maximize the dynamic range in a sigma-delta modulator.

Efficient Transmitter/Receiver Architectures for High Performance Wireless Applications

The thesis focuses on efficient design methods and reconfiguration architectures suitable for higher performance wireless communication .The work presented in this thesis describes the development of compact,inexpensive and low power communication devices that are robust,testable and capable of handling multiple communication standards.A new multistandard Decimation Filter Design Toolbox is developed in MATLAB GUIDE environment.RNS based dual-mode decimation filters reconfigurable for WCDMA/WiMAX and WCDMA/WLANa standards are designed and implemented.It offers high speed operation with lesser area requirement and lower dynamic power dissipation.A novel sigma-delta based direct analog-to-residue converter that reduces the complexity of RNS conversion circuitry is presented.The performance of an OFDM communication system with a new RRNS-convolutional concatenated coding is analysed and improved BER performance is obtained under different channel conditions. Easily testable MAC units for filters are presented using Reed-Muller logic for realization.

RNS based programmable multi-mode decimation filter for WCDMA and WiMAX

The recent trends envisage multi-standard architectures as a promising solution for the future wireless transceivers to attain higher system capacities and data rates. The computationally intensive decimation filter plays an important role in channel selection for multi-mode systems. An efficient reconfigurable implementation is a key to achieve low power consumption. To this end, this paper presents a dual-mode Residue Number System (RNS) based decimation filter which can be programmed for WCDMA and 802.16e standards. Decimation is done using multistage, multirate finite impulse response (FIR) filters. These FIR filters implemented in RNS domain offers high speed because of its carry free operation on smaller residues in parallel channels. Also, the FIR filters exhibit programmability to a selected standard by reconfiguring the hardware architecture. The total area is increased only by 24% to include WiMAX compared to a single mode WCDMA transceiver. In each mode, the unused parts of the overall architecture is powered down and bypassed to attain power saving. The performance of the proposed decimation filter in terms of critical path delay and area are tabulated.

Decimation Filter Design Toolbox for Multi-Standard Wireless Transceivers using MATLAB.

The demand for new telecommunication services requiring higher capacities, data rates and different operating modes have motivated the development of new generation multi-standard wireless transceivers. A multi-standard design often involves extensive system level analysis and architectural partitioning, typically requiring extensive calculations. In this research, a decimation filter design tool for wireless communication standards consisting of GSM, WCDMA, WLANa, WLANb, WLANg and WiMAX is developed in MATLAB® using GUIDE environment for visual analysis. The user can select a required wireless communication standard, and obtain the corresponding multistage decimation filter implementation using this toolbox. The toolbox helps the user or design engineer to perform a quick design and analysis of decimation filter for multiple standards without doing extensive calculation of the underlying methods.

Um microprocessador com capacidades analógicas

Este trabalho apresenta um estudo, implementação e simulação de geradores de sinais analógicos usando-se circuitos digitais, em forma de CORE, integrando-se este com o microprocessador Risco. As principais características procuradas no gerador de sinais são: facilidade de implementação em silício, programabilidade tanto em freqüência quanto em amplitude, qualidade do sinal e facilidade de integração com um microprocessador genérico. Foi feito um estudo sobre a geração convencional de sinais analógicos, dando-se ênfase em alguns tipos específicos de circuitos como circuitos osciladores sintonizados, multivibradores, geradores de sinais triangulares e síntese de freqüência digital direta. Foi feito também um estudo sobre conversão digital-analógica, onde foram mostrados alguns tipos básicos de conversores D/A. Além disso foram abordadas questões como a precisão desses conversores, tipos digitais de conversores digitalanalógico, circuitos geradores de sinais e as fontes mais comuns de erros na conversão D/A. Dando-se ênfase a um tipo específico de conversor D/A, o qual foi utilizado nesse trabalho, abordou-se a questão da conversão sigma-delta, concentrando-se principalmente no ciclo de formatação de ruído. Dentro desse assunto foram abordados o laço sigma-delta, as estruturas de realimentação do erro, estruturas em cascata, e também o laço quantizador. Foram abordados vários circuitos digitais capazes de gerar sinais analógicos, principalmente senóides. Além de geradores de senóides simples, também se abordou a geração de sinais multi-tom, geração de outros tipos de sinais baseando-se no gerador de senóides e também foi apresentado um gerador de funções. Foram mostradas implementações e resultados dessas. Iniciando-se pelo microprocessador Risco, depois o gerador de sinais, o teste deste, a integração do microprocessador com o gerador de sinais e finalmente a implementação standard-cell do leiaute desse sistema. Por fim foram apresentadas conclusões, comentários e sugestões de trabalhos futuros baseando-se no que foi visto e implementado nesse trabalho.

Mixed-signal analog-digital circuits design on the pre-diffused digital array using trapezoidal association of transistors

The mixed-signal and analog design on a pre-diffused array is a challenging task, given that the digital array is a linear matrix arrangement of minimum-length transistors. To surmount this drawback a specific discipline for designing analog circuits over such array is required. An important novel technique proposed is the use of TAT (Trapezoidal Associations of Transistors) composite transistors on the semi-custom Sea-Of-Transistors (SOT) array. The analysis and advantages of TAT arrangement are extensively analyzed and demonstrated, with simulation and measurement comparisons to equivalent single transistors. Basic analog cells were also designed as well in full-custom and TAT versions in 1.0mm and 0.5mm digital CMOS technologies. Most of the circuits were prototyped in full-custom and TAT-based on pre-diffused SOT arrays. An innovative demonstration of the TAT technique is shown with the design and implementation of a mixed-signal analog system, i. e., a fully differential 2nd order Sigma-Delta Analog-to-Digital (A/D) modulator, fabricated in both full-custom and SOT array methodologies in 0.5mm CMOS technology from MOSIS foundry. Three test-chips were designed and fabricated in 0.5mm. Two of them are IC chips containing the full-custom and SOT array versions of a 2nd-Order Sigma-Delta A/D modulator. The third IC contains a transistors-structure (TAT and single) and analog cells placed side-by-side, block components (Comparator and Folded-cascode OTA) of the Sigma-Delta modulator.

Mg/Ca ratios in planktonic foraminifera

The primary Mg/Ca ratio of foraminiferal shells is a potentially valuable paleoproxy for sea surface temperature (SST) reconstructions. However, the reliable extraction of this ratio from sedimentary calcite assumes that we can overcome artifacts related to foraminiferal ecology and partial dissolution, as well as contamination by secondary calcite and clay. The standard batch method for Mg/Ca analysis involves cracking, sonicating, and rinsing the tests to remove clay, followed by chemical cleaning, and finally acid-digestion and single-point measurement. This laborious procedure often results in substantial loss of sample (typically 30-60%). We find that even the earliest steps of this procedure can fractionate Mg from Ca, thus biasing the result toward a more variable and often anomalously low Mg/Ca ratio. Moreover, the more rigorous the cleaning, the more calcite is lost, and the more likely it becomes that any residual clay that has not been removed by physical cleaning will increase the ratio. These potentially significant sources of error can be overcome with a flow-through (FT) sequential leaching method that makes time- and labor-intensive pretreatments unnecessary. When combined with time-resolved analysis (FT-TRA) flow-through, performed with a gradually increasing and highly regulated acid strength, produces continuous records of Mg, Sr, Al, and Ca concentrations in the leachate sorted by dissolution susceptibility of the reacting material. Flow-through separates secondary calcite from less susceptible biogenic calcite and clay, and further resolves the biogenic component into primary and more resistant fractions. FT-TRA reliably separates secondary calcite (which is not representative of original life habitats) from the more resistant biogenic calcite (the desired signal) and clay (a contaminant of high Mg/Ca, which also contains Al), and further resolves the biogenic component into primary and more resistant fractions that may reflect habitat or other changes during ontogeny. We find that the most susceptible fraction of biogenic calcite in surface dwelling foraminifera gives the most accurate value for SST and therefore best represents primary calcite. Sequential dissolution curves can be used to correct the primary Mg/Ca ratio for clay, if necessary. However, the temporal separation of calcite from clay in FT-TRA is so complete that this correction is typically <=2%, even in clay-rich sediments. Unlike hands-on batch methods, that are difficult to reproduce exactly, flow-through lends itself to automation, providing precise replication of treatment for every sample. Our automated flow-through system can process 22 samples, two system blanks, and 48 mixed standards in <12 hours of unattended operation. FT-TRA thus represents a faster, cheaper, and better way to determine Mg/Ca ratios in foraminiferal calcite.

Yours 4 ever, W. Mitchell," older brother of L. J. Mitchel

2 scans - 1of2 = whole card, 2of2 = image alone