Prisons Memory Archive

Between 2006 and 2007, the Prisons Memory Archive (PMA) filmed participants, including former prisoners, prison staff, teachers, chaplains, visitors, solicitors and welfare workers back inside the Maze/Long Kesh Prison and Armagh Gaol. They shared the memory of the time spent in these prisons during the period of political violence from 1970 - 2000 in Northern Ireland, commonly known as the Troubles. Underpinning the overall methodology is co-ownership of the material, which gives participants the right to veto as well as to participate in the processes of editing and exhibiting their stories, so prioritising the value of co-authorship of their stories. The PMA adopted life-story interviewing techniques with the empty sites stimulating participants’ memory while they walked and talked their way around the empty sites. A third feature is inclusivity: the archive holds stories from across the full spectrum of the prison experience. A selection of the material, with accompanying context and links is available online www.prisonsmemoryarchive.com

Further Information:

The protocols of inclusivity, co-ownership and life-story telling make this collection significant as an initiative that engages with contemporary problems of how to negotiate narratives about a conflicted past in a society emerging out of violence. Inclusivity means that prison staff, prisoners, governors, chaplains, tutors and visitors have participated, relating their individual and collective experiences, which sit side by side on the PMA website. Co-ownership addresses the issues of ethics and sensitivity, allowing key constituencies to be involved. Life-story telling, based on oral history methodologies allows participants to be the authors of their own stories, crucial when dealing with sensitive issues from a violent past. The website hosts a selection of excerpts, e.g. the Armagh Stories page shows excerpts from 15 participants, while the Maze and Long Kesh Prison page offers interactive access to 24 participants from that prison. Using an interactive documentary structure, the site offers users opportunities to navigate their own way through the material and encourages them to hear and see the ‘other’, central to attempts at encouraging dialogue in a divided society. Further, public discussions have been held after screening of excerpts with community groups in the following locations - Belfast, Newtownabbey, Derry, Armagh, Enniskillen, London, Cork, Maynooth, Clones, and Monaghan. Extracts have been screened at international academic conferences in Valencia, Australia, Tartu, Estonia, Prague, and York. A dataset of the content, with description and links, is available for REF purposes.

On The Energy-Efficiency of Byte-Addressable Non-Volatile Memory

Non-Volatile Memory (NVM) technology holds promise to replace SRAM and DRAM at various levels of the memory hierarchy. The interest in NVM is motivated by the difficulty faced in scaling DRAM beyond 22 nm and, long-term, lower cost per bit. While offering higher density and negligible static power (leakage and refresh), NVM suffers increased latency and energy per memory access. This paper develops energy and performance models of memory systems and applies them to understand the energy-efficiency of replacing or complementing DRAM with NVM. Our analysis focusses on the application of NVM in main memory. We demonstrate that NVM such as STT-RAM and RRAM is energy-efficient for memory sizes commonly employed in servers and high-end workstations, but PCM is not. Furthermore, the model is well suited to quickly evaluate the impact of changes to the model parameters, which may be achieved through optimization of the memory architecture, and to determine the key parameters that impact system-level energy and performance.

Response time analysis of COTS-Based multicores considering the contention on the shared memory bus

The current industry trend is towards using Commercially available Off-The-Shelf (COTS) based multicores for developing real time embedded systems, as opposed to the usage of custom-made hardware. In typical implementation of such COTS-based multicores, multiple cores access the main memory via a shared bus. This often leads to contention on this shared channel, which results in an increase of the response time of the tasks. Analyzing this increased response time, considering the contention on the shared bus, is challenging on COTS-based systems mainly because bus arbitration protocols are often undocumented and the exact instants at which the shared bus is accessed by tasks are not explicitly controlled by the operating system scheduler; they are instead a result of cache misses. This paper makes three contributions towards analyzing tasks scheduled on COTS-based multicores. Firstly, we describe a method to model the memory access patterns of a task. Secondly, we apply this model to analyze the worst case response time for a set of tasks. Although the required parameters to obtain the request profile can be obtained by static analysis, we provide an alternative method to experimentally obtain them by using performance monitoring counters (PMCs). We also compare our work against an existing approach and show that our approach outperforms it by providing tighter upper-bound on the number of bus requests generated by a task.

fMRI delineation of working memory for emotional prosody in the brain: commonalities with the lexico-semantic emotion network

Decoding emotional prosody is crucial for successful social interactions, and continuous monitoring of emotional intent via prosody requires working memory. It has been proposed by Ross and others that emotional prosody cognitions in the right hemisphere are organized in an analogous fashion to propositional language functions in the left hemisphere. This study aimed to test the applicability of this model in the context of prefrontal cortex working memory functions. BOLD response data were therefore collected during performance of two emotional working memory tasks by participants undergoing fMRI. In the prosody task, participants identified the emotion conveyed in pre-recorded sentences, and working memory load was manipulated in the style of an N-back task. In the matched lexico-semantic task, participants identified the emotion conveyed by sentence content. Block-design neuroimaging data were analyzed parametrically with SPM5. At first, working memory for emotional prosody appeared to be right-lateralized in the PFC, however, further analyses revealed that it shared much bilateral prefrontal functional neuroanatomy with working memory for lexico-semantic emotion. Supplementary separate analyses of males and females suggested that these language functions were less bilateral in females, but their inclusion did not alter the direction of laterality. It is concluded that Ross et al.'s model is not applicable to prefrontal cortex working memory functions, that evidence that working memory cannot be subdivided in prefrontal cortex according to material type is increased, and that incidental working memory demands may explain the frontal lobe involvement in emotional prosody comprehension as revealed by neuroimaging studies. (c) 2007 Elsevier Inc. All rights reserved.

Short-term memory and the attentional blink: capacity versus content

When people monitor the rapid serial visual presentation (RSVP) of stimuli for two targets (T1 and T2), they often miss T2 if it falls into a time window of about half a second after T1 onset, a phenomenon known as the attentional blink (AB). We found that overall performance in an RSVP task was impaired by a concurrent short-term memory (STM) task and, furthermore, that this effect increased when STM load was higher and when its content was more task relevant. Loading visually defined stimuli and adding articulatory suppression further impaired performance on the RSVP task, but the size of the AB over time (i.e., T1-T2 lag) remained unaffected by load or content. This suggested that at least part of the performance in an RSVP task reflects interference between competing codes within STM, as interference models have held, whereas the AB proper reflects capacity limitations in the transfer to STM, as consolidation models have claimed.

Contrasting effects of changing rhythm and content on auditory distraction in immediate memory

Across five experiments, the temporal regularity and content of an irrelevant speech stream were varied and their effects on a serial recall task examined. Variations of the content, but not the rhythm, of the irrelevant speech stimuli reliably disrupted serial recall performance in all experiments. Bayesian analyses supported the null hypothesis over the hypothesis that irregular rhythms would disrupt memory to a greater extent than regular rhythms. Pooling the data in a combined analysis revealed that regular presentation of the irrelevant speech was significantly more disruptive to serial recall than irregular presentation. These results are consistent with the idea that auditory distraction is sensitive to both intra-item and inter-item relations and challenge an orienting-based account of auditory distraction.

Use of shared memory in the context of embedded multi-core processors: exploration of the technology and its limits

Modern embedded systems embrace many-core shared-memory designs. Due to constrained power and area budgets, most of them feature software-managed scratchpad memories instead of data caches to increase the data locality. It is therefore programmers’ responsibility to explicitly manage the memory transfers, and this make programming these platform cumbersome. Moreover, complex modern applications must be adequately parallelized before they can the parallel potential of the platform into actual performance. To support this, programming languages were proposed, which work at a high level of abstraction, and rely on a runtime whose cost hinders performance, especially in embedded systems, where resources and power budget are constrained. This dissertation explores the applicability of the shared-memory paradigm on modern many-core systems, focusing on the ease-of-programming. It focuses on OpenMP, the de-facto standard for shared memory programming. In a first part, the cost of algorithms for synchronization and data partitioning are analyzed, and they are adapted to modern embedded many-cores. Then, the original design of an OpenMP runtime library is presented, which supports complex forms of parallelism such as multi-level and irregular parallelism. In the second part of the thesis, the focus is on heterogeneous systems, where hardware accelerators are coupled to (many-)cores to implement key functional kernels with orders-of-magnitude of speedup and energy efficiency compared to the “pure software” version. However, three main issues rise, namely i) platform design complexity, ii) architectural scalability and iii) programmability. To tackle them, a template for a generic hardware processing unit (HWPU) is proposed, which share the memory banks with cores, and the template for a scalable architecture is shown, which integrates them through the shared-memory system. Then, a full software stack and toolchain are developed to support platform design and to let programmers exploiting the accelerators of the platform. The OpenMP frontend is extended to interact with it.