METAMATERIAL DEVICE AND USES THEREOF

The present invention relates to a logic gate, comprising a metamaterial surface enhanced Raman scattering (MetaSERS) sensor, comprising (a) alphabetical metamaterials in the form of split ring resonators operating in the wavelength range of from 560 to 2200 nm; and (b) a guanine (G) and thymine (T)-rich oligonucleotide that can, upon presence of potassium cations (K+), fold into a G-quadruplex structure, and in presence of Hg2+, form a T-Hg2+-T hairpin complex that inhibits or disrupts the G-quadruplex structure formed in presence of K+, as well as methods of operating and using such a logic gate.

Electrical characterization of electronic circuits produced by inkjet printing

Dissertação de Mestrado, Engenharia Electrónica e Telecomunicações, Faculdade de Ciências e Tecnologia, Universidade do Algarve, 2014

Performance projections and design optimization of planar double gate SOI MOSFETs for logic technology applications

In this paper, by investigating the influence of source/drain extension region engineering (also known as gate-source/drain underlap) in nanoscale planar double gate (DG) SOI MOSFETs, we offer new insights into the design of future nanoscale gate-underlap DG devices to achieve ITRS projections for high performance (HP), low standby power (LSTP) and low operating power (LOP) logic technologies. The impact of high-kappa gate dielectric, silicon film thickness, together with parameters associated with the lateral source/drain doping profile, is investigated in detail. The results show that spacer width along with lateral straggle can not only effectively control short-channel effects, thus presenting low off-current in a gate underlap device, but can also be optimized to achieve lower intrinsic delay and higher on-off current ratio (I-on/I-off). Based on the investigation of on-current (I-on), off-current (I-off), I-on/I-off, intrinsic delay (tau), energy delay product and static power dissipation, we present design guidelines to select key device parameters to achieve ITRS projections. Using nominal gate lengths for different technologies, as recommended from ITRS specification, optimally designed gate-underlap DG MOSFETs with a spacer-to-straggle (s/sigma) ratio of 2.3 for HP/LOP and 3.2 for LSTP logic technologies will meet ITRS projection. However, a relatively narrow range of lateral straggle lying between 7 to 8 nm is recommended. A sensitivity analysis of intrinsic delay, on-current and off-current to important parameters allows a comparative analysis of the various design options and shows that gate workfunction appears to be the most crucial parameter in the design of DG devices for all three technologies. The impact of back gate misalignment on I-on, I-off and tau is also investigated for optimized underlap devices.

Species differential regulation of COX2 can be described by an NFκB-dependent logic AND gate

Cyclooxygenase 2 (COX2), a key regulatory enzyme of the prostaglandin/eicosanoid pathway, is an important target for anti-inflammatory therapy. It is highly induced by pro-inflammatory cytokines in a Nuclear factor kappa B (NFκB)-dependent manner. However, the mechanisms determining the amplitude and dynamics of this important pro-inflammatory event are poorly understood. Furthermore, there is significant difference between human and mouse COX2 expression in response to the inflammatory stimulus tumor necrosis factor alpha (TNFα). Here, we report the presence of a molecular logic AND gate composed of two NFκB response elements (NREs) which controls the expression of human COX2 in a switch-like manner. Combining quantitative kinetic modeling and thermostatistical analysis followed by experimental validation in iterative cycles, we show that the human COX2 expression machinery regulated by NFκB displays features of a logic AND gate. We propose that this provides a digital, noise-filtering mechanism for a tighter control of expression in response to TNFα, such that a threshold level of NFκB activation is required before the promoter becomes active and initiates transcription. This NFκB-regulated AND gate is absent in the mouse COX2 promoter, most likely contributing to its differential graded response in promoter activity and protein expression to TNFα. Our data suggest that the NFκB-regulated AND gate acts as a novel mechanism for controlling the expression of human COX2 to TNFα, and its absence in the mouse COX2 provides the foundation for further studies on understanding species-specific differential gene regulation.

Experiences with implementing common mathematical operations using field programmable gate arrays

Many computationally intensive scientific applications involve repetitive floating point operations other than addition and multiplication which may present a significant performance bottleneck due to the relatively large latency or low throughput involved in executing such arithmetic primitives on commod- ity processors. A promising alternative is to execute such primitives on Field Programmable Gate Array (FPGA) hardware acting as an application-specific custom co-processor in a high performance reconfig- urable computing platform. The use of FPGAs can provide advantages such as fine-grain parallelism but issues relating to code development in a hardware description language and efficient data transfer to and from the FPGA chip can present significant application development challenges. In this paper, we discuss our practical experiences in developing a selection of floating point hardware designs to be implemented using FPGAs. Our designs include some basic mathemati cal library functions which can be implemented for user defined precisions suitable for novel applications requiring non-standard floating point represen- tation. We discuss the details of our designs along with results from performance and accuracy analysis tests.

Solving tri-diagonal linear systems using field programmable gate arrays

In this paper, we present the outcomes of a project on the exploration of the use of Field Programmable Gate Arrays(FPGAs) as co-processors for scientific computation. We designed a custom circuit for the pipelined solving of multiple tri-diagonal linear systems. The design is well suited for applications that require many independent tri diagonal system solves, such as finite difference methods for solving PDEs or applications utilising cubic spline interpolation. The selected solver algorithm was the Tri Diagonal Matrix Algorithm (TDMA or Thomas Algorithm). Our solver supports user specified precision thought the use of a custom floating point VHDL library supporting addition, subtraction, multiplication and division. The variable precision TDMA solver was tested for correctness in simulation mode. The TDMA pipeline was tested successfully in hardware using a simplified solver model. The details of implementation, the limitations, and future work are also discussed.

Solving tri-diagonal linear systems using field programmable gate arrays

In this paper, we present the outcomes of a project on the exploration of the use of Field Programmable Gate Arrays (FPGAs) as co-processors for scientific computation. We designed a custom circuit for the pipelined solving of multiple tri-diagonal linear systems. The design is well suited for applications that require many independent tri-diagonal system solves, such as finite difference methods for solving PDEs or applications utilising cubic spline interpolation. The selected solver algorithm was the Tri-Diagonal Matrix Algorithm (TDMA or Thomas Algorithm). Our solver supports user specified precision thought the use of a custom floating point VHDL library supporting addition, subtraction, multiplication and division. The variable precision TDMA solver was tested for correctness in simulation mode. The TDMA pipeline was tested successfully in hardware using a simplified solver model. The details of implementation, the limitations, and future work are also discussed.

An isolated MOSFET gate driver

Traditional methods of isolated MOSFET/IGBT gate drive are presented, and their pros and cons assessed. The best options are chosen to meet our objective— a small, high speed, low cost, low power isolated gate drive module. Two small ferrite bead transformers are used for isolation, one transmits power at 2.5MHz, the other sends narrow set reset pulses. On the secondary these pulses drive a transistor totem pole to ensure high current drive, and the value is held by CMOS buffers with positive feedback. An alternative design for driving logic level devices uses only an HC buffer on the secondary. Double sided SMDconstruction (primary one side, secondary on the other) yields an upright module 40x18x5mm. Propagation delaywas 20ns, and rise/fall time 15ns with a 1nF load. The design places no limits on frequency of operation or duty cycle. Power supply requirementswere 5V@20mA for operation below 100kHz, dominated by magnetising current.

Comparison of the gate drive parameter space for driving power MOSFETs using conventional and cascode configurations

Conventional voltage driven gate drive circuits utilise a resistor to control the switching speed of power MOS-FETs. The gate resistance is adjusted to provide controlled rate of change of load current and voltage. The cascode gate drive configuration has been proposed as an alternative to the conventional resistor-fed gate drive circuit. While cascode drive is broadly understood in the literature the switching characteristics of this topology are not well documented. This paper explores, through both simulation and experimentation, the gate drive parameter space of the cascode gate drive configuration and provides a comparison to the switching characteristics of conventional gate drive.

A Note on Easily Testable Realizations for Logic Functions

It is shown that at most, n + 3 tests are required to detect any single stuck-at fault in an AND gate or a single faulty EXCLUSIVE OR (EOR) gate in a Reed-Muller canonical form realization of a switching function.

Assessment of SET Logic Robustness Through Noise Margin Modeling

A compact model for noise margin (NM) of single-electron transistor (SET) logic is developed, which is a function of device capacitances and background charge (zeta). Noise margin is, then, used as a metric to evaluate the robustness of SET logic against background charge, temperature, and variation of SET gate and tunnel junction capacitances (CG and CT). It is shown that choosing alpha=CT/CG=1/3 maximizes the NM. An estimate of the maximum tolerable zeta is shown to be equal to plusmn0.03 e. Finally, the effect of mismatch in device parameters on the NM is studied through exhaustive simulations, which indicates that a isin [0.3, 0.4] provides maximum robustness. It is also observed that mismatch can have a significant impact on static power dissipation.

A low power, process invariant keeper design for high speed dynamic logic circuits

A low power keeper circuit using the concept of rate sensing has been proposed. The proposed technique reduces the amount of short circuit power dissipation in the domino gate by 70% compared to the conventional keeper technique. Also the total power-delay product is 26% lower compared to the previously reported techniques. The process tracking capability of the design enables the domino gate to achieve uniform delay across different process corners. This reduces the amount of short circuit power dissipation that occurs in the cascaded domino gates by 90%. The use of the proposed technique in the read path of a register file reduces the energy requirement by 26% as compared to the other keeper techniques. The proposed technique has been prototyped in 130nm CMOS technology.

Unified Vdd Vth Optimization Based DVFM Controller for a Logic Block

In this paper analytical expressions for optimal Vdd and Vth to minimize energy for a given speed constraint are derived. These expressions are based on the EKV model for transistors and are valid in both strong inversion and sub threshold regions. The effect of gate leakage on the optimal Vdd and Vth is analyzed. A new gradient based algorithm for controlling Vdd and Vth based on delay and power monitoring results is proposed. A Vdd-Vth controller which uses the algorithm to dynamically control the supply and threshold voltage of a representative logic block (sum of absolute difference computation of an MPEG decoder) is designed. Simulation results using 65 nm predictive technology models are given.

An Advanced Gate Driver for Insulated Gate Bipolar Transistors to Eliminate Dead-time Induced Distortions in Inverter Output

Dead-time is introduced between the gating signals to the top and bottom switches in a voltage source inverter (VSI) leg, to prevent shoot through fault due to the finite turn-off times of IGBTs. The dead-time results in a delay when the incoming device is an IGBT, resulting in error voltage pulses in the inverter output voltage. This paper presents the design, fabrication and testing of an advanced gate driver, which eliminates dead-time and consequent output distortion. Here, the gating pulses are generated such that the incoming IGBT transition is not delayed and shoot-through is also prevented. The various logic units of the driver card and fault tolerance of the driver are verified through extensive tests on different topologies such as chopper, half-bridge and full-bridge inverter, and also at different conditions of load. Experimental results demonstrate the improvement in the load current waveform quality with the proposed circuit, on account of elimination of dead-time.

Field programmable gate array based predictive control system for spacecraft rendezvous in elliptical orbits

Copyright © 2014 John Wiley & Sons, Ltd. Copyright © 2014 John Wiley & Sons, Ltd. Summary A field programmable gate array (FPGA) based model predictive controller for two phases of spacecraft rendezvous is presented. Linear time-varying prediction models are used to accommodate elliptical orbits, and a variable prediction horizon is used to facilitate finite time completion of the longer range manoeuvres, whilst a fixed and receding prediction horizon is used for fine-grained tracking at close range. The resulting constrained optimisation problems are solved using a primal-dual interior point algorithm. The majority of the computational demand is in solving a system of simultaneous linear equations at each iteration of this algorithm. To accelerate these operations, a custom circuit is implemented, using a combination of Mathworks HDL Coder and Xilinx System Generator for DSP, and used as a peripheral to a MicroBlaze soft-core processor on the FPGA, on which the remainder of the system is implemented. Certain logic that can be hard-coded for fixed sized problems is implemented to be configurable online, in order to accommodate the varying problem sizes associated with the variable prediction horizon. The system is demonstrated in closed-loop by linking the FPGA with a simulation of the spacecraft dynamics running in Simulink on a PC, using Ethernet. Timing comparisons indicate that the custom implementation is substantially faster than pure embedded software-based interior point methods running on the same MicroBlaze and could be competitive with a pure custom hardware implementation.