The use of C-V techniques to investigate instability mechanisms in M-I-S structures

In the field of flat panel displays, the current leading technology is the Active Matrix liquid Crystal Display; this uses a-Si:H based thin film transistors (TFTs) as the switching element in each pixel. However, under gate bias a-Si:H TFTs suffer from instability, as is evidenced by a shift in the gate threshold voltage. The shift in the gate threshold voltage is generally measured from the gate transfer characteristics, after subjecting the TFT to prolonged gate bias. However, a major drawback of this measurement method is that it cannot distinguish whether the shift is caused by the change in the midgap states in the a-Si:H channel or by charge trapping in the gate insulator. In view of this, we have developed a capacitance-voltage (C-V) method to measure the shift in threshold voltage. We employ Metal-Insulator-Semiconductor (MIS) structures to investigate the threshold voltage shift as they are simpler to fabricate than TFTs. We have investigated a large of number Metal/a-Si:H/Si3N4/Si+n structures using our C-V technique. From, the C-V data for the MIS structures, we have found that the relationship between the thermal energy and threshold voltage shift is similar to that reported by Wehrspohn et. al in a-Si:H TFTs (J Appl. Phys, 144, 87, 2000). The a-Si:H and Si3N4 layers were grown using the radio-frequency plasma-enhanced chemical vapour deposition technique.

Characterization of defect removal in hydrogenated and deuterated amorphous silicon thin film transistors

Thin film transistors (TFTs) utilizing an hydrogenated amorphous silicon (a-Si:H) channel layer exhibit a shift in the threshold voltage with time under the application of a gate bias voltage due to the creation of metastable defects. These defects are removed by annealing the device with zero gate bias applied. The defect removal process can be characterized by a thermalization energy which is, in turn, dependent upon an attempt-to-escape frequency for defect removal. The threshold voltage of both hydrogenated and deuterated amorphous silicon (a-Si:D) TFTs has been measured as a function of annealing time and temperature. Using a molecular dynamics simulation of hydrogen and deuterium in a silicon network in the H2 * configuration, it is shown that the experimental results are consistent with an attempt-to-escape frequency of (4.4 ± 0.3) × 1013 Hz and (5.7 ± 0.3) × 1013 Hz for a-Si:H and a-Si:D respectively which is attributed to the oscillation of the Si-H and Si-D bonds. Using this approach, it becomes possible to describe defect removal in hydrogenated and deuterated material by the thermalization energies of (1.552 ± 0.003) eV and (1.559 ± 0.003) eV respectively. This correlates with the energy per atom of the Si-H and Si-D bonds. © 2006 Elsevier B.V. All rights reserved.

Self-aligned high-resolution printed polymer transistors

A process to fabricate solution-processable thin-film transistors (TFTs) with a one-step self-aligned definition of the dimensions in all functional layers is demonstrated. The TFT-channel, semiconductor materials, and effective gate dimention of different layers are determined by a one-step imprint process and the subsequent pattern transfer without the need for multiple patterning and mask alignment. The process is compatible with fabrication of large-scale circuits. Copyright © 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

High mobility N-channel and P-channel nanocrystalline silicon thin-film transistors

We report high hole and electron mobilities in nanocrystalline silicon (nc-Si:H) top-gate staggered thin-film transistors (TFTs) fabricated by direct plasma-enhanced chemical vapor deposition (PECVD) at 260°C. The n-channel nc-Si:H TFT with n+ nc-Si:H ohmic contacts shows a field-effect electron mobility (μnFE) of 130 cm2/Vs, which increases to 150 cm2/Vs with Cr-silicide contacts, along with a field-effect hole mobility (μhFE) of 25 cm2/Vs. To the best of our knowledge, the hole and electron mobilities reported here are the highest achieved to date using direct PECVD. © 2005 IEEE.

Metastability mechanisms in thin film transistors quantitatively resolved using post-stress relaxation of threshold voltage

A new approach is presented to resolve bias-induced metastability mechanisms in hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFTs). The post stress relaxation of threshold voltage (V(T)) was employed to quantitatively distinguish between the charge trapping process in gate dielectric and defect state creation in active layer of transistor. The kinetics of the charge de-trapping from the SiN traps is analytically modeled and a Gaussian distribution of gap states is extracted for the SiN. Indeed, the relaxation in V(T) is in good agreement with the theory underlying the kinetics of charge de-trapping from gate dielectric. For the TFTs used in this work, the charge trapping in the SiN gate dielectric is shown to be the dominant metastability mechanism even at bias stress levels as low as 10 V.

One step self-aligned multilayer patterning process for the fabrication of organic complementary circuits in combination with inkjet printing

Recent development of solution processable organic semiconductors delineates the emergence of a new generation of air-stable, high performance p- and n-type materials. This makes it indeed possible for printed organic complementary circuits (CMOS) to be used in real applications. The main technical bottleneck for organic CMOS to be adopted as the next generation organic integrated circuit is how to deposit and pattern both p- and n-type semiconductor materials with high resolutions at the same time. It represents a significant technical challenge, especially if it can be done for multiple layers without mask alignment. In this paper, we propose a one-step self-aligned fabrication process which allows the deposition and high resolution patterning of functional layers for both p- and n-channel thin film transistors (TFTs) simultaneously. All the dimensional information of the device components is featured on a single imprinting stamp, and the TFT-channel geometry, electrodes with different work functions, p- and n-type semiconductors and effective gate dimensions can all be accurately defined by one-step imprinting and the subsequent pattern transfer process. As an example, we have demonstrated an organic complementary inverter fabricated by 3D imprinting in combination with inkjet printing and the measured electrical characteristics have validated the feasibility of the novel technique. © 2012 Elsevier B.V. All rights reserved.

Gated three-terminal device architecture to eliminate persistent photoconductivity in oxide semiconductor photosensor arrays

The composition of amorphous oxide semiconductors, which are well known for their optical transparency, can be tailored to enhance their absorption and induce photoconductivity for irradiation with green, and shorter wavelength light. In principle, amorphous oxide semiconductor-based thin-film photoconductors could hence be applied as photosensors. However, their photoconductivity persists for hours after illumination has been removed, which severely degrades the response time and the frame rate of oxide-based sensor arrays. We have solved the problem of persistent photoconductivity (PPC) by developing a gated amorphous oxide semiconductor photo thin-film transistor (photo-TFT) that can provide direct control over the position of the Fermi level in the active layer. Applying a short-duration (10 ns) voltage pulse to these devices induces electron accumulation and accelerates their recombination with ionized oxygen vacancy sites, which are thought to cause PPC. We have integrated these photo-TFTs in a transparent active-matrix photosensor array that can be operated at high frame rates and that has potential applications in contact-free interactive displays. © 2012 Macmillan Publishers Limited. All rights reserved.

Temperature dependent electron transport in amorphous oxide semiconductor thin film transistors

A temperature-dependent mobility model in amorphous oxide semiconductor (AOS) thin film transistors (TFTs) extracted from measurements of source-drain terminal currents at different gate voltages and temperatures is presented. At low gate voltages, trap-limited conduction prevails for a broad range of temperatures, whereas variable range hopping becomes dominant at lower temperatures. At high gate voltages and for all temperatures, percolation conduction comes into the picture. In all cases, the temperature-dependent mobility model obeys a universal power law as a function of gate voltage. © 2011 IEEE.

Transparent oxide semiconductors for advanced display applications

The article discusses the progress and issues related to transparent oxide semiconductor (TOS) TFTs for advanced display and imaging applications. Amorphous oxide semiconductors continue to spark new technological developments in transparent electronics on a multitude of non-conventional substrates. Applications range from high-frame-rate interactive displays with embedded imaging to flexible electronics, where speed and transparency are essential requirements. TOS TFTs exhibit high transparency as well as high electron mobility even when fabricated at room temperature. Compared to conventional a-Si TFT technology, TOS TFTs have higher mobility and sufficiently good uniformity over large areas, similar in many ways to LTPS TFTs. Moreover, because the amorphous oxide semiconductor has higher mobility compared to that of conventional a-Si TFT technology, this allows higher-frame-rate display operation. This would greatly benefit OLED displays in particular because of the need for lower-cost higher-mobility analog circuits at every subpixel.

How to achieve ultra high photoconductive gain for transparent oxide semiconductor image sensors

We present quantitative analysis of the ultra-high photoconductivity in amorphous oxide semiconductor (AOS) thin film transistors (TFTs), taking into account the sub-gap optical absorption in oxygen deficiency defects. We analyze the basis of photoconductivity in AOSs, explained in terms of the extended electron lifetime due to retarded recombination as a result of hole localization. Also, photoconductive gain in AOS photo-TFTs can be maximized by reducing the transit time associated with short channel lengths, making device scaling favourable for high sensitivity operation. © 2012 IEEE.

Analytical field-effect method for extraction of subgap states in thin-film transistors

We present an analytical field-effect method to extract the density of subgap states (subgap DOS) in amorphous semiconductor thin-film transistors (TFTs), using a closed-form relationship between surface potential and gate voltage. By accounting the interface states in the subthreshold characteristics, the subgap DOS is retrieved, leading to a reasonably accurate description of field-effect mobility and its gate voltage dependence. The method proposed here is very useful not only in extracting device performance but also in physically based compact TFT modeling for circuit simulation. © 2012 IEEE.

High-density remote plasma sputtering of high-dielectric-constant amorphous hafnium oxide films

Hafnium oxide (HfOx) is a high dielectric constant (k) oxide which has been identified as being suitable for use as the gate dielectric in thin film transistors (TFTs). Amorphous materials are preferred for a gate dielectric, but it has been an ongoing challenge to produce amorphous HfOx while maintaining a high dielectric constant. A technique called high target utilization sputtering (HiTUS) is demonstrated to be capable of depositing high-k amorphous HfOx thin films at room temperature. The plasma is generated in a remote chamber, allowing higher rate deposition of films with minimal ion damage. Compared to a conventional sputtering system, the HiTUS technique allows finer control of the thin film microstructure. Using a conventional reactive rf magnetron sputtering technique, monoclinic nanocrystalline HfOx thin films have been deposited at a rate of ∼1.6nmmin-1 at room temperature, with a resistivity of 1013Ωcm, a breakdown strength of 3.5MVcm-1 and a dielectric constant of ∼18.2. By comparison, using the HiTUS process, amorphous HfOx (x=2.1) thin films which appear to have a cubic-like short-range order have been deposited at a high deposition rate of ∼25nmmin-1 with a high resistivity of 1014Ωcm, a breakdown strength of 3MVcm-1 and a high dielectric constant of ∼30. Two key conditions must be satisfied in the HiTUS system for high-k HfOx to be produced. Firstly, the correct oxygen flow rate is required for a given sputtering rate from the metallic target. Secondly, there must be an absence of energetic oxygen ion bombardment to maintain an amorphous microstructure and a high flux of medium energy species emitted from the metallic sputtering target to induce a cubic-like short range order. This HfOx is very attractive as a dielectric material for large-area electronic applications on flexible substrates. A remote plasma sputtering process (high target utilization sputtering, HiTUS) has been used to deposit amorphous hafnium oxide with a very high dielectric constant (∼30). X-ray diffraction shows that this material has a microstructure in which the atoms have a cubic-like short-range order, whereas radio frequency (rf) magnetron sputtering produced a monoclinic polycrystalline microstructure. This is correlated to the difference in the energetics of remote plasma and rf magnetron sputtering processes. © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Stretching-assembled nanowires for organic-based thin film transistors

We demonstrate a stretched contact-printing technique to assemble one-dimensional nanostructures with controlled density and orientation. Over 90% nanowires are highly aligned along the primary stretching direction. Specifically, The hybrid inorganic-organic TFTs based on a parallel-aligned nanowire network and a semiconducting polymer reveal a significant positive enhancement in transistor performance and air-stability.

DC current rectification using indium-gallium zinc oxide-based selfswitching diodes

Self-switching diodes have been fabricated within a single layer of indium-gallium zinc oxide (IGZO). Current-voltage (I-V) measurements show the nanometer-scale asymmetric device gave a diode-like response. Full current rectification was achieved using very narrow channel widths of 50nm, with a turn-on voltage, Von, of 2.2V. The device did not breakdown within the -10V bias range measured. This single diode produced a current of 0.1μA at 10V and a reverse current of less than 0.1nA at -10V. Also by adjusting the channel width for these devices, Von could be altered; however, the effectiveness of the rectification also changed. © 2013 IEEE.

Fourier spectrum based extraction of an equivalent trap state density in indium gallium zinc oxide transistors

Segregating the dynamics of gate bias induced threshold voltage shift, and in particular, charge trapping in thin film transistors (TFTs) based on time constants provides insight into the different mechanisms underlying TFTs instability. In this Letter we develop a representation of the time constants and model the magnitude of charge trapped in the form of an equivalent density of created trap states. This representation is extracted from the Fourier spectrum of the dynamics of charge trapping. Using amorphous In-Ga-Zn-O TFTs as an example, the charge trapping was modeled within an energy range of ΔEt 0.3 eV and with a density of state distribution as Dt(Et-j)=Dt0exp(-ΔEt/ kT)with Dt0 = 5.02 × 1011 cm-2 eV-1. Such a model is useful for developing simulation tools for circuit design. © 2014 AIP Publishing LLC.