48 resultados para VCO
Resumo:
The paper describes a system for measuring radiation efficiency of a small antenna operating alone or in the presence of objects similar to those as in an actual service. The system applies the direct approach to determining the antenna efficiency by measuring the radiated field over the entire sphere surrounding the tested antenna. In order to overcome problems associated with the conventional measuring equipment, the antenna under test is equipped with a miniature built-in VCO signal generator and supported by a low reflectivity dielectric positioner. The positioner is of sufficient size and strength to hold a human head phantom to investigate changes in radiation characteristics when the antenna operates in the presence of a human operator.
Resumo:
I circuti di tipo charge-pump trovano vasto impiego nell'elettronica moderna in quanto offrono un metodo semplice e totalmente integrato per elevare le basse tensioni di alimentazione tipiche dei circuiti digitali e trasformarle nelle alimentazioni adatte al pilotaggio di circuti di programmazione delle memorie, al pilotaggio dei mos di potenza, alla generazione della tensione di riferimento dei VCO nei PLL e in numerose altre applicazioni. Questa tesi studia il circuito charge-pump di Dickson nel suo comportamento sia a regime stazionario sia a regime dinamico. Al fine di aumentare l'efficienza è infatti importante attivare il circuito solo all'occorrenza, prestando attenzione al transitorio di accensione. Ogni aspetto teorico viene verificato per mezzo di simulazioni su LTSpice. Si è quindi potuto constatare che un dimensionamento corretto del numero di stadi ottimizza le prestazioni sia statiche che dinamiche sotto il vincolo di una massima occupazione d'area. L'impiego dei circuiti charge-pump si prevede possa essere sempre più diffuso in futuro, visto il trend verso un maggiore livello di integrazione dei sistemi elettronici e la tendenza ad utilizzare tensioni di alimentazione sempre più basse.
Resumo:
Integrated circuit scaling has enabled a huge growth in processing capability, which necessitates a corresponding increase in inter-chip communication bandwidth. As bandwidth requirements for chip-to-chip interconnection scale, deficiencies of electrical channels become more apparent. Optical links present a viable alternative due to their low frequency-dependent loss and higher bandwidth density in the form of wavelength division multiplexing. As integrated photonics and bonding technologies are maturing, commercialization of hybrid-integrated optical links are becoming a reality. Increasing silicon integration leads to better performance in optical links but necessitates a corresponding co-design strategy in both electronics and photonics. In this light, holistic design of high-speed optical links with an in-depth understanding of photonics and state-of-the-art electronics brings their performance to unprecedented levels. This thesis presents developments in high-speed optical links by co-designing and co-integrating the primary elements of an optical link: receiver, transmitter, and clocking.
In the first part of this thesis a 3D-integrated CMOS/Silicon-photonic receiver will be presented. The electronic chip features a novel design that employs a low-bandwidth TIA front-end, double-sampling and equalization through dynamic offset modulation. Measured results show -14.9dBm of sensitivity and energy efficiency of 170fJ/b at 25Gb/s. The same receiver front-end is also used to implement source-synchronous 4-channel WDM-based parallel optical receiver. Quadrature ILO-based clocking is employed for synchronization and a novel frequency-tracking method that exploits the dynamics of IL in a quadrature ring oscillator to increase the effective locking range. An adaptive body-biasing circuit is designed to maintain the per-bit-energy consumption constant across wide data-rates. The prototype measurements indicate a record-low power consumption of 153fJ/b at 32Gb/s. The receiver sensitivity is measured to be -8.8dBm at 32Gb/s.
Next, on the optical transmitter side, three new techniques will be presented. First one is a differential ring modulator that breaks the optical bandwidth/quality factor trade-off known to limit the speed of high-Q ring modulators. This structure maintains a constant energy in the ring to avoid pattern-dependent power droop. As a first proof of concept, a prototype has been fabricated and measured up to 10Gb/s. The second technique is thermal stabilization of micro-ring resonator modulators through direct measurement of temperature using a monolithic PTAT temperature sensor. The measured temperature is used in a feedback loop to adjust the thermal tuner of the ring. A prototype is fabricated and a closed-loop feedback system is demonstrated to operate at 20Gb/s in the presence of temperature fluctuations. The third technique is a switched-capacitor based pre-emphasis technique designed to extend the inherently low bandwidth of carrier injection micro-ring modulators. A measured prototype of the optical transmitter achieves energy efficiency of 342fJ/bit at 10Gb/s and the wavelength stabilization circuit based on the monolithic PTAT sensor consumes 0.29mW.
Lastly, a first-order frequency synthesizer that is suitable for high-speed on-chip clock generation will be discussed. The proposed design features an architecture combining an LC quadrature VCO, two sample-and-holds, a PI, digital coarse-tuning, and rotational frequency detection for fine-tuning. In addition to an electrical reference clock, as an extra feature, the prototype chip is capable of receiving a low jitter optical reference clock generated by a high-repetition-rate mode-locked laser. The output clock at 8GHz has an integrated RMS jitter of 490fs, peak-to-peak periodic jitter of 2.06ps, and total RMS jitter of 680fs. The reference spurs are measured to be –64.3dB below the carrier frequency. At 8GHz the system consumes 2.49mW from a 1V supply.