Design and analysis of rate aware ad hoc 802.11 networks

802.11 WLANs are characterized by high bit error rate and frequent changes in network topology. The key feature that distinguishes WLANs from wired networks is the multi-rate transmission capability, which helps to accommodate a wide range of channel conditions. This has a significant impact on higher layers such as routing and transport levels. While many WLAN products provide rate control at the hardware level to adapt to the channel conditions, some chipsets like Atheros do not have support for automatic rate control. We first present a design and implementation of an FER-based automatic rate control state machine, which utilizes the statistics available at the device driver to find the optimal rate. The results show that the proposed rate switching mechanism adapts quite fast to the channel conditions. The hop count metric used by current routing protocols has proven itself for single rate networks. But it fails to take into account other important factors in a multi-rate network environment. We propose transmission time as a better path quality metric to guide routing decisions. It incorporates the effects of contention for the channel, the air time to send the data and the asymmetry of links. In this paper, we present a new design for a multi-rate mechanism as well as a new routing metric that is responsive to the rate. We address the issues involved in using transmission time as a metric and presents a comparison of the performance of different metrics for dynamic routing.

Multi power port converter for hybrid electric vehicles using multi phase bidirectional fly-back topology

For hybrid electric vehicles the batteries and the drive dc-link may be at different voltages. The batteries are at low voltage to obtain higher volumetric efficiencies and the dc-link is at higher voltage to have higher efficiency on the motor side. Therefore a power interface between the batteries and the drive's dc-link is essential. This power interface should handle power flow from battery to motor, motor to battery, external genset to battery and grid to battery. This paper proposes a multi power port topology which is capable of handling multiple power sources and still maintains simplicity and features like obtaining any gain, wide load variations, lower output current ripple and capability of parallel battery energy due to the modular structure. The development and testing of a bi-directional fly-back DC-DC converter for hybrid electric vehicle is described in this paper. Simple hysteresis voltage control is used for DC link voltage regulation. The experimental results are presented to show the working of the proposed converter.

A Simple Five-Level Inverter Topology for Induction Motor Drive Using Conventional Two-Level Inverters and Flying Capacitor Technique

This paper proposes a new five-level inverter topology for open-end winding induction motor (IM) drive. The popular existing circuit configurations for five-level inverter include the NPC inverter and flying capacitor topologies. Compared to the NPC inverter, the proposed topology eliminates eighteen clamping diodes having different voltage ratings in the present circuit. Moreover it requires only one capacitor bank per phase, whereas flying capacitor schemes for five level topologies require six capacitor banks per phase. The proposed topology is realized by feeding the phase winding of an open-end induction motor with two-level inverters in series with flying capacitors. The flying capacitor voltages are balanced using the switching state redundancy for full modulation range. The proposed inverter scheme is capable of producing two-level to five-level pulse width modulated voltage across the phase winding depending on the modulation range. Additionally, in case of any switch failure in the flying capacitor connection, the proposed inverter topology can be operated as a three-level inverter for full modulation range. The proposed scheme is experimentally verified on a four pole, 5hp induction motor drive.

Using Water as a Design Element in Crystal Engineering. Host-Guest Compounds of Hydrated 3,5-Dihydroxybenzoic Acid

Thirteen host guest compounds of 3,5-dihydroxybenzoic acid (DHBA) have been structurally characterized. Water molecules occupy the peripheries of a hexagonal void, created with DHBA molecules, and act as ``hooks'' to connect the guest molecules with the host-framework via hydrogen bonding. The ``water hook'' is an OH group acting as a donor. Consequently, the guest molecules were chosen so that they contain good hydrogen bond acceptor functionalities. A number of multicomponent hydrates were isolated with stoichiometries (DHBA)(x)(H2O). (guest),. Of these, compounds with the following as guests were obtained as crystals that were good enough for single crystal work: ethyl acetate (EtOAc), diethyl oxalate, dimethyl oxalate, di(n-propyl) oxalate, diethyl malonate, diethyl succinate, chloroacetonitrile, N,N-dimethyl formamide (DMF), acetone, dimethyl sulfoxide (DMSO), 1-propanol, and 2-butanol. From 2-butanol, a hemihydrate, (DHBA)(2)(H2O), was also obtained concomitantly. Further to guest stabilization, water acts as a good mediator of effective crystal packing and also determines the topology of the host framework. En the present series of compounds, the role of water is wide ranging, and it is not easy to classify it specifically as a host or as a guest.

A Hybrid Multilevel Inverter Topology for an Open-End Winding Induction-Motor Drive Using Two-Level Inverters in Series With a Capacitor-Fed H-Bridge Cell

In this paper, a new five-level inverter topology for open-end winding induction-motor (IM) drive is proposed. The open-end winding IM is fed from one end with a two-level inverter in series with a capacitor-fed H-bridge cell, while the other end is connected to a conventional two-level inverter. The combined inverter system produces voltage space-vector locations identical to that of a conventional five-level inverter. A total of 2744 space-vector combinations are distributed over 61 space-vector locations in the proposed scheme. With such a high number of switching state redundancies, it is possible to balance the H-bridge capacitor voltages under all operating conditions including overmodulation region. In addition to that, the proposed topology eliminates 18 clamping diodes having different voltage ratings compared with the neutral point clamped inverter. On the other hand, it requires only one capacitor bank per phase, whereas the flying-capacitor scheme for a five-level topology requires more than one capacitor bank per phase. The proposed inverter topology can be operated as a three-level inverter for full modulation range, in case of any switch failure in the capacitor-fed H-bridge cell. This will increase the reliability of the system. The proposed scheme is experimentally verified on a four-pole 5-hp IM drive.

A Deterministic Optimization Approach to Protein Sequence Design Using Continuous Models

Determining the sequence of amino acid residues in a heteropolymer chain of a protein with a given conformation is a discrete combinatorial problem that is not generally amenable for gradient-based continuous optimization algorithms. In this paper we present a new approach to this problem using continuous models. In this modeling, continuous "state functions" are proposed to designate the type of each residue in the chain. Such a continuous model helps define a continuous sequence space in which a chosen criterion is optimized to find the most appropriate sequence. Searching a continuous sequence space using a deterministic optimization algorithm makes it possible to find the optimal sequences with much less computation than many other approaches. The computational efficiency of this method is further improved by combining it with a graph spectral method, which explicitly takes into account the topology of the desired conformation and also helps make the combined method more robust. The continuous modeling used here appears to have additional advantages in mimicking the folding pathways and in creating the energy landscapes that help find sequences with high stability and kinetic accessibility. To illustrate the new approach, a widely used simplifying assumption is made by considering only two types of residues: hydrophobic (H) and polar (P). Self-avoiding compact lattice models are used to validate the method with known results in the literature and data that can be practically obtained by exhaustive enumeration on a desktop computer. We also present examples of sequence design for the HP models of some real proteins, which are solved in less than five minutes on a single-processor desktop computer Some open issues and future extensions are noted.

Analysis, Design, Modeling, and Implementation of an Active Clamp HF Link Converter

This paper deals with the system oriented analysis, design, modeling, and implementation of active clamp HF link three phase converter. The main advantage of the topology is reduced size, weight, and cost of the isolation transformer. However, violation of basic power conversion rules due to presence of the leakage inductance in the HF transformer causes over voltage stresses across the cycloconverter devices. It makes use of the snubber circuit necessary in such topologies. The conventional RCD snubbers are dissipative in nature and hence inefficient. The efficiency of the system is greatly improved by using regenerative snubber or active clamp circuit. It consists of an active switching device with an anti-parallel diode and one capacitor to absorb the energy stored in the leakage inductance of the isolation transformer and to regenerate the same without affecting circuit performance. The turn on instant and duration of the active device are selected such that it requires simple commutation requirements. The time domain expressions for circuit dynamics, design criteria of the snubber capacitor with two conflicting constrains (over voltage stress across the devices and the resonating current duration), the simulation results based on generalized circuit model and the experimental results based on laboratory prototype are presented.

Synthesis of workspaces of planar manipulators with arbitrary topology using shape representation and simulated annealing

This paper presents a general methodology for the synthesis of the external boundary of the workspaces of a planar manipulator with arbitrary topology. Both the desired workspace and the manipulator workspaces are identified by their boundaries and are treated as simple closed polygons. The paper introduces the concept of best match configuration and shows that the corresponding transformation can be obtained by using the concept of shape normalization available in image processing literature. Introduction of the concept of shape in workspace synthesis allows highly accurate synthesis with fewer numbers of design variables. This paper uses a new global property based vector representation for the shape of the workspaces which is computationally efficient because six out of the seven elements of this vector are obtained as a by-product of the shape normalization procedure. The synthesis of workspaces is formulated as an optimization problem where the distance between the shape vector of the desired workspace and that of the workspace of the manipulator at hand are minimized by changing the dimensional parameters of the manipulator. In view of the irregular nature of the error manifold, the statistical optimization procedure of simulated annealing has been used. A number of worked-out examples illustrate the generality and efficiency of the present method. (C) 1998 Elsevier Science Ltd. All rights reserved.

A Seven-Level Inverter Topology for Induction Motor Drive Using Two-Level Inverters and Floating Capacitor Fed H-Bridges

A multilevel inverter topology for seven-level space vector generation is proposed in this paper. In this topology, the seven-level structure is realized using two conventional two-level inverters and six capacitor-fed H-bridge cells. It needs only two isolated dc-voltage sources of voltage rating V(dc)/2 where V(dc) is the dc voltage magnitude required by the conventional neutral point clamped (NPC) seven-level topology. The proposed topology is capable of maintaining the H-bridge capacitor voltages at the required level of V(dc)/6 under all operating conditions, covering the entire linear modulation and overmodulation regions, by making use of the switching state redundancies. In the event of any switch failure in H-bridges, this inverter can operate in three-level mode, a feature that enhances the reliability of the drive system. The two-level inverters, which operate at a higher voltage level of V(dc)/2, switch less compared to the H-bridges, which operate at a lower voltage level of V(dc)/6, resulting in switching loss reduction. The experimental verification of the proposed topology is carried out for the entire modulation range, under steady state as well as transient conditions.

Topology Optimization of Micromachined Structures with the Manufacturing Constraints of KOH Etching of (110) Silicon

The focus of this paper is on designing useful compliant micro-mechanisms of high-aspect-ratio which can be microfabricated by the cost-effective wet etching of (110) orientation silicon (Si) wafers. Wet etching of (110) Si imposes constraints on the geometry of the realized mechanisms because it allows only etch-through in the form of slots parallel to the wafer's flat with a certain minimum length. In this paper, we incorporate this constraint in the topology optimization and obtain compliant designs that meet the specifications on the desired motion for given input forces. Using this design technique and wet etching, we show that we can realize high-aspect-ratio compliant micro-mechanisms. For a (110) Si wafer of 250 µm thickness, the minimum length of the etch opening to get a slot is found to be 866 µm. The minimum achievable width of the slot is limited by the resolution of the lithography process and this can be a very small value. This is studied by conducting trials with different mask layouts on a (110) Si wafer. These constraints are taken care of by using a suitable design parameterization rather than by imposing the constraints explicitly. Topology optimization, as is well known, gives designs using only the essential design specifications. In this work, we show that our technique also gives manufacturable mechanism designs along with lithography mask layouts. Some designs obtained are transferred to lithography masks and mechanisms are fabricated on (110) Si wafers.

A Comparative Study of the Formulations for Topology Optimization of Compliant Mechanisms

The topology optimization problem for the synthesis of compliant mechanisms has been formulated in many different ways in the last 15 years, but there is not yet a definitive formulation that is universally accepted. Furthermore, there are two unresolved issues in this problem. In this paper, we present a comparative study of five distinctly different formulations that are reported in the literature. Three benchmark examples are solved with these formulations using the same input and output specifications and the same numerical optimization algorithm. A total of 35 different synthesis examples are implemented. The examples are limited to desired instantaneous output direction for prescribed input force direction. Hence, this study is limited to linear elastic modeling with small deformations. Two design parameterizations, namely, the frame element based ground structure and the density approach using continuum elements, are used. The obtained designs are evaluated with all other objective functions and are compared with each other. The checkerboard patterns, point flexures, the ability to converge from an unbiased uniform initial guess, and the computation time are analyzed. Some observations are noted based on the extensive implementation done in this study. Complete details of the benchmark problems and the results are included. The computer codes related to this study are made available on the internet for ready access.

Cojoined Irregular Topology and Routing Table Generation for Network-on-Chip

Scalable Networks on Chips (NoCs) are needed to match the ever-increasing communication demands of large-scale Multi-Processor Systems-on-chip (MPSoCs) for multi media communication applications. The heterogeneous nature of application specific on-chip cores along with the specific communication requirements among the cores calls for the design of application-specific NoCs for improved performance in terms of communication energy, latency, and throughput. In this work, we propose a methodology for the design of customized irregular networks-on-chip. The proposed method exploits a priori knowledge of the applications communication characteristic to generate an optimized network topology and corresponding routing tables.

Symmetry in Scalar Field Topology

Study of symmetric or repeating patterns in scalar fields is important in scientific data analysis because it gives deep insights into the properties of the underlying phenomenon. Though geometric symmetry has been well studied within areas like shape processing, identifying symmetry in scalar fields has remained largely unexplored due to the high computational cost of the associated algorithms. We propose a computationally efficient algorithm for detecting symmetric patterns in a scalar field distribution by analysing the topology of level sets of the scalar field. Our algorithm computes the contour tree of a given scalar field and identifies subtrees that are similar. We define a robust similarity measure for comparing subtrees of the contour tree and use it to group similar subtrees together. Regions of the domain corresponding to subtrees that belong to a common group are extracted and reported to be symmetric. Identifying symmetry in scalar fields finds applications in visualization, data exploration, and feature detection. We describe two applications in detail: symmetry-aware transfer function design and symmetry-aware isosurface extraction.

Topology Optimization of Micromachined Structures with Surface Micromachining Manufacturing Constraints

Topology optimization methods have been shown to have extensive application in the design of microsystems. However, their utility in practical situations is restricted to predominantly planar configurations due to the limitations of most microfabrication techniques in realizing structures with arbitrary topologies in the direction perpendicular to the substrate. This study addresses the problem of synthesizing optimal topologies in the out-of-plane direction while obeying the constraints imposed by surface micromachining. A new formulation that achieves this by defining a design space that implicitly obeys the manufacturing constraints with a continuous design parameterization is presented in this paper. This is in contrast to including manufacturing cost in the objective function or constraints. The resulting solutions of the new formulation obtained with gradient-based optimization directly provide the photolithographic mask layouts. Two examples that illustrate the approach for the case of stiff structures are included.

Topology Optimization of Electrostatically Actuated Micromechanical Structures with Accurate Electrostatic Modeling of the Interpolated Material Model

In this paper, we present a novel formulation for performing topology optimization of electrostatically actuated constrained elastic structures. We propose a new electrostatic-elastic formulation that uses the leaky capacitor model and material interpolation to define the material state at every point of a given design domain continuously between conductor and void states. The new formulation accurately captures the physical behavior when the material in between a conductor and a void is present during the iterative process of topology optimization. The method then uses the optimality criteria method to solve the optimization problem by iteratively pushing the state of the domain towards that of a conductor or a void in the appropriate regions. We present examples to illustrate the ability of the method in creating the stiffest structure under electrostatic force for different boundary conditions.