Photonic switching architectures with logic cells

Possible switching architectures, with Optically Programmable Logic Cells - OPLCs - will be reported in this paper. These basic units, previously employed by us for some other applications mainly in optical computing, will be employed as main elements to switch optical communications signals. The main aspect to be considered is that because the nternal components of these cells have nonlinear behaviors, namely either pure bistable or SEED-like properties, several are the possibilities to be obtained. Moreover, because their properties are dependent, under certain condition, of the signal wavelength, they are apt to be employed in WDM systems and the final result will depend on the orresponding optical signal frequency. We will give special emphasis to the case where self-routing is achieved, namely to structures of the Batcher or Banyan type. In these cases, as it will be shown, there is the possibility to route any packet input to a certain direction according to its first bits. The number of possible outputs gives the number of bits needed to route signals. An advantage of this configuration is that a very versatile behavior may be allowed. The main one is the possibility to obtain configurations with different kinds of behavior, namely, Strictly Nonblocking, Wide-Sense Nonblocking or Rearrangeably Nonblocking as well as to eliminate switching conflicts at a certain intermediate stages.

Logic cells as basic structures to add/drop WDM information signals

Nowadays, in order to take advantage of fiber optic bandwidth, any optical communications system tends to be WDM. The way to extract a channel, characterized by a wavelength, from the optical fiber is to filter the specific wavelength. This gives the systems a low degree of freedom due to the fact of the static character of most of the employed devices. In this paper we will present a different way to extract channels from an optical fiber with WDM transmission. The employed method is based on an Optically Programmable Logic Cells (OPLC) previously published by us, for other applications as a chaotic generator or as basic element for optical computing. In this paper we will describe the configuration of the OPLC to be employed as a dropping device. It acts as a filter because it will extract the data carried by a concrete wavelength. It does depend, internally, on the wavelength. We will show how the intensity of the signal is able to select the chosen information from the line. It will be also demonstrated that a new idea of redundant information it is the way of selecting the concrete wavelength. As a matter of fact this idea is apparently the only way to use the OPLC as a dropping device. Moreover, based on these concepts, a similar way to route signals to different routes is reported. The basis is the use of photonic switching configurations, namely Batcher or Bayan structures, where the unit switching cells are the above indicated OPLCs.

A self-timed multipurpose delay sensor for field programmable gate arrays (FPGAs)

This paper presents a novel self-timed multi-purpose sensor especially conceived for Field Programmable Gate Arrays (FPGAs). The aim of the sensor is to measure performance variations during the life-cycle of the device, such as process variability, critical path timing and temperature variations. The proposed topology, through the use of both combinational and sequential FPGA elements, amplifies the time of a signal traversing a delay chain to produce a pulse whose width is the sensor’s measurement. The sensor is fully self-timed, avoiding the need for clock distribution networks and eliminating the limitations imposed by the system clock. One single off- or on-chip time-to-digital converter is able to perform digitization of several sensors in a single operation. These features allow for a simplified approach for designers wanting to intertwine a multi-purpose sensor network with their application logic. Employed as a temperature sensor, it has been measured to have an error of ±0.67 °C, over the range of 20–100 °C, employing 20 logic elements with a 2-point calibration.

An Algorithm for Optimal Bipartite PLA Folding

This paper presents some results of PLA area optimizing by means of its column and row folding. A more restricted type of PLA simple folding is considered. It is introduced by Egan and Liu and called as bipartite folding. An efficient approach is presented which allows finding an optimal bipartite folding without exhaustive computational efforts.

Protótipo de rastreador solar de um eixo baseado em microcontrolador

The increase in the efficiency of photo-voltaic systems has been the object of various studies the past few years. One possible way to increase the power extracted by a photovoltaic panel is the solar tracking, performing its movement in order to follow the sun’s path. One way to activate the tracking system is using an electric induction motor, which should have sufficient torque and low speed, ensuring tracking accuracy. With the use of voltage source inverters and logic devices that generate the appropriate switching is possible to obtain the torque and speed required for the system to operate. This paper proposes the implementation of a angular position sensor and a driver to be applied in solar tracker built at a Power Electronics and Renewable Energies Laboratory, located in UFRN. The speed variation of the motor is performed via a voltage source inverter whose PWM command to actuate their keys will be implemented in an FPGA (Field Programmable Gate Array) device and a TM4C microcontroller. A platform test with an AC induction machine of 1.5 CV was assembled for the comparative testing. The angular position sensor of the panel is implemented in a ATMega328 microcontroller coupled to an accelerometer, commanded by an Arduino prototyping board. The solar position is also calculated by the microcontroller from the geographic coordinates of the site where it was placed, and the local time and date obtained from an RTC (Real-Time Clock) device. A prototype of a solar tracker polar axis moved by a DC motor was assembled to certify the operation of the sensor and to check the tracking efficiency.

The Design and Implementation of a SD Card File System

SD card (Secure Digital Memory Card) is widely used in portable storage medium. Currently, latest researches on SD card, are mainly SD card controller based on FPGA (Field Programmable Gate Array). Most of them are relying on API interface (Application Programming Interface), AHB bus (Advanced High performance Bus), etc. They are dedicated to the realization of ultra high speed communication between SD card and upper systems. Studies about SD card controller, really play a vital role in the field of high speed cameras and other sub-areas of expertise. This design of FPGA-based file systems and SD2.0 IP (Intellectual Property core) does not only exhibit a nice transmission rate, but also achieve the systematic management of files, while retaining a strong portability and practicality. The file system design and implementation on a SD card covers the main three IP innovation points. First, the combination and integration of file system and SD card controller, makes the overall system highly integrated and practical. The popular SD2.0 protocol is implemented for communication channels. Pure digital logic design based on VHDL (Very-High-Speed Integrated Circuit Hardware Description Language), integrates the SD card controller in hardware layer and the FAT32 file system for the entire system. Secondly, the document management system mechanism makes document processing more convenient and easy. Especially for small files in batch processing, it can ease the pressure of upper system to frequently access and process them, thereby enhancing the overall efficiency of systems. Finally, digital design ensures the superior performance. For transmission security, CRC (Cyclic Redundancy Check) algorithm is for data transmission protection. Design of each module is platform-independent of macro cells, and keeps a better portability. Custom integrated instructions and interfaces may facilitate easily to use. Finally, the actual test went through multi-platform method, Xilinx and Altera FPGA developing platforms. The timing simulation and debugging of each module was covered. Finally, Test results show that the designed FPGA-based file system IP on SD card can support SD card, TF card and Micro SD with 2.0 protocols, and the successful implementation of systematic management for stored files, and supports SD bus mode. Data read and write rates in Kingston class10 card is approximately 24.27MB/s and 16.94MB/s.

Minimalist Hardware Architectures for Agent Tracking and Guidance

The philosophy of minimalism in robotics promotes gaining an understanding of sensing and computational requirements for solving a task. This minimalist approach lies in contrast to the common practice of first taking an existing sensory motor system, and only afterwards determining how to apply the robotic system to the task. While it may seem convenient to simply apply existing hardware systems to the task at hand, this design philosophy often proves to be wasteful in terms of energy consumption and cost, along with unnecessary complexity and decreased reliability. While impressive in terms of their versatility, complex robots such as the PR2 (which cost hundreds of thousands of dollars) are impractical for many common applications. Instead, if a specific task is required, sensing and computational requirements can be determined specific to that task, and a clever hardware implementation can be built to accomplish the task. Since this minimalist hardware would be designed around accomplishing the specified task, significant reductions in hardware complexity can be obtained. This can lead to huge advantages in battery life, cost, and reliability. Even if cost is of no concern, battery life is often a limiting factor in many applications. Thus, a minimalist hardware system is critical in achieving the system requirements. In this thesis, we will discuss an implementation of a counting, tracking, and actuation system as it relates to ergodic bodies to illustrate a minimalist design methodology.

Design and Development of Network Monitoring Strategies in P4-enabled Programmable Switches

Network monitoring is of paramount importance for effective network management: it allows to constantly observe the network’s behavior to ensure it is working as intended and can trigger both automated and manual remediation procedures in case of failures and anomalies. The concept of SDN decouples the control logic from legacy network infrastructure to perform centralized control on multiple switches in the network, and in this context, the responsibility of switches is only to forward packets according to the flow control instructions provided by controller. However, as current SDN switches only expose simple per-port and per-flow counters, the controller has to do almost all the processing to determine the network state, which causes significant communication overhead and excessive latency for monitoring purposes. The absence of programmability in the data plane of SDN prompted the advent of programmable switches, which allow developers to customize the data-plane pipeline and implement novel programs operating directly in the switches. This means that we can offload certain monitoring tasks to programmable data planes, to perform fine-grained monitoring even at very high packet processing speeds. Given the central importance of network monitoring exploiting programmable data planes, the goal of this thesis is to enable a wide range of monitoring tasks in programmable switches, with a specific focus on the ones equipped with programmable ASICs. Indeed, most network monitoring solutions available in literature do not take computational and memory constraints of programmable switches into due account, preventing, de facto, their successful implementation in commodity switches. This claims that network monitoring tasks can be executed in programmable switches. Our evaluations show that the contributions in this thesis could be used by network administrators as well as network security engineers, to better understand the network status depending on different monitoring metrics, and thus prevent network infrastructure and service outages.

Array-CGH testing in spontaneous abortions with normal karyotypes

In about 50% of first trimester spontaneous abortion the cause remains undetermined after standard cytogenetic investigation. We evaluated the usefulness of array-CGH in diagnosing chromosome abnormalities in products of conception from first trimester spontaneous abortions. Cell culture was carried out in short- and long-term cultures of 54 specimens and cytogenetic analysis was successful in 49 of them. Cytogenetic abnormalities (numerical and structural) were detected in 22 (44.89%) specimens. Subsequent, array-CGH based on large insert clones spaced at ~1 Mb intervals over the whole genome was used in 17 cases with normal G-banding karyotype. This revealed chromosome aneuplodies in three additional cases, giving a final total of 51% cases in which an abnormal karyotype was detected. In keeping with other recently published works, this study shows that array-CGH detects abnormalities in a further ~10% of spontaneous abortion specimens considered to be normal using standard cytogenetic methods. As such, array-CGH technique may present a suitable complementary test to cytogenetic analysis in cases with a normal karyotype.

Design and fabrication of microcavity-array superhydrophobic surfaces

We have modeled, fabricated, and characterized superhydrophobic surfaces with a morphology formed of periodic microstructures which are cavities. This surface morphology is the inverse of that generally reported in the literature when the surface is formed of pillars or protrusions, and has the advantage that when immersed in water the confined air inside the cavities tends to expel the invading water. This differs from the case of a surface morphology formed of pillars or protrusions, for which water can penetrate irreversibly among the microstructures, necessitating complete drying of the surface in order to again recover its superhydrophobic character. We have developed a theoretical model that allows calculation of the microcavity dimensions needed to obtain superhydrophobic surfaces composed of patterns of such microcavities, and that provides estimates of the advancing and receding contact angle as a function of microcavity parameters. The model predicts that the cavity aspect ratio (depth-to-diameter ratio) can be much less than unity, indicating that the microcavities do not need to be deep in order to obtain a surface with enhanced superhydrophobic character. Specific microcavity patterns have been fabricated in polydimethylsiloxane and characterized by scanning electron microscopy, atomic force microscopy, and contact angle measurements. The measured advancing and receding contact angles are in good agreement with the predictions of the model. (C) 2010 American Institute of Physics. [doi:10.1063/1.3466979]

Universal resistance capacitance crossover in current-voltage characteristics for unshunted array of overdamped Nb-AlOx-Nb Josephson junctions

We report on some unusual behavior of the measured current-voltage characteristics (CVC) in artificially prepared two-dimensional unshunted array of overdamped Nb-AlO(x)-Nb Josephson junctions. The obtained nonlinear CVC are found to exhibit a pronounced (and practically temperature independent) crossover at some current I(cr) = (1/2 beta(C)-1)I(C) from a resistance R dominated state with V(R)=R root I(2)-I(C)(2) below I(cr) to a capacitance C dominated state with V(C) = root(h) over bar /4eC root I-I(C) above I(cr). The origin of the observed behavior is discussed within a single-plaquette approximation assuming the conventional resistively shunted junction model with a finite capacitance and the Ambegaokar-Baratoff relation for the critical current of the single junction. (C) 2010 American Institute of Physics. [doi: 10.1063/1.3407566]

Programmable diagnostic devices made from paper and tape

This paper describes three-dimensional microfluidic paper-based analytical devices (3-D mu PADs) that can be programmed (postfabrication) by the user to generate multiple patterns of flow through them. These devices are programmed by pressing single-use 'on' buttons, using a stylus or a ballpoint pen. Pressing a button closes a small space (gap) between two vertically aligned microfluidic channels, and allows fluids to wick from one channel to the other. These devices are simple to fabricate, and are made entirely out of paper and double-sided adhesive tape. Programmable devices expand the capabilities of mu PADs and provide a simple method for controlling the movement of fluids in paper-based channels. They are the conceptual equivalent of field-programmable gate arrays (FPGAs) widely used in electronics.

LEACHATE TREATMENT PROCESS AT A MUNICIPAL STABILIZED LANDFILL BY CATALYTIC OZONATION: AN EXPLORATORY STUDY FROM TAGUCHI ORTHOGONAL ARRAY

Catalytic ozonation has been recognized in the scientific community as an efficient technique, reaching elevated rates of recalcitrant organic material mineralization, even at the presence of scavenger species of hydroxyl free radicals. This study presents the most significant factors involving the leachate treatment stabilized by the municipal landfill of the city of Guaratingueta, State of Sao Paulo, Brazil, by using a catalytic ozonation activated by metallic ions Fe(3+), Zn(2+), Mn(2+), Ni(2+) and Cr(3+). The Taguchi L(16) orthogonal array and its associated statistical methods were also used in this study. Among the researched ions, the most notable catalysis was obtained with ferric ion, statistically significant in the reduction of COD with a confidence level of 99.5%.

A classification methodology for the risk of weed infestation using fuzzy logic

Despite modern weed control practices, weeds continue to be a threat to agricultural production. Considering the variability of weeds, a classification methodology for the risk of infestation in agricultural zones using fuzzy logic is proposed. The inputs for the classification are attributes extracted from estimated maps for weed seed production and weed coverage using kriging and map analysis and from the percentage of surface infested by grass weeds, in order to account for the presence of weed species with a high rate of development and proliferation. The output for the classification predicts the risk of infestation of regions of the field for the next crop. The risk classification methodology described in this paper integrates analysis techniques which may help to reduce costs and improve weed control practices. Results for the risk classification of the infestation in a maize crop field are presented. To illustrate the effectiveness of the proposed system, the risk of infestation over the entire field is checked against the yield loss map estimated by kriging and also with the average yield loss estimated from a hyperbolic model.

Information Filtering and Array Algorithms for Discrete-Time Markovian Jump Linear Systems

This technical note develops information filter and array algorithms for a linear minimum mean square error estimator of discrete-time Markovian jump linear systems. A numerical example for a two-mode Markovian jump linear system, to show the advantage of using array algorithms to filter this class of systems, is provided.