A simplified method for determining the high frequency induction motor equivalent electrical circuit parameters to be used in EMI effect

The aim of this paper is to present a simple method for determining the high frequency parameters of a three-phase induction motor to be used in studies involving variable speed drives with PWM three-phase inverters, in which it is necessary to check the effects caused to the motor by the electromagnetic interference, (EMI) in the differential mode, as well as in the common mode. The motor parameters determination is generally performed in adequate laboratories using accurate instruments, such as very expensive RLC bridges. The method proposed here consists in the identification of the motor equivalent electrical circuit parameters in rated frequency and in high frequency through characteristic tests in the laboratory, together with the use of characteristic equations and curves, shown in the references to be mentioned for determining the motor high frequency parasite capacitances and also through system simulations using dedicated software, like Pspice, determining the characteristic waveforms involved in the differential and common mode phenomena, comparing and validating the procedure through published papers [01].

Inversor CS Boost monofásico em aplicações com fontes renováveis

This paper presents a new methodology for the operation and control of a single-phase current-source (CS) Boost Inverter, considering that the conventional current-source inverter (CSI) has a right-half-plane (RHP) zero in its control-to-output transfer function, and this RHP zero causes the known non-minimum-phase effects. In this context, a special design with low boost inductance and a multi-loop control is developed in order to assure stable and very fast dynamics. Furthermore, the Inverter presents output voltage with very low total harmonic distortion (THD), reduced components and high power density. Therefore, this paper presents the inverter operation, the proposed control technique, and main simulation and experimental results in order to demonstrate the feasibility of the proposal. © 2010 IEEE.

Uma nova metodologia de projeto e controle para o inversor Boost (CSI) monofásico, para o aproveitamento de fontes alternativas e renováveis de energia elétrica

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Análise experimental de erros de medição de energia elétrica ativa em medidores eletromagnéticos tipo indução, sujeitos a distorções harmônicas de correntes e tensões, em sistemas equilibrados e desequilibrados

Pós-graduação em Engenharia Elétrica - FEIS

Tap-Off Power From the Overhead Shield Wires of an HV Transmission Line

In recent years, there was an increase of ancillary service loads, such as signaling systems, inspection robots, surveillance cameras, and other monitoring devices distributed along high-voltage transmission lines which require low-power dc voltage supplies. This paper investigates the use of the induced voltage in the shield wires of an overhead 525 kV transmission line as a primary power source. Since phase current variations throughout the day affect the induced voltage in the overhead ground wire, a step-down dc-dc converter is used after rectification of the ac voltage to provide a regulated dc output voltage. The initial encouraging results obtained indicate that this form of power supply can be a feasible and cost-effective alternative for feeding small ancillary service loads. The simulation results are validated by field measurements as well as the installation of a 200 W voltage stabilization system prototype.

A "Free-Lunch" tour of the Jovian System

An ED-tether mission to Jupiter is presented. A bare tether carrying cathodic devices at both ends but no power supply, and using no propellant, could move 'freely' among Jupiter's 4 great moons. The tour scheme would have current naturally driven throughout by the motional electric field, the Lorentz force switching direction with current around a 'drag' radius of 160,00 kms, where the speed of the jovian ionosphere equals the speed of a spacecraft in circular orbit. With plasma density and magnetic field decreasing rapidly with distance from Jupiter, drag/thrust would only be operated in the inner plasmasphere, current being near shut off conveniently in orbit by disconnecting cathodes or plugging in a very large resistance; the tether could serve as its own power supply by plugging in an electric load where convenient, with just some reduction in thrust or drag. The periapsis of the spacecraft in a heliocentric transfer orbit from Earth would lie inside the drag sphere; with tether deployed and current on around periapsis, magnetic drag allows Jupiter to capture the spacecraft into an elliptic orbit of high eccentricity. Current would be on at succesive perijove passes and off elsewhere, reducing the eccentricity by lowering the apoapsis progressively to allow visits of the giant moons. In a second phase, current is on around apoapsis outside the drag sphere, rising the periapsis until the full orbit lies outside that sphere. In a third phase, current is on at periapsis, increasing the eccentricity until a last push makes the orbit hyperbolic to escape Jupiter. Dynamical issues such as low gravity-gradient at Jupiter and tether orientation in elliptic orbits of high eccentricity are discussed.

Wide bandwidth envelope trackers with reduced switching frequency for RF power amplifier

El requerimiento de proveer alta frecuencia de datos en los modernos sistema de comunicación inalámbricos resulta en complejas señales moduladas de radio-frequencia (RF) con un gran ancho de banda y alto ratio pico-promedio (PAPR). Para garantizar la linealidad del comportamiento, los amplificadores lineales de potencia comunes funcionan típicamente entre 4 y 10 dB de back-o_ desde la máxima potencia de salida, ocasionando una baja eficiencia del sistema. La eliminación y restauración de la evolvente (EER) y el seguimiento de la evolvente (ET) son dos prometedoras técnicas para resolver el problema de la eficiencia. Tanto en EER como en ET, es complicado diseñar un amplificador de potencia que sea eficiente para señales de RF de alto ancho de banda y alto PAPR. Una propuesta común para los amplificadores de potencia es incluir un convertidor de potencia de muy alta eficiencia operando a frecuencias más altas que el ancho de banda de la señal RF. En este caso, la potencia perdida del convertidor ocasionado por la alta frecuencia desaconseja su práctica cuando el ancho de banda es muy alto. La solución a este problema es el enfoque de esta disertación que presenta dos arquitecturas de amplificador evolvente: convertidor híbrido-serie con una técnica de evolvente lenta y un convertidor multinivel basado en un convertidor reductor multifase con control de tiempo mínimo. En la primera arquitectura, una topología híbrida está compuesta de una convertidor reductor conmutado y un regulador lineal en serie que trabajan juntos para ajustar la tensión de salida para seguir a la evolvente con precisión. Un algoritmo de generación de una evolvente lenta crea una forma de onda con una pendiente limitada que es menor que la pendiente máxima de la evolvente original. La salida del convertidor reductor sigue esa forma de onda en vez de la evolvente original usando una menor frecuencia de conmutación, porque la forma de onda no sólo tiene una pendiente reducida sino también un menor ancho de banda. De esta forma, el regulador lineal se usa para filtrar la forma de onda tiene una pérdida de potencia adicional. Dependiendo de cuánto se puede reducir la pendiente de la evolvente para producir la forma de onda, existe un trade-off entre la pérdida de potencia del convertidor reductor relacionada con la frecuencia de conmutación y el regulador lineal. El punto óptimo referido a la menor pérdida de potencia total del amplificador de evolvente es capaz de identificarse con la ayuda de modelo preciso de pérdidas que es una combinación de modelos comportamentales y analíticos de pérdidas. Además, se analiza el efecto en la respuesta del filtro de salida del convertidor reductor. Un filtro de dampeo paralelo extra es necesario para eliminar la oscilación resonante del filtro de salida porque el convertidor reductor opera en lazo abierto. La segunda arquitectura es un amplificador de evolvente de seguimiento de tensión multinivel. Al contrario que los convertidores que usan multi-fuentes, un convertidor reductor multifase se emplea para generar la tensión multinivel. En régimen permanente, el convertidor reductor opera en puntos del ciclo de trabajo con cancelación completa del rizado. El número de niveles de tensión es igual al número de fases de acuerdo a las características del entrelazamiento del convertidor reductor. En la transición, un control de tiempo mínimo (MTC) para convertidores multifase es novedosamente propuesto y desarrollado para cambiar la tensión de salida del convertidor reductor entre diferentes niveles. A diferencia de controles convencionales de tiempo mínimo para convertidores multifase con inductancia equivalente, el propuesto MTC considera el rizado de corriente por cada fase basado en un desfase fijo que resulta en diferentes esquemas de control entre las fases. La ventaja de este control es que todas las corrientes vuelven a su fase en régimen permanente después de la transición para que la siguiente transición pueda empezar muy pronto, lo que es muy favorable para la aplicación de seguimiento de tensión multinivel. Además, el control es independiente de la carga y no es afectado por corrientes de fase desbalanceadas. Al igual que en la primera arquitectura, hay una etapa lineal con la misma función, conectada en serie con el convertidor reductor multifase. Dado que tanto el régimen permanente como el estado de transición del convertidor no están fuertemente relacionados con la frecuencia de conmutación, la frecuencia de conmutación puede ser reducida para el alto ancho de banda de la evolvente, la cual es la principal consideración de esta arquitectura. La optimización de la segunda arquitectura para más alto anchos de banda de la evolvente es presentada incluyendo el diseño del filtro de salida, la frecuencia de conmutación y el número de fases. El área de diseño del filtro está restringido por la transición rápida y el mínimo pulso del hardware. La rápida transición necesita un filtro pequeño pero la limitación del pulso mínimo del hardware lleva el diseño en el sentido contrario. La frecuencia de conmutación del convertidor afecta principalmente a la limitación del mínimo pulso y a las pérdidas de potencia. Con una menor frecuencia de conmutación, el ancho de pulso en la transición es más pequeño. El número de fases relativo a la aplicación específica puede ser optimizado en términos de la eficiencia global. Otro aspecto de la optimización es mejorar la estrategia de control. La transición permite seguir algunas partes de la evolvente que son más rápidas de lo que el hardware puede soportar al precio de complejidad. El nuevo método de sincronización de la transición incrementa la frecuencia de la transición, permitiendo que la tensión multinivel esté más cerca de la evolvente. Ambas estrategias permiten que el convertidor pueda seguir una evolvente con un ancho de banda más alto que la limitación de la etapa de potencia. El modelo de pérdidas del amplificador de evolvente se ha detallado y validado mediante medidas. El mecanismo de pérdidas de potencia del convertidor reductor tiene que incluir las transiciones en tiempo real, lo cual es diferente del clásico modelos de pérdidas de un convertidor reductor síncrono. Este modelo estima la eficiencia del sistema y juega un papel muy importante en el proceso de optimización. Finalmente, la segunda arquitectura del amplificador de evolvente se integra con el amplificador de clase F. La medida del sistema EER prueba el ahorro de energía con el amplificador de evolvente propuesto sin perjudicar la linealidad del sistema. ABSTRACT The requirement of delivering high data rates in modern wireless communication systems results in complex modulated RF signals with wide bandwidth and high peak-to-average ratio (PAPR). In order to guarantee the linearity performance, the conventional linear power amplifiers typically work at 4 to 10 dB back-off from the maximum output power, leading to low system efficiency. The envelope elimination and restoration (EER) and envelope tracking (ET) are two promising techniques to overcome the efficiency problem. In both EER and ET, it is challenging to design efficient envelope amplifier for wide bandwidth and high PAPR RF signals. An usual approach for envelope amplifier includes a high-efficiency switching power converter operating at a frequency higher than the RF signal's bandwidth. In this case, the power loss of converter caused by high switching operation becomes unbearable for system efficiency when signal bandwidth is very wide. The solution of this problem is the focus of this dissertation that presents two architectures of envelope amplifier: a hybrid series converter with slow-envelope technique and a multilevel converter based on a multiphase buck converter with the minimum time control. In the first architecture, a hybrid topology is composed of a switched buck converter and a linear regulator in series that work together to adjust the output voltage to track the envelope with accuracy. A slow envelope generation algorithm yields a waveform with limited slew rate that is lower than the maximum slew rate of the original envelope. The buck converter's output follows this waveform instead of the original envelope using lower switching frequency, because the waveform has not only reduced slew rate but also reduced bandwidth. In this way, the linear regulator used to filter the waveform has additional power loss. Depending on how much reduction of the slew rate of envelope in order to obtain that waveform, there is a trade-off between the power loss of buck converter related to the switching frequency and the power loss of linear regulator. The optimal point referring to the lowest total power loss of this envelope amplifier is identified with the help of a precise power loss model that is a combination of behavioral and analytic loss model. In addition, the output filter's effect on the response is analyzed. An extra parallel damping filter is needed to eliminate the resonant oscillation of output filter L and C, because the buck converter operates in open loop. The second architecture is a multilevel voltage tracking envelope amplifier. Unlike the converters using multi-sources, a multiphase buck converter is employed to generate the multilevel voltage. In the steady state, the buck converter operates at complete ripple cancellation points of duty cycle. The number of the voltage levels is equal to the number of phases according the characteristics of interleaved buck converter. In the transition, a minimum time control (MTC) for multiphase converter is originally proposed and developed for changing the output voltage of buck converter between different levels. As opposed to conventional minimum time control for multiphase converter with equivalent inductance, the proposed MTC considers the current ripple of each phase based on the fixed phase shift resulting in different control schemes among the phases. The advantage of this control is that all the phase current return to the steady state after the transition so that the next transition can be triggered very soon, which is very favorable for the application of multilevel voltage tracking. Besides, the control is independent on the load condition and not affected by the unbalance of phase current. Like the first architecture, there is also a linear stage with the same function, connected in series with the multiphase buck converter. Since both steady state and transition state of the converter are not strongly related to the switching frequency, it can be reduced for wide bandwidth envelope which is the main consideration of this architecture. The optimization of the second architecture for wider bandwidth envelope is presented including the output filter design, switching frequency and the number of phases. The filter design area is restrained by fast transition and the minimum pulse of hardware. The fast transition needs small filter but the minimum pulse of hardware limitation pushes the filter in opposite way. The converter switching frequency mainly affects the minimum pulse limitation and the power loss. With lower switching frequency, the pulse width in the transition is smaller. The number of phases related to specific application can be optimized in terms of overall efficiency. Another aspect of optimization is improving control strategy. Transition shift allows tracking some parts of envelope that are faster than the hardware can support at the price of complexity. The new transition synchronization method increases the frequency of transition, allowing the multilevel voltage to be closer to the envelope. Both control strategies push the converter to track wider bandwidth envelope than the limitation of power stage. The power loss model of envelope amplifier is detailed and validated by measurements. The power loss mechanism of buck converter has to include the transitions in real time operation, which is different from classical power loss model of synchronous buck converter. This model estimates the system efficiency and play a very important role in optimization process. Finally, the second envelope amplifier architecture is integrated with a Class F amplifier. EER system measurement proves the power saving with the proposed envelope amplifier without disrupting the linearity performance.

RGS proteins reconstitute the rapid gating kinetics of Gβγ-activated inwardly rectifying K+ channels

G protein-gated inward rectifier K+ (GIRK) channels mediate hyperpolarizing postsynaptic potentials in the nervous system and in the heart during activation of Gα(i/o)-coupled receptors. In neurons and cardiac atrial cells the time course for receptor-mediated GIRK current deactivation is 20–40 times faster than that observed in heterologous systems expressing cloned receptors and GIRK channels, suggesting that an additional component(s) is required to confer the rapid kinetic properties of the native transduction pathway. We report here that heterologous expression of “regulators of G protein signaling” (RGS proteins), along with cloned G protein-coupled receptors and GIRK channels, reconstitutes the temporal properties of the native receptor → GIRK signal transduction pathway. GIRK current waveforms evoked by agonist activation of muscarinic m2 receptors or serotonin 1A receptors were dramatically accelerated by coexpression of either RGS1, RGS3, or RGS4, but not RGS2. For the brain-expressed RGS4 isoform, neither the current amplitude nor the steady-state agonist dose-response relationship was significantly affected by RGS expression, although the agonist-independent “basal” GIRK current was suppressed by ≈40%. Because GIRK activation and deactivation kinetics are the limiting rates for the onset and termination of “slow” postsynaptic inhibitory currents in neurons and atrial cells, RGS proteins may play crucial roles in the timing of information transfer within the brain and to peripheral tissues.

Central-tapped node linked modular fault-tolerance topology for SRM applications

Electric vehicles (EVs) and hybrid electric vehicles (HEVs) can reduce greenhouse gas emissions while switched reluctance motor (SRM) is one of the promising motor for such applications. This paper presents a novel SRM fault-diagnosis and fault-tolerance operation solution. Based on the traditional asymmetric half-bridge topology for the SRM driving, the central tapped winding of the SRM in modular half-bridge configuration are introduced to provide fault-diagnosis and fault-tolerance functions, which are set idle in normal conditions. The fault diagnosis can be achieved by detecting the characteristic of the excitation and demagnetization currents. An SRM fault-tolerance operation strategy is also realized by the proposed topology, which compensates for the missing phase torque under the open-circuit fault, and reduces the unbalanced phase current under the short-circuit fault due to the uncontrolled faulty phase. Furthermore, the current sensor placement strategy is also discussed to give two placement methods for low cost or modular structure. Simulation results in MATLAB/Simulink and experiments on a 750-W SRM validate the effectiveness of the proposed strategy, which may have significant implications and improve the reliability of EVs/HEVs.

New integrated multilevel converter for switched reluctance motor drives in plug-in hybrid electric vehicles with flexible energy conversion

This paper presents an integrated multilevel converter of switched reluctance motors (SRMs) fed by a modular front-end circuit for plug-in hybrid electric vehicle (PHEV) applications. Several operating modes can be achieved by changing the on-off states of the switches in the front-end circuit. In generator driving mode, the battery bank is employed to elevate the phase voltage for fast excitation and demagnetization. In battery driving mode, the converter is reconfigured as a four-level converter, and the capacitor is used as an additional charge capacitor to produce multilevel voltage outputs, which enhances the torque capability. The operating modes of the proposed drive are explained and the phase current and voltage are analyzed in details. The battery charging is naturally achieved by the demagnetization current in motoring mode and by the regenerative current in braking mode. Moreover, the battery can be charged by the external AC source or generator through the proposed converter when the vehicle is in standstill condition. The SRM-based PHEV can operate at different speeds by coordinating the power flow between the generator and battery. Simulation in MATLAB/Simulink and experiments on a three-phase 12/8 SRM confirm the effectiveness of the proposed converter topology.

Contribuições para estratégia de controle aplicada à geração fotovoltaica interconectada à rede elétrica

Generation systems, using renewable sources, are becoming increasingly popular due to the need for increased use of electricity. Currently, renewables sources have a role to cooperate with conventional generation, due to the system limitation in delivering the required power, the need for reduction of unwanted effects from sources that use fossil fuels (pollution) and the difficulty of building new transmission and/or distribution lines. This cooperation takes place through distributed generation. Therefore, this work proposes a control strategy for the interconnection of a PV (Photovoltaic) system generation distributed with a three-phase power grid through a connection filter the type LCL. The compensation of power quality at point of common coupling (PCC) is performed ensuring that the mains supply or consume only active power and that his currents have low distorcion. Unlike traditional techniques which require schemes for harmonic detection, the technique performs the harmonic compensation without the use of this schemes, controlling the output currents of the system in an indirect way. So that there is effective control of the DC (Direct Current) bus voltage is used the robust controller mode dual DSMPI (Dual-Sliding Mode-Proportional Integral), that behaves as a sliding mode controller SM-PI (Sliding Mode-Proportional Integral) during the transition and like a conventional PI (Proportional Integral) in the steady-state. For control of current is used to repetitive control strategy, which are used double sequence controllers (DSC) tuned to the fundamental component, the fifth and seventh harmonic. The output phase current are aligned with the phase angle of the utility voltage vector obtained from the use of a SRF-PLL (Synchronous Reference Frame Phase-Locked-Loop). In order to obtain the maximum power from the PV array is used a MPPT (Maximum Power Point Tracking) algorithm without the need for adding sensors. Experimental results are presented to demonstrate the effectiveness of the proposed control system.

Power Quality Evaluation of a Photovoltaic System on an Electric Grid

This paper focuses on tests of photovoltaic systems in order to address two case studies with silicon monocrystalline and silicon polycrystalline panels, respectively. The first case is an identification of the three parameters of the single-diode equivalent circuit for modelling photovoltaic systems with conclusion about the inevitably age degradation. A comparison between experimental observed and computed I-V and V-P characteristics curves is carried out at standard test conditions. The second case is an experimental observation on a photovoltaic system connected to an electric grid in what regards the quality of the energy injected into the grid. A measuring of the harmonic content in the voltage and in the current waveforms at the terminals of the photovoltaic system is carried out in order to conclude about the conformity with the Standard EN 50160 and the IEEE 519-1992, respectively.