MPI-based parallel synchronous vector evaluated particle swarm optimization for multi-objective design optimization of composite structures

This paper presents a decentralized/peer-to-peer architecture-based parallel version of the vector evaluated particle swarm optimization (VEPSO) algorithm for multi-objective design optimization of laminated composite plates using message passing interface (MPI). The design optimization of laminated composite plates being a combinatorially explosive constrained non-linear optimization problem (CNOP), with many design variables and a vast solution space, warrants the use of non-parametric and heuristic optimization algorithms like PSO. Optimization requires minimizing both the weight and cost of these composite plates, simultaneously, which renders the problem multi-objective. Hence VEPSO, a multi-objective variant of the PSO algorithm, is used. Despite the use of such a heuristic, the application problem, being computationally intensive, suffers from long execution times due to sequential computation. Hence, a parallel version of the PSO algorithm for the problem has been developed to run on several nodes of an IBM P720 cluster. The proposed parallel algorithm, using MPI's collective communication directives, establishes a peer-to-peer relationship between the constituent parallel processes, deviating from the more common master-slave approach, in achieving reduction of computation time by factor of up to 10. Finally we show the effectiveness of the proposed parallel algorithm by comparing it with a serial implementation of VEPSO and a parallel implementation of the vector evaluated genetic algorithm (VEGA) for the same design problem. (c) 2012 Elsevier Ltd. All rights reserved.

An efficient design of serial and parallel memory using Quantum dot cellular automata

Quantum cellular automata (QCA) is a new technology in the nanometer scale and has been considered as one of the alternative to CMOS technology. In this paper, we describe the design and layout of a serial memory and parallel memory, showing the layout of individual memory cells. Assuming that we can fabricate cells which are separated by 10nm, memory capacities of over 1.6 Gbit/cm2 can be achieved. Simulations on the proposed memories were carried out using QCADesigner, a layout and simulation tool for QCA. During the design, we have tried to reduce the number of cells as well as to reduce the area which is found to be 86.16sq mm and 0.12 nm2 area with the QCA based memory cell. We have also achieved an increase in efficiency by 40%.These circuits are the building block of nano processors and provide us to understand the nano devices of the future.

Parallel twin-body trawl for shrimps, its design and efficiency

Comparative studies with a new 17 m parallel twin-body trawl and a 17 m bulged belly trawl conducted off Cochin during 1974-77 are reported. The parallel twin body trawl showed an increase of 28% in catch over that of bulged belly with a break up of 39.9% and 23.1 % for prawns and fishes respectively. The increase in catch is attributed to the extra wide mouth opening (26.6 %) of the parallel twin-body trawl. Parallel twin-body trawl had 8.96% lesser resistance which resulted in lower utilization of horse power.

Superconducting fault current limiter design using parallel-connected YBCO thin films

Superconducting Fault Current Limiters (SFCLs) are able to reduce fault currents to an acceptable value, reducing potential mechanical and thermal damage to power system apparatus and allowing more flexibility in power system design and operation. The device can also help avoid replacing circuit breakers whose capacity has been exceeded. Due to limitations in current YBCO thin film manufacturing processes, it is not easy to obtain one large thin film that satisfies the specifications for high voltage and large current applications. The combination of standardized thin films has merit to reduce costs and maintain device quality, and it is necessary to connect these thin films in different series and parallel configurations in order to meet these specifications. In this paper, the design of a resistive type SFCL using parallel-connected YBCO thin films is discussed, including the role of a parallel resistor and the influence of individual thin film characteristics, based on both theory and experimental results. © 2009 IEEE.

Parallel coordinates in computational engineering design

Modern Engineering Design involves the deployment of many computational tools. Re- search on challenging real-world design problems is focused on developing improvements for the engineering design process through the integration and application of advanced com- putational search/optimization and analysis tools. Successful application of these methods generates vast quantities of data on potential optimum designs. To gain maximum value from the optimization process, designers need to visualise and interpret this information leading to better understanding of the complex and multimodal relations between param- eters, objectives and decision-making of multiple and strongly conflicting criteria. Initial work by the authors has identified that the Parallel Coordinates interactive visualisation method has considerable potential in this regard. This methodology involves significant levels of user-interaction, making the engineering designer central to the process, rather than the passive recipient of a deluge of pre-formatted information. In the present work we have applied and demonstrated this methodology in two differ- ent aerodynamic turbomachinery design cases; a detailed 3D shape design for compressor blades, and a preliminary mean-line design for the whole compressor core. The first case comprises 26 design parameters for the parameterisation of the blade geometry, and we analysed the data produced from a three-objective optimization study, thus describing a design space with 29 dimensions. The latter case comprises 45 design parameters and two objective functions, hence developing a design space with 47 dimensions. In both cases the dimensionality can be managed quite easily in Parallel Coordinates space, and most importantly, we are able to identify interesting and crucial aspects of the relationships between the design parameters and optimum level of the objective functions under con- sideration. These findings guide the human designer to find answers to questions that could not even be addressed before. In this way, understanding the design leads to more intelligent decision-making and design space exploration. © 2012 AIAA.

Design and Evaluation of the Hamal Parallel Computer

Parallel shared-memory machines with hundreds or thousands of processor-memory nodes have been built; in the future we will see machines with millions or even billions of nodes. Associated with such large systems is a new set of design challenges. Many problems must be addressed by an architecture in order for it to be successful; of these, we focus on three in particular. First, a scalable memory system is required. Second, the network messaging protocol must be fault-tolerant. Third, the overheads of thread creation, thread management and synchronization must be extremely low. This thesis presents the complete system design for Hamal, a shared-memory architecture which addresses these concerns and is directly scalable to one million nodes. Virtual memory and distributed objects are implemented in a manner that requires neither inter-node synchronization nor the storage of globally coherent translations at each node. We develop a lightweight fault-tolerant messaging protocol that guarantees message delivery and idempotence across a discarding network. A number of hardware mechanisms provide efficient support for massive multithreading and fine-grained synchronization. Experiments are conducted in simulation, using a trace-driven network simulator to investigate the messaging protocol and a cycle-accurate simulator to evaluate the Hamal architecture. We determine implementation parameters for the messaging protocol which optimize performance. A discarding network is easier to design and can be clocked at a higher rate, and we find that with this protocol its performance can approach that of a non-discarding network. Our simulations of Hamal demonstrate the effectiveness of its thread management and synchronization primitives. In particular, we find register-based synchronization to be an extremely efficient mechanism which can be used to implement a software barrier with a latency of only 523 cycles on a 512 node machine.

Design of parallel algorithms for fractal video compression

The intrinsic independent features of the optimal codebook cubes searching process in fractal video compression systems are examined and exploited. The design of a suitable parallel algorithm reflecting the concept is presented. The Message Passing Interface (MPI) is chosen to be the communication tool for the implementation of the parallel algorithm on distributed memory parallel computers. Experimental results show that the parallel algorithm is able to reduce the compression time and achieve a high speed-up without changing the compression ratio and the quality of the decompressed image. A scalability test was also performed, and the results show that this parallel algorithm is scalable.

Kinematic Design of a 6-DOF Parallel Manipulator with Decoupled Translation and Rotation

A new three-limb, six-degree-of-freedom (DOF) parallel manipulator (PM), termed a selectively actuated PM (SA-PM), is proposed. The end-effector of the manipulator can produce 3-DOF spherical motion, 3-DOF translation, 3-DOF hybrid motion, or complete 6-DOF spatial motion, depending on the types of the actuation (rotary or linear) chosen for the actuators. The manipulator architecture completely decouples translation and rotation of the end-effector for individual control. The structure synthesis of SA-PM is achieved using the line geometry. Singularity analysis shows that the SA-PM is an isotropic translation PM when all the actuators are in linear mode. Because of the decoupled motion structure, a decomposition method is applied for both the displacement analysis and dimension optimization. With the index of maximal workspace satisfying given global conditioning requirements, the geometrical parameters are optimized. As a result, the translational workspace is a cube, and the orientation workspace is nearly unlimited.

Design criteria for a barrier-based gas-liquid flow distributor for parallel microchannels

This paper presents criteria for the design of a flow distributor for even distribution of gas and liquid flows over parallel microchannels. The design criteria are illustrated for the case of a nitrogen-water Taylor flow (1

Design and test of a bit parallel 2nd order IIR filter structure

Test procedures for a pipelined bit-parallel IIR filter chip which maximally exploit its regularity are described. It is shown that small modifications to the basic architecture result in significant reductions in the number of test patterns required to test such chips. The methods used allow 100% fault coverage to be achieved using less than 1000 test vectors for a chip which has 12 bit data and coefficients.