Operand Isolation Circuits with Reduced Overhead for Low Power Data-Path Design

Dynamic power dissipation due to redundant switching is an important metric in data-path design. This paper focuses on the use of ingenious operand isolation circuits for low power design. Operand isolation attempts to reduce switching by clamping or latching the output of a first level of combinational circuit. This paper presents a novel method using power supply switching wherein both PMOS and NMOS stacks of a circuit are connected to the same power supply. Thus, the output gets clamped or latched to the power supply value with minimal leakage. The proposed circuits make use of only two transistors to clamp the entire Multiple Input Multiple Output (MIMO) block. Also, the latch-based designs have higher drive strength in comparison to the existing methods. Simulation results have shown considerable area reduction in comparison to the existing techniques without increasing timing overhead.

Gamma oscillations in the midbrain spatial attention network: linking circuits to function

Gamma-band (25-140 Hz) oscillations are ubiquitous in mammalian forebrain structures involved in sensory processing, attention, learning and memory. The optic tectum (01) is the central structure in a midbrain network that participates critically in controlling spatial attention. In this review, we summarize recent advances in characterizing a neural circuit in this midbrain network that generates large amplitude, space-specific, gamma oscillations in the avian OT, both in vivo and in vitro. We describe key physiological and pharmacological mechanisms that produce and regulate the structure of these oscillations. The extensive similarities between midbrain gamma oscillations in birds and those in the neocortex and hippocampus of mammals, offer important insights into the functional significance of a midbrain gamma oscillatory code.

Switch-level timing verification for CMOS circuits. A semianalytic approach

The paper describes a semianalytic slope delay model for CMOS switch-level timing verification. It is characterised by classification of the effects of the input slope, internal size and load capacitance of a logic gate on delay time, and then the use of a series of carefully chosen analytic functions to estimate delay times under different circumstances. In the field of VLSI analysis, this model achieves improvements in speed and accuracy compared with conventional approaches to transistor-level and switch-level simulation.

Développement des méthodes de stabilisation pour la conception des circuits hyperfréquences : application à l'optimisation d'un amplificateur de puissance spatial

209 p. : graf.