Real time fault injection using a modified debugging infrastructure

Dependability is a critical factor in computer systems, requiring high quality validation & verification procedures in the development stage. At the same time, digital devices are getting smaller and access to their internal signals and registers is increasingly complex, requiring innovative debugging methodologies. To address this issue, most recent microprocessors include an on-chip debug (OCD) infrastructure to facilitate common debugging operations. This paper proposes an enhanced OCD infrastructure with the objective of supporting the verification of fault-tolerant mechanisms through fault injection campaigns. This upgraded on-chip debug and fault injection (OCD-FI) infrastructure provides an efficient fault injection mechanism with improved capabilities and dynamic behavior. Preliminary results show that this solution provides flexibility in terms of fault triggering and allows high speed real-time fault injection in memory elements

From design-for-test to design-for-debug-and-test: analysis of requirements and limitations for 1149.1

The increasing complexity of VLSI circuits and the reduced accessibility of modern packaging and mounting technologies restrict the usefulness of conventional in-circuit debugging tools, such as in-circuit emulators for microprocessors and microcontrollers. However, this same trend enables the development of more complex products, which in turn require more powerful debugging tools. These conflicting demands could be met if the standard scan test infrastructures now common in most complex components were able to match the debugging requirements of design verification and prototype validation. This paper analyses the main debug requirements in the design of microprocessor-based applications and the feasibility of their implementation using the mandatory, optional and additional operating modes of the standard IEEE 1149.1 test infrastructure.

Real-time fault injection using enhanced on-chip debug infrastructures

The rapid increase in the use of microprocessor-based systems in critical areas, where failures imply risks to human lives, to the environment or to expensive equipment, significantly increased the need for dependable systems, able to detect, tolerate and eventually correct faults. The verification and validation of such systems is frequently performed via fault injection, using various forms and techniques. However, as electronic devices get smaller and more complex, controllability and observability issues, and sometimes real time constraints, make it harder to apply most conventional fault injection techniques. This paper proposes a fault injection environment and a scalable methodology to assist the execution of real-time fault injection campaigns, providing enhanced performance and capabilities. Our proposed solutions are based on the use of common and customized on-chip debug (OCD) mechanisms, present in many modern electronic devices, with the main objective of enabling the insertion of faults in microprocessor memory elements with minimum delay and intrusiveness. Different configurations were implemented starting from basic Components Off-The-Shelf (COTS) microprocessors, equipped with real-time OCD infrastructures, to improved solutions based on modified interfaces, and dedicated OCD circuitry that enhance fault injection capabilities and performance. All methodologies and configurations were evaluated and compared concerning performance gain and silicon overhead.

A modified debugging infrastructure to assist real time fault injection campaigns

Fault injection is frequently used for the verification and validation of the fault tolerant features of microprocessors. This paper proposes the modification of a common on-chip debugging (OCD) infrastructure to add fault injection capabilities and improve performance. The proposed solution imposes a very low logic overhead and provides a flexible and efficient mechanism for the execution of fault injection campaigns, being applicable to different target system architectures.

Some Studies and New Results on Multi Microprocessor Applications

One of the fastest expanding areas of computer exploitation is in embedded systems, whose prime function is not that of computing, but which nevertheless require information processing in order to carry out their prime function. Advances in hardware technology have made multi microprocessor systems a viable alternative to uniprocessor systems in many embedded application areas. This thesis reports the results of investigations carried out on multi microprocessors oriented towards embedded applications, with a view to enhancing throughput and reliability. An ideal controller for multiprocessor operation is developed which would smoothen sharing of routines and enable more powerful and efficient code I data interchange. Results of performance evaluation are appended.A typical application scenario is presented, which calls for classifying tasks based on characteristic features that were identified. The different classes are introduced along with a partitioned storage scheme. Theoretical analysis is also given. A review of schemes available for reducing disc access time is carried out and a new scheme presented. This is found to speed up data base transactions in embedded systems. The significance of software maintenance and adaptation in such applications is highlighted. A novel scheme of prov1d1ng a maintenance folio to system firmware is presented, alongwith experimental results. Processing reliability can be enhanced if facility exists to check if a particular instruction in a stream is appropriate. Likelihood of occurrence of a particular instruction would be more prudent if number of instructions in the set is less. A new organisation is derived to form the basement for further work. Some early results that would help steer the course of the work are presented.

Design and synthesis of efficient mac architectures for high speed decimal processor

Most of the commercial and financial data are stored in decimal fonn. Recently, support for decimal arithmetic has received increased attention due to the growing importance in financial analysis, banking, tax calculation, currency conversion, insurance, telephone billing and accounting. Performing decimal arithmetic with systems that do not support decimal computations may give a result with representation error, conversion error, and/or rounding error. In this world of precision, such errors are no more tolerable. The errors can be eliminated and better accuracy can be achieved if decimal computations are done using Decimal Floating Point (DFP) units. But the floating-point arithmetic units in today's general-purpose microprocessors are based on the binary number system, and the decimal computations are done using binary arithmetic. Only few common decimal numbers can be exactly represented in Binary Floating Point (BF P). ln many; cases, the law requires that results generated from financial calculations performed on a computer should exactly match with manual calculations. Currently many applications involving fractional decimal data perform decimal computations either in software or with a combination of software and hardware. The performance can be dramatically improved by complete hardware DFP units and this leads to the design of processors that include DF P hardware.VLSI implementations using same modular building blocks can decrease system design and manufacturing cost. A multiplexer realization is a natural choice from the viewpoint of cost and speed.This thesis focuses on the design and synthesis of efficient decimal MAC (Multiply ACeumulate) architecture for high speed decimal processors based on IEEE Standard for Floating-point Arithmetic (IEEE 754-2008). The research goal is to design and synthesize deeimal'MAC architectures to achieve higher performance.Efficient design methods and architectures are developed for a high performance DFP MAC unit as part of this research.

Message Integrity in the World Wide Web: Use of Nested Hash Function and a Fast Stream Cipher

The focus of this work is to provide authentication and confidentiality of messages in a swift and cost effective manner to suit the fast growing Internet applications. A nested hash function with lower computational and storage demands is designed with a view to providing authentication as also to encrypt the message as well as the hash code using a fast stream cipher MAJE4 with a variable key size of 128-bit or 256-bit for achieving confidentiality. Both nested Hash function and MAJE4 stream cipher algorithm use primitive computational operators commonly found in microprocessors; this makes the method simple and fast to implement both in hardware and software. Since the memory requirement is less, it can be used for handheld devices for security purposes.

Microscale thermal engineering of electronic systems

The electronics industry is encountering thermal challenges and opportunities with lengthscales comparable to or much less than one micrometer. Examples include nanoscale phonon hotspots in transistors and the increasing temperature rise in onchip interconnects. Millimeter-scale hotspots on microprocessors, resulting from varying rates of power consumption, are being addressed using two-phase microchannel heat sinks. Nanoscale thermal data storage technology has received much attention recently. This paper provides an overview of these topics with a focus on related research at Stanford University.

SBR technology for wastewater treatment: suitable operational conditions for a nutrient removal

Actualment, la legislació ambiental ha esdevingut més restrictiva pel que fa a la descàrrega d'aigües residuals amb nutrients, especialment en les anomenades àrees sensibles o zones vulnerables. Arran d'aquest fet, s'ha estimulat el coneixement, desenvolupament i millora dels processos d'eliminació de nutrients. El Reactor Discontinu Seqüencial (RDS) o Sequencing Batch Reactor (SBR) en anglès, és un sistema de tractament de fangs actius que opera mitjançant un procediment d'omplerta-buidat. En aquest tipus de reactors, l'aigua residual és addicionada en un sol reactor que treballa per càrregues repetint un cicle (seqüència) al llarg del temps. Una de les característiques dels SBR és que totes les diferents operacions (omplerta, reacció, sedimentació i buidat) es donen en un mateix reactor. La tecnologia SBR no és nova d'ara. El fet, és que va aparèixer abans que els sistema de tractament continu de fangs actius. El precursor dels SBR va ser un sistema d'omplerta-buidat que operava en discontinu. Entre els anys 1914 i 1920, varen sorgir certes dificultats moltes d'elles a nivell d'operació (vàlvules, canvis el cabal d'un reactor a un altre, elevat temps d'atenció per l'operari...) per aquests reactors. Però no va ser fins a finals de la dècada dels '50 principis del '60, amb el desenvolupament de nous equipaments i noves tecnologies, quan va tornar a ressorgir l'interès pels SBRs. Importants millores en el camp del subministrament d'aire (vàlvules motoritzades o d'acció pneumàtica) i en el de control (sondes de nivell, mesuradors de cabal, temporitzadors automàtics, microprocessadors) han permès que avui en dia els SBRs competeixin amb els sistemes convencional de fangs actius. L'objectiu de la present tesi és la identificació de les condicions d'operació adequades per un cicle segons el tipus d'aigua residual a l'entrada, les necessitats del tractament i la qualitat desitjada de la sortida utilitzant la tecnologia SBR. Aquestes tres característiques, l'aigua a tractar, les necessitats del tractament i la qualitat final desitjada determinen en gran mesura el tractament a realitzar. Així doncs, per tal d'adequar el tractament a cada tipus d'aigua residual i les seves necessitats, han estat estudiats diferents estratègies d'alimentació. El seguiment del procés es realitza mitjançant mesures on-line de pH, OD i RedOx, els canvis de les quals donen informació sobre l'estat del procés. Alhora un altre paràmetre que es pot calcular a partir de l'oxigen dissolt és la OUR que és una dada complementària als paràmetres esmentats. S'han avaluat les condicions d'operació per eliminar nitrogen d'una aigua residual sintètica utilitzant una estratègia d'alimentació esglaonada, a través de l'estudi de l'efecte del nombre d'alimentacions, la definició de la llargada i el número de fases per cicle, i la identificació dels punts crítics seguint les sondes de pH, OD i RedOx. S'ha aplicat l'estratègia d'alimentació esglaonada a dues aigües residuals diferents: una procedent d'una indústria tèxtil i l'altra, dels lixiviats d'un abocador. En ambdues aigües residuals es va estudiar l'eficiència del procés a partir de les condicions d'operació i de la velocitat del consum d'oxigen. Mentre que en l'aigua residual tèxtil el principal objectiu era eliminar matèria orgànica, en l'aigua procedent dels lixiviats d'abocador era eliminar matèria orgànica i nitrogen. S'han avaluat les condicions d'operació per eliminar nitrogen i fòsfor d'una aigua residual urbana utilitzant una estratègia d'alimentació esglaonada, a través de la definició del número i la llargada de les fases per cicle, i la identificació dels punts crítics seguint les sondes de pH, OD i RedOx. S'ha analitzat la influència del pH i la font de carboni per tal d'eliminar fòsfor d'una aigua sintètica a partir de l'estudi de l'increment de pH a dos reactors amb diferents fonts de carboni i l'estudi de l'efecte de canviar la font de carboni. Tal i com es pot veure al llarg de la tesi, on s'han tractat diferents aigües residuals per a diferents necessitats, un dels avantatges més importants d'un SBR és la seva flexibilitat.

Integració 3D de detectors de píxels híbrids

La miniaturització de la industria microelectrònica és un fet del tot inqüestionables i la tecnologia CMOS no n'és una excepció. En conseqüència la comunitat científica s'ha plantejat dos grans reptes: En primer lloc portar la tecnologia CMOS el més lluny possible ('Beyond CMOS') tot desenvolupant sistemes d'altes prestacions com microprocessadors, micro - nanosistemes o bé sistemes de píxels. I en segon lloc encetar una nova generació electrònica basada en tecnologies totalment diferents dins l'àmbit de les Nanotecnologies. Tots aquests avanços exigeixen una recerca i innovació constant en la resta d'àrees complementaries com són les d'encapsulat. L'encapsulat ha de satisfer bàsicament tres funcions: Interfície elèctrica del sistema amb l'exterior, Proporcionar un suport mecànic al sistema i Proporcionar un camí de dissipació de calor. Per tant, si tenim en compte que la majoria d'aquests dispositius d'altes prestacions demanden un alt nombre d'entrades i sortides, els mòduls multixip (MCMs) i la tecnologia flip chip es presenten com una solució molt interessant per aquests tipus de dispositiu. L'objectiu d'aquesta tesi és la de desenvolupar una tecnologia de mòduls multixip basada en interconnexions flip chip per a la integració de detectors de píxels híbrids, que inclou: 1) El desenvolupament d'una tecnologia de bumping basada en bumps de soldadura Sn/Ag eutèctics dipositats per electrodeposició amb un pitch de 50µm, i 2) El desenvolupament d'una tecnologia de vies d'or en silici que permet interconnectar i apilar xips verticalment (3D packaging) amb un pitch de 100µm. Finalment aquesta alta capacitat d'interconnexió dels encapsulats flip chip ha permès que sistemes de píxels tradicionalment monolítics puguin evolucionar cap a sistemes híbrids més compactes i complexes, i que en aquesta tesi s'ha vist reflectit transferint la tecnologia desenvolupada al camp de la física d'altes energies, en concret implantant el sistema de bump bonding d'un mamògraf digital. Addicionalment s'ha implantat també un dispositiu detector híbrid modular per a la reconstrucció d'imatges 3D en temps real, que ha donat lloc a una patent.

Decentralized load balancing for highly irregular search problems

In this paper, we present a distributed computing framework for problems characterized by a highly irregular search tree, whereby no reliable workload prediction is available. The framework is based on a peer-to-peer computing environment and dynamic load balancing. The system allows for dynamic resource aggregation, does not depend on any specific meta-computing middleware and is suitable for large-scale, multi-domain, heterogeneous environments, such as computational Grids. Dynamic load balancing policies based on global statistics are known to provide optimal load balancing performance, while randomized techniques provide high scalability. The proposed method combines both advantages and adopts distributed job-pools and a randomized polling technique. The framework has been successfully adopted in a parallel search algorithm for subgraph mining and evaluated on a molecular compounds dataset. The parallel application has shown good calability and close-to linear speedup in a distributed network of workstations.

A comparison-based diagnosis algorithm tailored for crossed cube multiprocessor systems

Comparison-based diagnosis is an effective approach to system-level fault diagnosis. Under the Maeng-Malek comparison model (NM* model), Sengupta and Dahbura proposed an O(N-5) diagnosis algorithm for general diagnosable systems with N nodes. Thanks to lower diameter and better graph embedding capability as compared with a hypercube of the same size, the crossed cube has been a promising candidate for interconnection networks. In this paper, we propose a fault diagnosis algorithm tailored for crossed cube connected multicomputer systems under the MM* model. By introducing appropriate data structures, this algorithm runs in O(Nlog(2)(2) N) time, which is linear in the size of the input. As a result, this algorithm is significantly superior to the Sengupta-Dahbura's algorithm when applied to crossed cube systems. (C) 2004 Elsevier B.V. All rights reserved.

Pancyclicity of Mobius cubes with faulty nodes

An interconnection network with n nodes is four-pancyclic if it contains a cycle of length l for each integer l with 4 <= l <= n. An interconnection network is fault-tolerant four-pancyclic if the surviving network is four-pancyclic in the presence of faults. The fault-tolerant four-pancyclicity of interconnection networks is a desired property because many classical parallel algorithms can be mapped onto such networks in a communication-efficient fashion, even in the presence of failing nodes or edges. Due to some attractive properties as compared with its hypercube counterpart of the same size, the Mobius cube has been proposed as a promising candidate for interconnection topology. Hsieh and Chen [S.Y. Hsieh, C.H. Chen, Pancyclicity on Mobius cubes with maximal edge faults, Parallel Computing, 30(3) (2004) 407-421.] showed that an n-dimensional Mobius cube is four-pancyclic in the presence of up to n-2 faulty edges. In this paper, we show that an n-dimensional Mobius cube is four-pancyclic in the presence of up to n-2 faulty nodes. The obtained result is optimal in that, if n-1 nodes are removed, the surviving network may not be four-pancyclic. (C) 2005 Elsevier B.V. All rights reserved.

Microprocessor systems: an introduction

The aim of this book is to provide and introduction to microprocessor systems, their operation and design. It covers those topics needed by engineers and computer scientists who are interested in applying microprocessors in practical situations, namely computer hardware including logic and interfacing, software, in particular high level and assembly language programming, and the design and testing of such systems. The fundamental principles of micrprocessor systems are described and these are illustrated with reference to two microprocessors, the 32-bit MC68020 from Motorola and a single chip microcomputer, the 8051 from Intel; and in addition, interfacing to the general purpose STE bus is described. The details of the processors and the bus are concentrated in three chapters, thus allowing the presentation of the material to be independent of the microprocessors if that is desired, and permitting the specific details to be found easily.

Hardware development of the Yorick series of active vision systems

This paper presents a review of the design and development of the Yorick series of active stereo camera platforms and their integration into real-time closed loop active vision systems, whose applications span surveillance, navigation of autonomously guided vehicles (AGVs), and inspection tasks for teleoperation, including immersive visual telepresence. The mechatronic approach adopted for the design of the first system, including head/eye platform, local controller, vision engine, gaze controller and system integration, proved to be very successful. The design team comprised researchers with experience in parallel computing, robot control, mechanical design and machine vision. The success of the project has generated sufficient interest to sanction a number of revisions of the original head design, including the design of a lightweight compact head for use on a robot arm, and the further development of a robot head to look specifically at increasing visual resolution for visual telepresence. The controller and vision processing engines have also been upgraded, to include the control of robot heads on mobile platforms and control of vergence through tracking of an operator's eye movement. This paper details the hardware development of the different active vision/telepresence systems.