A Hybrid Five-Level Inverter With Common-Mode Voltage Elimination Having Single Voltage Source for IM Drive Applications

A new hybrid five-level inverter topology with common-mode voltage (CMV) elimination for induction motor drive is proposed in this paper. This topology has only one dc source, and different voltage levels are generated by using this voltage source along with floating capacitors charged to asymmetrical voltage levels. The pulsewidth modulation (PWM) scheme employed in this topology balances the capacitor voltages at the required levels at any power factor and modulation index while eliminating the CMV. This inverter has good fault-tolerant capability as it can be operated in three-or two-level mode with CMV elimination, in case of any failure in the H-bridges. More voltage levels with CMV elimination can be realized from this topology but only in a limited range of modulation index and power factor. Extensive simulation is done to validate the PWM technique for CMV elimination and balancing of the capacitor voltages. The experimental verification of the proposed inverter-fed induction motor is carried out in the linear modulation and overmodulation regions. The steady-state and transient operations of the drive are verified. The dynamics of the capacitor voltage balancing is also tested. The experimental results demonstrate that the proposed topology can be considered for industrial drive applications.

Nearly constant switching frequency hysteresis current controller for general n-level inverter fed induction motor drive

A current-error space phasor based hysteresis controller with nearly constant switching frequency is proposed for a general n-level voltage source inverter fed three-phase induction motor drive. Like voltage-controlled space vector PWM (SVPWM), the proposed controller can precisely detect sub-sector changes and for switching it selects only the nearest switching voltage vectors using the information of the estimated fundamental stator voltages along α and β axes. It provides smooth transition between voltage levels, including operation in over modulation region. Due to adjacent switching amongst the nearest switching vectors forming a triangular sub-sector, in which tip of the fundamental stator voltage vector of the machine lies, switching loss is reduced while keeping the current-error space phasor within the varying parabolic boundary. Appropriate dimension and orientation of this parabolic boundary ensures similar switching frequency spectrum like constant switching frequency SVPWM-based induction motor (IM) drive. Inherent advantages of multi-level inverter and space phasor based current hysteresis controller are retained. The proposed controller is simulated as well as implemented on a 5-level inverter fed 7.5 kW open-end winding IM drive.

A Space-Vector-Based Hysteresis Current Controller for a General n-Level Inverter-Fed Drive With Nearly Constant Switching Frequency Control

A current-error space-vector-based hysteresis current controller for a general n-level voltage-source inverter (VSI)-fed three-phase induction motor (IM) drive is proposed here, with control of the switching frequency variation for the full linear modulation range. The proposed current controller monitors the space-vector-based current error of an n-level VSI-fed IM to keep the current error within a parabolic boundary, using the information of the current triangular sector in which the tip of the reference vector lies. Information of the reference voltage vector is estimated using the measured current-error space vectors, along the alpha- and beta-axes. Appropriate dimension and orientation of this parabolic boundary ensure a switching frequency spectrum similar to that of a constant-switching-frequency voltage-controlled space vector pulsewidth modulation (PWM) (SVPWM)-based IM drive. Like SVPWM for multilevel inverters, the proposed controller selects inverter switching vectors, forming a triangular sector in which the tip of the reference vector stays, for the hysteresis PWM control. The sector in the n-level inverter space vector diagram, in which the tip of the fundamental stator voltage stays, is precisely detected, using the sampled reference space vector estimated from the instantaneous current-error space vectors. The proposed controller retains all the advantages of a conventional hysteresis controller such as fast current control, with smooth transition to the overmodulation region. The proposed controller is implemented on a five-level VSI-fed 7.5-kW IM drive.

A Hybrid Multilevel Inverter System Based on Dodecagonal Space Vectors for Medium Voltage IM Drives

Dodecagonal (12-sided) space vector pulsewidth modulation (PWM) schemes are characterized by the complete absence of (6n +/- 1)th-order harmonics (for odd n) in the phase voltages, within the linear modulation range and beyond, including over-modulation. This paper presents a new topology suitable for the realization of such multilevel inverter schemes for induction motor (IM) drives, by cascading two-level inverters with flying-capacitor-inverter fed floating H-bridge cells. Now, any standard IM may be used to get the dodecagonal operation which hitherto was possible only with open-end winding IM. To minimize the current total harmonic distortion (THD), a strategy for synchronous PWM is also proposed. It is shown that the proposed method is capable of obtaining better THD figures, compared to conventional dodecagonal schemes. The topology and the PWM strategy are validated through analysis and subsequently verified experimentally.

A Multilevel Inverter Scheme With Dodecagonal Voltage Space Vectors Based on Flying Capacitor Topology for Induction Motor Drives

This paper presents a multilevel inverter topology suitable for the generation of dodecagonal space vectors instead of hexagonal space vectors as in the case of conventional schemes. This feature eliminates all the 6n +/- 1 (n = odd) harmonics from the phase voltages and currents in the entire modulation range with an increase in the linear modulation range. The topology is realized by flying capacitor-based three-level inverters feeding from two ends of an open-end winding induction motor with asymmetric dc links. The flying capacitor voltages are tightly controlled throughout the modulation range using redundant switching states for any load power factor. A simple and fast carrier-based space-vector pulsewidth modulation (PWM) scheme is also proposed for the topology which utilizes only the sampled amplitudes of the reference wave for the PWM timing computation.

Harmonic Analysis of DC-Link Capacitor Current in Sinusoidally Modulated Neutral-Point-Clamped Inverter

The voltage ripple and power loss in the DC-capacitor of a voltage source inverter depend on the harmonic currents flowing through the capacitor. This paper presents double Fourier series based harmonic analysis of DC capacitor current in a three-level neutral point clamped inverter, modulated with sine-triangle PWM. The analytical results are validated experimentally on a 5-kVA three-level inverter prototype. The results of the analysis are used for predicting the power loss in the DC capacitor.

Study on the Effect of Dead Time and its Compensation for Bus-Clamping PWM Techniques

Dead-time is provided in between the gating signals of the top and bottom semiconductor switches in an inverter leg to prevent the shorting of DC bus. Due to this dead time, there is a significant unwanted change in the output voltage of the inverter. The effect is different for different pulse width modulation (PWM) methodologies. The effect of dead-time on the output fundamental voltage is studied theoretically as well as experimentally for bus-clamping PWM methodologies. Further, experimental observations on the effectiveness of dead-time compensation are presented.

A Quick-Simulation Tool for Induction Motor Drives Controlled Using Advanced Space-Vector-Based PWM Techniques

Space-vector-based pulse width modulation (PWM) for a voltage source inverter (VSI) offers flexibility in terms of different switching sequences. Numerical simulation is helpful to assess the performance of a PWM method before actual implementation. A quick-simulation tool to simulate a variety of space-vector-based PWM strategies for a two-level VSI-fed squirrel cage induction motor drive is presented. The simulator is developed using C and Python programming languages, and has a graphical user interface (GUI) also. The prime focus being PWM strategies, the simulator developed is 40 times faster than MATLAB in terms of the actual time taken for a simulation. Simulation and experimental results are presented on a 5-hp ac motor drive.

A 5th and 7th Order Harmonic Suppression Scheme for Open-end Winding Asymmetrical Six-phase IM Drive Using Capacitor-fed Inverter

Voltage source inverter (VSI) fed six-phase induction motor drives have high 6n +/- 1; n = odd order harmonic currents, due to absence of back emf for these currents. To suppress these harmonic currents, either bulky inductive harmonic filters or complex pulse width modulation (PWM) techniques have to be used. This paper proposes a simple harmonic elimination scheme using capacitor fed inverters, for an asymmetrical six-phase induction motor VSI fed drive. Two three phase inverters fed from a single capacitor is used on the open-end side of the motor, to suppress 6n +/- 1; n = odd order harmonics. A PWM scheme that can suppress the harmonics, as well as balance the capacitor voltage is also proposed. The capacitor fed inverters are switched so that the fundamental voltage is not affected. The proposed scheme is verified using MATLAB Simulink simulation at different speeds. The effectiveness of the scheme is demonstrated by comparing the results with those obtained by disabling the capacitor fed inverters. Experimental results are also provided to validate the functionality of the proposed controller.

Analysis of the modulation process in advanced bus-clamping PWM techniques

Advanced bus-clamping pulse width modulation (ABCPWM) techniques are advantageous in terms of line current distortion and inverter switching loss in voltage source inverter-fed applications. However, the PWM waveforms corresponding to these techniques are not amenable to carrier-based generation. The modulation process in ABCPWM methods is analyzed here from a “per-phase” perspective. It is shown that three sets of descendant modulating functions (or modified modulating functions) can be generated from the three-phase sinusoidal signals. Each set of the modified modulating functions can be used to produce the PWM waveform of a given phase in a computationally efficient manner. Theoretical results and experimental investigations on a 5hp motor drive are presented

Space-Vector-Based Hybrid Pulsewidth Modulation Techniques for a Three-Level Inverter

Novel switching sequences have been proposed recently for a neutral-point-clamped three-level inverter, controlled effectively as an equivalent two-level inverter. It is shown that the four novel sequences can be grouped into two pairs of sequences. Using each pair of sequences, a hybrid pulsewidth modulation (PWM) technique is proposed, which deploys the two sequences in appropriate spatial regions to reduce the current ripple. Further, a third hybrid PWM technique is proposed which uses all the five sequences (including the conventional sequence) in appropriate spatial regions. Each proposed hybrid PWM is shown, both analytically and experimentally, to outperform its constituent PWM methods in terms of harmonic distortion. In particular, the third proposed hybrid PWM reduces the total harmonic distortion considerably at low- and high-speed ranges of a constant volts-per-hertz induction motor drive, compared to centered space vector PWM.

On-line Estimation of Fundamental and Ripple Components of Line Currents in a Voltage-Source Inverter Operated at Low Switching Frequency

High-power voltage-source inverters (VSI) are often switched at low frequencies due to switching loss constraints. Numerous low-switching-frequency PWM techniques have been reported, which are quite successful in reducing the total harmonic distortion under open-loop conditions at such low operating frequencies. However, the line current still contains low-frequency components (though of reduced amplitudes), which are fed back to the current loop controller during closed-loop operation. Since the harmonic frequencies are quite low and are not much higher than the bandwidth of the current loop, these are amplified by the current controller, causing oscillations and instability. Hence, only the fundamental current should be fed back. Filtering out these harmonics from the measured current (before feeding back) leads to phase shift and attenuation of the fundamental component, while not eliminating the harmonics totally. This paper proposes a method for on-line extraction of the fundamental current in induction motor drives, modulated with low-switching-frequency PWM. The proposed method is validated through simulations on MATLAB/Simulink. Further, the proposed algorithm is implemented on Cyclone FPGA based controller board. Experimental results are presented for an R-L load.

Space vector based modulation scheme for reducing capacitor RMS current in three-level diode-clamped inverter

The DC capacitor is an important component in a voltage source inverter.The RMS current flowing through the capacitor determines the capacitor size and losses. The losses, in turn, influence the capacitor life. This paper proposes a space vector based modulation strategy for reducing the capacitor RMS current in a three-level diode-clamped inverter. An analytical closed-form expression is derived for the DC capacitor RMS current with the proposed PWM strategy. The analytical expression is validated through simulations and also experimentally. Theoretical and experimental results are presented, comparing the proposed strategy with conventional space vector PWM (CSVPWM). It is shown that the proposed strategy reduces the capacitor RMS current significantly at high modulation indices and high power factors. (C) 2014 Elsevier B.V. All rights reserved.

Filter Configuration and PWM Method For Single Phase Inverters with Reduced Conducted EMI Noise

Electromagnetic Interference (EMI) noise is one of the major issues during the design of the grid-tied power converters. Presence of high dv/dt in Common Mode (CM) voltage, excites the parasitic capacitances and causes injection of narrow peaky current to ground. This results in high EMI noise level. A topology consisting of a single phase PWM-rectifier with LCL filter, utilising bipolar PWM method is proposed which reduces the EMI noise level by more than 30dB. This filter topology is shown to be insensitive to the switching delays between the legs of the inverter. The proposed topology eliminates high dv/dt from the dc-bus CM voltage by making it sinusoidal. Hence, the high frequency CM current injection to ground is minimized.

Study of Multilevel Sinusoidal PWM methods for Cascaded H-Bridge Multilevel Inverters

This paper is a study of Multilevel Sinusoidal Pulse Width Modulation (MSPWM) methods; Phase Disposition (PD), Alternate Phase Opposition Disposition (APOD), Phase Opposition Disposition (POD) on a single phase Cascaded H-Bridge Multilevel inverter. Various factors such as amplitude modulation index (Ma), frequency modulation index (M-f), phase angle between carrier and reference modulating wave (phi) have been considered for simulation. Variation in these factors and their effect on inverter performance is evaluated. Factors such as DC bus utilization, output r.m.s voltage, total harmonic distortion (%THD), dominant harmonic order, switching losses are evaluated based on simulation results.