Evaluation and modeling of lanthanum diffusion in TiN/La 2O 3/HfSiON/SiO 2/Si high-k stacks

In this study, TiN/La 2O 3/HfSiON/SiO 2/Si gate stacks with thick high-k (HK) and thick pedestal oxide were used. Samples were annealed at different temperatures and times in order to characterize in detail the interaction mechanisms between La and the gate stack layers. Time-of-flight secondary ion mass spectrometry (ToF-SIMS) measurements performed on these samples show a time diffusion saturation of La in the high-k insulator, indicating an La front immobilization due to LaSiO formation at the high-k/interfacial layer. Based on the SIMS data, a technology computer aided design (TCAD) diffusion model including La time diffusion saturation effect was developed. © 2012 American Institute of Physics.

Three-dimensional distribution of Al in high-k metal gate: Impact on transistor voltage threshold

The three-dimensional spatial distribution of Al in the high-k metal gates of metal-oxide-semiconductor field-effect-transistors is measured by atom probe tomography. Chemical distribution is correlated with the transistor voltage threshold (VTH) shift generated by the introduction of a metallic Al layer in the metal gate. After a 1050 °C annealing, it is shown that a 2-Å thick Al layer completely diffuses into oxide layers, while a positive VTH shift is measured. On the contrary, for thicker Al layers, Al precipitation in the metal gate stack is observed and the VTH shift becomes negative. © 2012 American Institute of Physics.

Development of high-k gate dielectric materials

The traditional gate dielectric material Of SiO2 can not satisfy the need of the continuous downscaling of CMOS dimensions. High-K gate dielectric materials have attracted extensive research efforts recently and obtained great progress. In this paper, the developments of high-K gate materials were reviewed. Based on the author's background and research work in the area, the latest achievements of high-K gate dielectric materials on the recrystalization temperature, the low-K interface layer, and the dielectric breakdown and metal gate electrode were introduced in detail.

Role of interface dipole in metal gate/high-k effective work function modulation by aluminum incorporation

The interface dipole and its role in the effective work function (EWF) modulation by Al incorporation are investigated. Our study shows that the interface dipole located at the high-k/SiO2 interface causes an electrostatic potential difference across the metal/high-k interface, which significantly shifts the band alignment between the metal and high-k, consequently modulating the EWF. The electrochemical potential equalization and electrostatic potential methods are used to evaluate the interface dipole and its contribution. The calculated EWF modulation agrees with experimental data and can provide insight to the control of EWF in future pMOS technology.

Properties of high k gate dielectric gadolinium oxide deposited on Si(100) by dual ion beam deposition (DIBD)

Gadolinium oxide thin films have been prepared on silicon (100) substrates with a low-energy dual ion-beam epitaxial technique. Substrate temperature was an important factor to affect the crystal structures and textures in an ion energy range of 100-500 eV. The films had a monoclinic Gd2O3 structure with preferred orientation ((4) over bar 02) at low substrate temperatures. When the substrate temperature was increased, the orientation turned to (202), and finally, the cubic structure appeared at the substrate temperature of 700 degreesC, which disagreed with the previous report because of the ion energy. The AES studies found that Gadolinium oxide shared Gd2O3 structures, although there were a lot of oxygen deficiencies in the films, and the XPS results confirmed this. AFM was also used to investigate the surface images of the samples. Finally, the electrical properties were presented. (C) 2004 Elsevier B.V. All rights reserved.

Origin of flat-band voltage sharp roll-off in metal gate/high-k/ultrathin- SiO2/Si p-channel metal-oxide-semiconductor stacks

The origin of the flat band voltage roll-off (V-FB roll-off) in metal gate/high-k/ultrathin-SiO2/Si metal-oxide-semiconductor stacks is analyzed and a model describing the role of the dipoles at the SiO2/Si interface on the V-FB sharp roll-off is proposed. The V-FB sharp roll-off appears when the thickness of the SiO2 interlayer diminishes to below the oxygen diffusion depth. The results derived using our model agree well with experimental data and provide insights to the mechanism of the V-FB sharp roll-off.

Fermi-Level Pinning at Metal/High-k Interface Influenced by Electron State Density of Metal Gate

The Fermi-level pinning (FLP) at the metal/high-k interface and its dependence on the electron state density of the metal gate are investigated. It is found that the FLP is largely determined by the distortion of the vacuum level of the metal which is quantitatively ruled by the electron state density of the metal. The physical origin of the vacuum level distortion of the metal is attributed to an image charge of the interface charge in the metal. Such results indicate that the effective work function of the metal/high-k stack is also governed by the electron state density of the metal.

Optimisation of source/drain extension region profile for suppression of short channel effects in sub-50 nm DG SOI MOSFETs with high- k gate dielectrics

Novel technology dependent scaling parameters i.e. spacer to gradient ratio and effective channel length (Leff) are proposed for source/drain engineered DG MOSFET, and their significance in minimizing short channel effects (SCES) in high-k gate dielectrics is discussed in detail. Results show that a high-k dielectric should be associated with a higher spacer to gradient ratio to minimise SCEs The analytical model agrees with simulated data over the entire range of spacer widths, doping gradients, high-k gate dielectrics and effective channel lengths.