Regulating bereavement : inquests, family pressure and the gate keeping of suicide statistics

This study of English Coronial practice raises a number of questions, not only regarding state investigations of suicide, but also of the role of the Coroner itself. Following observations at over 20 inquests into possible suicides, and in-depth interviews with six Coroners, three main issue emerged: first, there exists considerable slippage between different Coroners over which deaths are likely to be classified as suicide; second, the high standard of proof required, and immense pressure faced by Coroners from family members at inquest to reach any verdict other than suicide, can significantly depress likely suicide rates; and finally, Coroners feel no professional obligation, either individually or collectively, to contribute to the production of consistent and useful social data regarding suicide—arguably rendering comparative suicide statistics relatively worthless. These issues lead, ultimately, to a more important question about the role we expect Coroners to play within social governance, and within an effective, contemporary democracy.

An isolated MOSFET gate driver

Traditional methods of isolated MOSFET/IGBT gate drive are presented, and their pros and cons assessed. The best options are chosen to meet our objective— a small, high speed, low cost, low power isolated gate drive module. Two small ferrite bead transformers are used for isolation, one transmits power at 2.5MHz, the other sends narrow set reset pulses. On the secondary these pulses drive a transistor totem pole to ensure high current drive, and the value is held by CMOS buffers with positive feedback. An alternative design for driving logic level devices uses only an HC buffer on the secondary. Double sided SMDconstruction (primary one side, secondary on the other) yields an upright module 40x18x5mm. Propagation delaywas 20ns, and rise/fall time 15ns with a 1nF load. The design places no limits on frequency of operation or duty cycle. Power supply requirementswere 5V@20mA for operation below 100kHz, dominated by magnetising current.

Plasma functionalization of SiO2 nanoparticles for the synthesis of polymer nano-dielectrics

In this study, we improve the insulation performance of polymeric nano-dielectrics by using plasma pre-treatment on the filled nanoparticles. Non-equilibrium atmospheric-pressure plasma is employed to modify a commercial type of silane-coated SiO2 nanoparticles. The treated nanoparticles and the synthesized epoxy-based nanocomposites are characterized using scanning electron microscopy (SEM), Fourier transform infrared spectroscopy (FTIR), and X-ray photoelectron spectroscopy (XPS). The plasma-treated SiO2 nanoparticles can disperse uniformly and form strong covalent bonds with the molecules of the polymer matrix. Moreover, the electrical insulation properties of the synthesized nanocomposites are investigated. Results show that the nanocomposites with plasma-treated SiO2 nanoparticles obtain improved dielectric breakdown strength and extended endurance under intense electrical ageing process.

An improved gate driver for power MOSFETs using a cascode configuration

To overcome the limitations of existing gate drive topologies an improved gate drive concept is proposed to provide fast, controlled switching of power MOSFETs. The proposed topology exploits the cascode configuration with the inclusion of an active gate clamp to ensure that the driven MOSFET may be turned off under all load conditions. Key operating principles and advantages of the proposed gate drive topology are discussed. Characteristic waveforms are investigated via simulation and experimentation for the cascode driver in an inductive switching application at 375V and 10A. Experimental waveforms compared well with simulations with long gate charging delays (including the Miller plateau) being eliminated from the gate voltage waveform.

Logic-gate devices based on printed polymer semiconducting nanostripes

The applications of organic semiconductors in complex circuitry such as printed CMOS-like logic circuits demand miniaturization of the active structures to the submicrometric and nanoscale level while enhancing or at least preserving the charge transport properties upon processing. Here, we addressed this issue by using a wet lithographic technique, which exploits and enhances the molecular order in polymers by spatial confinement, to fabricate ambipolar organic field effect transistors and inverter circuits based on nanostructured single component ambipolar polymeric semiconductor. In our devices, the current flows through a precisely defined array of nanostripes made of a highly ordered diketopyrrolopyrrole-benzothiadiazole copolymer with high charge carrier mobility (1.45 cm2 V-1 s-1 for electrons and 0.70 cm2 V-1 s-1 for holes). Finally, we demonstrated the functionality of the ambipolar nanostripe transistors by assembling them into an inverter circuit that exhibits a gain (105) comparable to inverters based on single crystal semiconductors.

High mobility top-gate and dual-gate polymer thin-film transistors based on diketopyrrolopyrrole-naphthalene copolymer

In this letter, the performance characteristics of top-gate and dual-gate thin-film transistors (TFTs) with active semiconductor layers consisting of diketopyrrolopyrrole-naphthalene copolymer are described. Optimized top-gate TFTs possess mobilities of up to 1 cm 2 /V s with low contact resistance and reduced hysteresis in air. Dual-gate devices possess higher drive currents as well as improved subthreshold and above threshold characteristics compared to single-gate devices. We also describe the reasons that dual-gate devices result in improved performance. The good stability of this polymer combined with their promising electrical properties make this material a very promising semiconductor for printable electronics.

Charge-carrier velocity distributions in high-mobility polymer dual-gate thin-film transistors

We report charge-carrier velocity distributions in high-mobility polymer thin-film transistors (PTFTs) employing a dual-gate configuration. Our time-domain measurements of dual-gate PTFTs indicate higher effective mobility as well as fewer low-velocity carriers than in single-gate operation. Such nonquasi-static (NQS) measurements support and clarify the previously reported results of improved device performance in dual-gate devices by various groups. We believe that this letter demonstrates the utility of NQS measurements in studying charge-carrier transport in dual-gate thin-film transistors.

Solution-processed dual-gate polymer field-effect transistors for display applications

We describe the advantages of dual-gate thin-film transistors (TFTs) for display applications. We show that in TFTs with active semiconductor layers composed of diketopyrrolopyrrole-naphthalene copolymer, the on-current is increased, the off-current is reduced, and the sub-threshold swing is improved compared to single-gate devices. Charge transport measurements in steady-state and under non-quasi-static conditions reveal the reasons for this improved performance. We show that in dual-gate devices, a much smaller fraction of charge carriers move in slow trap states. We also compare the activation energies for charge transport in the top-gate and bottom-gate configurations.

Comparison of the gate drive parameter space for driving power MOSFETs using conventional and cascode configurations

Conventional voltage driven gate drive circuits utilise a resistor to control the switching speed of power MOS-FETs. The gate resistance is adjusted to provide controlled rate of change of load current and voltage. The cascode gate drive configuration has been proposed as an alternative to the conventional resistor-fed gate drive circuit. While cascode drive is broadly understood in the literature the switching characteristics of this topology are not well documented. This paper explores, through both simulation and experimentation, the gate drive parameter space of the cascode gate drive configuration and provides a comparison to the switching characteristics of conventional gate drive.

Characterisation of the cascode gate drive of power MOSFETs in clamped inductive switching applications

This thesis proposes a novel gate drive circuit to improve the switching performance of MOSFET power switches in power electronic converters. The proposed topology exploits the cascode configuration, allowing the minimisation of switching losses in the presence of practical circuit constraints, which enables efficiency and power density improvements. Switching characteristics of the new topology are investigated and key mechanisms that control the switching process are identified. Unique analysis tools and techniques are also developed to demonstrate the application of the cascode gate drive circuit for switching performance optimisation.

Lock the gate: Fracking, investor-state dispute settlement, and the Trans-Pacific Partnership

There has been much debate about the relationship between international trade, the environment, biodiversity protection, and climate change.The Obama Administration has pushed such issues into sharp relief, with its advocacy for sweeping international trade agreements, such as the Trans-Pacific Partnership and the Trans-Atlantic Trade and Investment Partnership. There has been much public concern about the impact of the mega-trade deals upon the protection of the environment. In particular, there has been a debate about whether the Trans-Pacific Partnership will promote dirty fracking. Will the Trans-Pacific Partnership transform the Pacific Rim into a Gasland?There has been a particular focus upon investor-state dispute settlement being used by unconventional mining companies. Investor-state dispute settlement is a mechanism which enables foreign investors to seek compensation from national governments at international arbitration tribunals. In her prescient 2009 book, The Expropriation of Environmental Governance, Kyla Tienhaara foresaw the rise of investor-state dispute resolution of environmental matters. She observed:'Over the last decade there has been an explosive increase of cases investment arbitration. This is significant in terms of not only the number of disputes that have arisen and the number of states that have been involved, but also the novel types of dispute that have emerged. Rather than solely involving straightforward incidences of nationalization or breach of contract, modern disputes often revolve around public policy measures and implicate sensitive issues such as access to drinking water, development on sacred indigenous sites and the protection of biodiversity.'In her study, Kyla Tienhaara observed that investment agreements, foreign investment contracts and investment arbitration had significant implications for the protection for the protection of the environment. She concluded that arbitrators have made it clear that they can, and will, award compensation to investors that claim to have been harmed by environmental regulation. She also found that some of the cases suggest that the mere threat of arbitration is sufficient to chill environmental policy development. Tienhaara was equally concerned by the possibility that a government may use the threat of arbitration as an excuse or cover for its failure to improve environmental regulation. In her view, it is evident that arbitrators have expropriated certain fundamental aspects of environmental governance from states. Tienhaara held: As a result, environmental regulation has become riskier, more expensive, and less democratic, especially in developing countries. This article provides a comparative analysis of the battles over fracking, investment, trade, and the environment in a number of key jurisdictions including the United States, Canada, Australia, and New Zealand. Part 1 focuses upon the United States. Part 2 examines the dispute between the Lone Pine Resources Inc. and the Government of Canada over a fracking moratorium in Quebec. Part 3 charts the rise of the Lock the Gate Alliance in Australia, and its demands for a moratorium in respect of coal seam gas and unconventional mining. Part 4 focuses upon parallel developments in New Zealand. This article concludes that Pacific Rim countries should withdraw from investor-state dispute settlement procedures, because of the threat posed to environmental regulation in respect of air, land, and water.

Modeling of Channel Potential and Subthreshold Slope of Symmetric Double-Gate Transistor

A new physically based classical continuous potential distribution model, particularly considering the channel center, is proposed for a short-channel undoped body symmetrical double-gate transistor. It involves a novel technique for solving the 2-D nonlinear Poisson's equation in a rectangular coordinate system, which makes the model valid from weak to strong inversion regimes and from the channel center to the surface. We demonstrated, using the proposed model, that the channel potential versus gate voltage characteristics for the devices having equal channel lengths but different thicknesses pass through a single common point (termed ``crossover point''). Based on the potential model, a new compact model for the subthreshold swing is formulated. It is shown that for the devices having very high short-channel effects (SCE), the effective subthreshold slope factor is mainly dictated by the potential close to the channel center rather than the surface. SCEs and drain-induced barrier lowering are also assessed using the proposed model and validated against a professional numerical device simulator.

Within-Die Gate Delay Variability Measurement using Re-configurable Ring Oscillator

We report a circuit technique to measure the on-chip delay of an individual logic gate (both inverting and non-inverting) in its unmodified form using digitally reconfigurable ring oscillator (RO). Solving a system of linear equations with different configuration setting of the RO gives delay of an individual gate. Experimental results from a test chip in 65nm process node show the feasibility of measuring the delay of an individual inverter to within 1pS accuracy. Delay measurements of different nominally identical inverters in close physical proximity show variations of up to 26% indicating the large impact of local or within-die variations.

Within-Die Gate Delay Variability Measurement Using Reconfigurable Ring Oscillator

We report the design and characterization of a circuit technique to measure the on-chip delay of an individual logic gate (both inverting and noninverting) in its unmodified form. The test circuit comprises of digitally reconfigurable ring oscillator (RO). The gate under test is embedded in each stage of the ring oscillator. A system of linear equations is then formed with different configuration settings of the RO, relating the individual gate delay to the measured period of the RO, whose solution gives the delay of the individual gates. Experimental results from a test chip in 65-nm process node show the feasibility of measuring the delay of an individual inverter to within 1 ps accuracy. Delay measurements of different nominally identicall inverters in close physical proximity show variations of up to 28% indicating the large impact of local variations. As a demonstration of this technique, we have studied delay variation with poly-pitch, length of diffusion (LOD) and different orientations of layout in silicon. The proposed technique is quite suitable for early process characterization, monitoring mature process in manufacturing and correlating model-to-hardware.

Garden gate to Daijas' father's house Architecture; Residences; Exterior

Verso: Das Gartentor zu Daijas Vaterhaus Georg lebete um die Ecke