Simultaneous demultiplexing, data regeneration, and clock recovery with a single semiconductor optical amplifier-based nonlinear-optical loop mirror

We demonstrate simultaneous demultiplexing, data regeneration and clock recovery at 10Gbits/s, using a single semiconductor optical amplifier–based nonlinear-optical loop mirror in a phase-locked loop configuration.

Simultaneous clock recovery and data regeneration using a nonlinear optical loop mirror as an all-optical mixer

High-speed optical clock recovery, demultiplexing and data regeneration will be integral parts of any future photonic network based on high bit-rate OTDM. Much research has been conducted on devices that perform these functions, however to date each process has been demonstrated independently. A very promising method of all-optical switching is that of a semiconductor optical amplifier-based nonlinear optical loop mirror (SOA-NOLM). This has various advantages compared with the standard fiber NOLM, most notably low switching power, compact size and stability. We use the SOA-NOLM as an all-optical mixer in a classical phase-locked loop arrangement to achieve optical clock recovery, while at the same time achieving data regeneration in a single compact device

Simultaneous clock recovery and data regeneration using a nonlinear optical loop mirror as an all-optical mixer

High-speed optical clock recovery, demultiplexing and data regeneration will be integral parts of any future photonic network based on high bit-rate OTDM. Much research has been conducted on devices that perform these functions, however to date each process has been demonstrated independently. A very promising method of all-optical switching is that of a semiconductor optical amplifier-based nonlinear optical loop mirror (SOA-NOLM). This has various advantages compared with the standard fiber NOLM, most notably low switching power, compact size and stability. We use the SOA-NOLM as an all-optical mixer in a classical phase-locked loop arrangement to achieve optical clock recovery, while at the same time achieving data regeneration in a single compact device

Simultaneous demultiplexing, data regeneration, and clock recovery with a single semiconductor optical amplifier-based nonlinear-optical loop mirror

We demonstrate simultaneous demultiplexing, data regeneration and clock recovery at 10Gbits/s, using a single semiconductor optical amplifier–based nonlinear-optical loop mirror in a phase-locked loop configuration.

Contribuições para estratégia de controle aplicada à geração fotovoltaica interconectada à rede elétrica

Generation systems, using renewable sources, are becoming increasingly popular due to the need for increased use of electricity. Currently, renewables sources have a role to cooperate with conventional generation, due to the system limitation in delivering the required power, the need for reduction of unwanted effects from sources that use fossil fuels (pollution) and the difficulty of building new transmission and/or distribution lines. This cooperation takes place through distributed generation. Therefore, this work proposes a control strategy for the interconnection of a PV (Photovoltaic) system generation distributed with a three-phase power grid through a connection filter the type LCL. The compensation of power quality at point of common coupling (PCC) is performed ensuring that the mains supply or consume only active power and that his currents have low distorcion. Unlike traditional techniques which require schemes for harmonic detection, the technique performs the harmonic compensation without the use of this schemes, controlling the output currents of the system in an indirect way. So that there is effective control of the DC (Direct Current) bus voltage is used the robust controller mode dual DSMPI (Dual-Sliding Mode-Proportional Integral), that behaves as a sliding mode controller SM-PI (Sliding Mode-Proportional Integral) during the transition and like a conventional PI (Proportional Integral) in the steady-state. For control of current is used to repetitive control strategy, which are used double sequence controllers (DSC) tuned to the fundamental component, the fifth and seventh harmonic. The output phase current are aligned with the phase angle of the utility voltage vector obtained from the use of a SRF-PLL (Synchronous Reference Frame Phase-Locked-Loop). In order to obtain the maximum power from the PV array is used a MPPT (Maximum Power Point Tracking) algorithm without the need for adding sensors. Experimental results are presented to demonstrate the effectiveness of the proposed control system.

Taming Chaotic Circuits

Control algorithms that exploit chaotic behavior can vastly improve the performance of many practical and useful systems. The program Perfect Moment is built around a collection of such techniques. It autonomously explores a dynamical system's behavior, using rules embodying theorems and definitions from nonlinear dynamics to zero in on interesting and useful parameter ranges and state-space regions. It then constructs a reference trajectory based on that information and causes the system to follow it. This program and its results are illustrated with several examples, among them the phase-locked loop, where sections of chaotic attractors are used to increase the capture range of the circuit.

Reference generator for voltage controlled power conditioners

Voltage reference generation is an important issue on electronic power conditioners or voltage compensators connected to the electric grid. Several equipments, such as Dynamic Voltage Restorers (DVR), Uninterruptable Power Supplies (UPS) and Unified Power Quality Conditioners (UPQC) need a proper voltage reference to be able to compensate electric network disturbances. This work presents a new reference generator's algorithm, based on vector algebra and digital filtering techniques. It is particularly suited for the development of voltage compensators with energy storage, which would be able to mitigate steady state disturbances, such as waveform distortions and unbalances, and also transient disturbances, like voltage sags and swells. Simulation and experimental results are presented for the validation of the proposed algorithm. © 2011 IEEE.

Simultaneous demultiplexing and clock recovery using a single electroabsorption modulator in a novel bi-directional configuration

A single electroabsorption modulator was used to demultiplex a 10 Gbit/s channel from a 40 Gbit/s OTDM data stream, whilst simultaneously recovering the 10 GHz electrical clock. This was achieved using a new bi-directional operation of the EA modulator, combined with a simple phase-locked loop feedback circuit. Excellent system performance was achieved, indicating that operation up to and beyond 100 Gbit/s is possible using current technology.

Simultaneous demultiplexing and clock recovery using a single electroabsorption modulator in a novel bi-directional configuration

A single electroabsorption modulator was used to demultiplex a 10 Gbit/s channel from a 40 Gbit/s OTDM data stream, whilst simultaneously recovering the 10 GHz electrical clock. This was achieved using a new bi-directional operation of the EA modulator, combined with a simple phase-locked loop feedback circuit. Excellent system performance was achieved, indicating that operation up to and beyond 100 Gbit/s is possible using current technology.

Fopid Controller Design for Robust Performance Using Particle Swarm Optimization

Mathematics Subject Classification: 26A33; 93C15, 93C55, 93B36, 93B35, 93B51; 03B42; 70Q05; 49N05

Enabling Blocks for Integrated CMOS UWB Transceivers

The last decades have seen an unrivaled growth and diffusion of mobile telecommunications. Several standards have been developed to this purposes, from GSM mobile phone communications to WLAN IEEE 802.11, providing different services for the the transmission of signals ranging from voice to high data rate digital communications and Digital Video Broadcasting (DVB). In this wide research and market field, this thesis focuses on Ultra Wideband (UWB) communications, an emerging technology for providing very high data rate transmissions over very short distances. In particular the presented research deals with the circuit design of enabling blocks for MB-OFDM UWB CMOS single-chip transceivers, namely the frequency synthesizer and the transmission mixer and power amplifier. First we discuss three different models for the simulation of chargepump phase-locked loops, namely the continuous time s-domain and discrete time z-domain approximations and the exact semi-analytical time-domain model. The limitations of the two approximated models are analyzed in terms of error in the computed settling time as a function of loop parameters, deriving practical conditions under which the different models are reliable for fast settling PLLs up to fourth order. Besides, a phase noise analysis method based upon the time-domain model is introduced and compared to the results obtained by means of the s-domain model. We compare the three models over the simulation of a fast switching PLL to be integrated in a frequency synthesizer for WiMedia MB-OFDM UWB systems. In the second part, the theoretical analysis is applied to the design of a 60mW 3.4 to 9.2GHz 12 Bands frequency synthesizer for MB-OFDM UWB based on two wide-band PLLs. The design is presented and discussed up to layout level. A test chip has been implemented in TSMC CMOS 90nm technology, measured data is provided. The functionality of the circuit is proved and specifications are met with state-of-the-art area occupation and power consumption. The last part of the thesis deals with the design of a transmission mixer and a power amplifier for MB-OFDM UWB band group 1. The design has been carried on up to layout level in ST Microlectronics 65nm CMOS technology. Main characteristics of the systems are the wideband behavior (1.6 GHz of bandwidth) and the constant behavior over process parameters, temperature and supply voltage thanks to the design of dedicated adaptive biasing circuits.

Fully Connected PLL Networks: How Filter Determines the Number of Nodes

Synchronization plays an important role in telecommunication systems, integrated circuits, and automation systems. Formerly, the masterslave synchronization strategy was used in the great majority of cases due to its reliability and simplicity. Recently, with the wireless networks development, and with the increase of the operation frequency of integrated circuits, the decentralized clock distribution strategies are gaining importance. Consequently, fully connected clock distribution systems with nodes composed of phase-locked loops (PLLs) appear as a convenient engineering solution. In this work, the stability of the synchronous state of these networks is studied in two relevant situations: when the node filters are first-order lag-lead low-pass or when the node filters are second-order low-pass. For first-order filters, the synchronous state of the network shows to be stable for any number of nodes. For second-order filter, there is a superior limit for the number of nodes, depending on the PLL parameters. Copyright (C) 2009 Atila Madureira Bueno et al.

Multiple synchronous states in static delay-free mutually connected PLL networks

In many engineering applications, the time coordination of geographically separated events is of fundamental importance, as in digital telecommunications and integrated digital circuits. Mutually connected (MC) networks are very good candidates for some new types of application, such as wireless sensor networks. This paper presents a study on the behavior of MC networks of digital phase-locked loops (DPLLs). Analytical results are derived showing that, even for static networks without delays, different synchronous states may exist for the network. An upper bound for the number of such states is also presented. Numerical simulations are used to show the following results: (i) the synchronization precision in MC DPLLs networks; (ii) the existence of synchronous states for the network does not guarantee its achievement and (iii) different synchronous states may be achieved for different initial conditions. These results are important in the neural computation context. as in this case, each synchronous state may be associated to a different analog memory information. (C) 2010 Elsevier B.V. All rights reserved.

Adaptive frequency tracking of the baseline ECG identifies the site of atrial fibrillation termination by catheter ablation

Multiple organization indices have been used to predict the outcome of stepwise catheter ablation in long-standing persistent atrial fibrillation (AF), however with limited success. Our study aims at developinginnovative organization indices from baseline ECG (i.e. during the procedure, before ablation) in orderto identify the site of AF termination by catheter ablation. Seventeen consecutive male patients (age60 ± 5 years, AF duration 7 ± 5 years) underwent a stepwise catheter ablation. Chest lead V6 was placedin the back (V6b). QRST cancelation was performed from chest leads V1 to V6b. Using an innovativeadaptive harmonic frequency tracking, two measures of AF organization were computed to quantify theharmonics components of ECG activity: (1) the adaptive phase difference variance (APD) between theAF harmonic components as a measure of AF regularity, and (2) and adaptive organization index (AOI)evaluating the cyclicity of the AF oscillations. Both adaptive indices were compared to indices computedusing a time-invariant approach: (1) ECG AF cycle length (AFCL), (2) the spectrum based organizationindex (OI), and (3) the time-invariant phase difference TIPD. Long-standing persistent AF was terminatedinto sinus rhythm or atrial tachycardia in 13/17 patients during stepwise ablation, 11 during left atriumablation (left terminated patients - LT), 2 during the right atrium ablation (right terminated patients -RT), and 4 were non terminated (NT) and required electrical cardioversion. Our findings showed that LTpatients were best separated from RT/NT before ablation by the duration of sustained AF and by AOI onchest lead V1 and APD from the dorsal lead V6b as compared to ECG AFCL, OI and TIPD, respectively. Ourresults suggest that adaptive measures of AF organization computed before ablation perform better thantime-invariant based indices for identifying patients whose AF will terminate during ablation within theleft atrium. These findings are indicative of a higher baseline organization in these patients that could beused to select candidates for the termination of AF by stepwise catheter ablation.© 2013 Elsevier Ltd. All rights reserved.

Architectures, stability and optimization for clock distribution networks

Synchronous telecommunication networks, distributed control systems and integrated circuits have its accuracy of operation dependent on the existence of a reliable time basis signal extracted from the line data stream and acquirable to each node. In this sense, the existence of a sub-network (inside the main network) dedicated to the distribution of the clock signals is crucially important. There are different solutions for the architecture of the time distribution sub-network and choosing one of them depends on cost, precision, reliability and operational security. In this work we expose: (i) the possible time distribution networks and their usual topologies and arrangements. (ii) How parameters of the network nodes can affect the reachability and stability of the synchronous state of a network. (iii) Optimizations methods for synchronous networks which can provide low cost architectures with operational precision, reliability and security. (C) 2011 Elsevier B. V. All rights reserved.