Variable-speed wind power generation using doubly fed wound rotor induction machine - A comparison with alternative schemes

In this paper, a wind energy conversion system (WECS) using grid-connected wound rotor induction machine controlled from the rotor side is compared with both fixed speed and variable speed systems using cage rotor induction machine. The comparison is done on the basis of (I) major hardware components required, (II) operating region, and (III) energy output due to a defined wind function using the characteristics of a practical wind turbine. Although a fixed speed system is more simple and reliable, it severely limits the energy output of a wind turbine. In case of variable speed systems, comparison shows that using a wound rotor induction machine of similar rating can significantly enhance energy capture. This comes about due to the ability to operate with rated torque even at supersynchronous speeds; power is then generated out of the rotor as well as the stator. Moreover, with rotor side control, the voltage rating of the power devices and dc bus capacitor bank is reduced. The size of the line side inductor also decreasesd. Results are presented to show the substantial advantages of the doubly fed system.

An asymmetric cascaded H-Bridge inverters for generating 12-sided polygonal space vector diagrams for Motor drives

A new topology of asymmetric cascaded H-Bridge inverter is presented in this paper It consists of two cascaded H-bridge cells per phase. They are fed from isolated dc sources having a dc bus ratio of 1:0.366. Out of many space vectors possible from this circuit, only those are chosen that lie on 12-sided polygons. Thus, the overall space vector diagram produced by this circuit consists of multiple numbers of 12-sided polygons. With a proper PWM timing calculations based on these selected space vectors, it is possible to eliminate all the 6n +/- 1, (n = odd) harmonics from the phase voltage under all operating conditions. The switching frequency of individual H-Bridge cells is also substantially low. Extensive experimental results have been presented in this paper to validate the proposed concept.

Digital Dead Time Logic and Protection Circuitry for PWM Voltage Source Converters

Power semiconductor devices have finite turn on and turn off delays that may not be perfectly matched. In a leg of a voltage source converter, the simultaneous turn on of one device and the turn off of the complementary device will cause a DC bus shoot through, if the turn off delay is larger than the turn on delay time. To avoid this situation it is common practice to blank the two complementary devices in a leg for a small duration of time while switching, which is called dead time. This paper proposes a logic circuit for digital implementation required to control the complementary devices of a leg independently and at the same time preventing cross conduction of devices in a leg, and while providing accurate and stable dead time. This implementation is based on the concept of finite state machines. This circuit can also block improper PWM pulses to semiconductor switches and filters small pulses notches below a threshold time width as the narrow pulses do not provide any significant contribution to average pole voltage, but leads to increased switching loss. This proposed dead time logic has been implemented in a CPLD and is implemented in a protection and delay card for 3- power converters.

Multilevel dodecagonal space-vector generation for induction motor drives by cascading three-level and two-level inverters

This study proposes an inverter circuit topology capable of generating multilevel dodecagonal (12-sided polygon) voltage space vectors by the cascaded connection of two-level and three-level inverters. By the proper selection of DC-link voltages and resultant switching states for the inverters, voltage space vectors whose tips lie on three concentric dodecagons, are obtained. A rectifier circuit for the inverter is also proposed, which significantly improves the power factor. The topology offers advantages such as the complete elimination of the fifth and seventh harmonics in phase voltages and an extension of the linear modulation range. In this study, a simple method for the calculation of pulse width modulation timing was presented along with extensive simulation and experimental results in order to validate the proposed concept.

Medium Voltage Drive for Induction Motors Using Multilevel Octadecagonal Voltage Space Vectors

Multilevel inverters with hexagonal and dodecagonal voltage space vector structures have improved harmonic profile compared to two-level inverters. Further improvement in the quality of the waveform is possible using multilevel octadecagonal (18-sided polygon) voltage space vectors. This paper proposes an inverter circuit topology capable of generating multilevel octadecagonal voltage space vectors, by cascading two asymmetric three-level inverters. By the proper selection of dc-link voltages and the resultant switching states for the inverters, voltage space vectors, whose tips lie on three concentric octadecagons, are obtained. The advantages of octadecagonal voltage space vector-based pulsewidth modulation (PWM) techniques are the complete elimination of fifth, seventh, eleventh, and thirteenth harmonics in phase voltages and the extension of linear modulation range. In this paper, a simple PWM timing calculation method is also proposed. Experimental results have been presented in this paper to validate the proposed concept.

Multilevel octadecagonal space vector generation for induction motor drives by cascading asymmetric three level inverters

Multilevel inverters with hexagonal and dodecagonal voltage space vector structures have improved harmonic profile compared to two level inverters. Further improvement in the quality of the waveform is possible using multilevel octadecagonal (18 sided polygon) voltage space vectors. This paper proposes an inverter circuit topology capable of generating multilevel octadecagonal voltage space vectors, by cascading two asymmetric three level inverters. By proper selection of DC link voltages and the resultant switching states for the inverters, voltage space vectors, whose tips lie on three concentric octadecagons, are obtained. The advantages of octadecagonal voltage space vector based PWM techniques are the complete elimination of fifth, seventh, eleventh and thirteenth harmonics in phase voltages and the extension of linear modulation range. In this paper, a simple PWM timing calculation method is also proposed. Matlab simulation results and experimental results have been presented in this paper to validate the proposed concept.

Filter Configuration and PWM Method For Single Phase Inverters with Reduced Conducted EMI Noise

Electromagnetic Interference (EMI) noise is one of the major issues during the design of the grid-tied power converters. Presence of high dv/dt in Common Mode (CM) voltage, excites the parasitic capacitances and causes injection of narrow peaky current to ground. This results in high EMI noise level. A topology consisting of a single phase PWM-rectifier with LCL filter, utilising bipolar PWM method is proposed which reduces the EMI noise level by more than 30dB. This filter topology is shown to be insensitive to the switching delays between the legs of the inverter. The proposed topology eliminates high dv/dt from the dc-bus CM voltage by making it sinusoidal. Hence, the high frequency CM current injection to ground is minimized.

Experimental Study on Switching Characteristics of an Inverter Leg Consisting of IGBTs of Dissimilar Makes

Usually the top and bottom IGBT devices in an inverter leg are of the same make (i.e. from same manufacturer). At low power level, these two devices even may be contained in the same module. However at high power levels the top and bottom devices are in separate modules. Sometimes, in the event of device failure, device of particular make may be replaced by one of another make, but of same ratings (on account of non-availability of the original make). This paper investigates the effect of such intermixing of two different makes of high power IGBTs in an inverter leg on the switching characteristics. The switching transitions between IGBT and diode of similar make and those of IGBT and diode of dissimilar make are compared experimentally at various DC link voltages and currents. The comparisons are made in terms of, IGBT peak turn-on di/dt, IGBT peak turn-off di/dt, peak diode reverse recovery current (I-rr), peak IGBT voltage overshoot and switching energy losses.

Study of Multilevel Sinusoidal PWM methods for Cascaded H-Bridge Multilevel Inverters

This paper is a study of Multilevel Sinusoidal Pulse Width Modulation (MSPWM) methods; Phase Disposition (PD), Alternate Phase Opposition Disposition (APOD), Phase Opposition Disposition (POD) on a single phase Cascaded H-Bridge Multilevel inverter. Various factors such as amplitude modulation index (Ma), frequency modulation index (M-f), phase angle between carrier and reference modulating wave (phi) have been considered for simulation. Variation in these factors and their effect on inverter performance is evaluated. Factors such as DC bus utilization, output r.m.s voltage, total harmonic distortion (%THD), dominant harmonic order, switching losses are evaluated based on simulation results.

Filter Configuration and PWM Method For Single-Phase Inverters With Reduced Conducted EMI Noise

Electromagnetic interference (EMI) noise is one of the major issues during design of grid-tied power converters. A novel LCL filter topology for a single-phase pulsewidth modulation (PWM) rectifier that makes use of bipolar PWM method is proposed for a single-phase to three-phase motor drive power converter. The proposed topology eliminates high dv/dt from the dc-bus common-mode (CM) voltage by making it sinusoidal. Hence, the high-frequency CM current injection to the ground and the motor-side CM current are minimized. The proposed filter configuration makes the system insensitive to circuit non-idealities such as mismatch in inductors values, unequal turn-on and turn-off delays, and dead-time mismatch between the inverter legs. Different variants of the filter topology are compared to establish the effectiveness of the proposed circuit. Experimental results based on the EMI measurement on the grid side and the CM current measurement on the motor side are presented for a 5-kW motor drive. It is shown that the proposed filter topology reduces the EMI noise level by about 35 dB.

An Open-End winding IM drive with Multilevel 12-sided Polygonal Vectors with Symmetric Triangles

Multilevel inverters with hexagonal voltage space vector structures have improved performance of induction motor drives compared to that of the two level inverters. Further reduction in the torque ripple on the motor shaft is possible by using multilevel dodecagonal (12-sided polygon) voltage space vector structures. The advantages of dodecagonal voltage space vector based PWM techniques are the complete elimination of fifth and seventh harmonics in phase voltages for the full modulation range and the extension of linear modulation range. This paper proposes an inverter circuit topology capable of generating multilevel dodecagonal voltage space vectors with symmetric triangles, by cascading two asymmetric three level inverters with isolated H-Bridges. This is made possible by proper selection of DC link voltages and the selection of resultant switching states for the inverters. In this paper, a simple PWM timing calculation method is proposed. Experimental results have also been presented in this paper to validate the proposed concept.

A Voltage Space Vector Diagram Formed by Nineteen Concentric Dodecagons for Medium-Voltage Induction Motor Drive

In this paper, a multilevel dodecagonal voltage space vector structure with nineteen concentric dodecagons is proposed for the first time. This space vector structure is achieved by cascading two sets of asymmetric three-level inverters with isolated H-bridges on either side of an open-end winding induction motor. The dodecagonal structure is made possible by proper selection of dc link voltages and switching states of the inverters. The proposed scheme retains all the advantages of multilevel topologies as well as the advantages of dodecagonal voltage space vector structure. In addition to that, a generic and simple method for calculation of pulsewidth modulation timings using only sampled reference values (v(alpha) and v(beta)) is proposed. This enables the scheme to be used for any closed-loop application such as vector control. In addition, a new method of switching technique is proposed, which ensures minimum switching while eliminating the fifth-and seventh-order harmonics and suppressing the eleventh and thirteenth harmonics, eliminating the need for bulky filters. The motor phase voltage is a 24-stepped wave-form for the entire modulation range thereby reducing the number of switchings of the individual inverter modules. Experimental results for steady-state operation, transient operation, including start-up have been presented and the results of fast Fourier transform analysis is also presented for validating the proposed concept.

A controller design method for 3 phase 4 wire grid connected VSI with LCL filter

Closed loop control of a grid connected VSI requires line current control and dc bus voltage control. The closed loop system comprising PR current controller and grid connected VSI with LCL filter is a higher order system. Closed loop control gain expressions are therefore difficult to obtain directly for such systems. In this work a simplified approach has been adopted to find current and voltage controller gain expressions for a 3 phase 4 wire grid connected VSI with LCL filter. The closed loop system considered here utilises PR current controller in natural reference frame and PI controller for dc bus voltage control. Asymptotic frequency response plot and gain bandwidth requirements of the system have been used for current control and voltage controller design. A simplified lower order model, derived for closed loop current control, is used for the dc bus voltage controller design. The adopted design method has been verified through experiments by comparison of the time domain response.

Analysis of sine-triangle and zero-sequence injection modulation schemes for split-phase induction motor drive

A split-phase induction motor is fed from two three-phase voltage source inverters for speed control. This study analyses carrier-comparison based pulse width modulation (PWM) schemes for a split-phase motor drive, from a space-vector perspective. Sine-triangle PWM, one zero-sequence injection PWM where the same zero-sequence signal is used for both the inverters, and another zero-sequence injection PWM where different zero-sequence signals are employed for the two inverters are considered. The set of voltage vectors applied, the sequence in which the voltage vectors are applied, and the resulting current ripple vector are analysed for all the PWM methods. Besides all the PWM methods are compared in terms of dc bus utilisation. For the same three-phase sine reference, the PWM method with different zero-sequence signals for the two inverters is found to employ a set of vectors different from the other methods. Both analysis and experimental results show that this method results in lower total harmonic distortion and higher dc bus utilisation than the other two PWM methods.

Gate commutated thyristor with voltage independent maximum controllable current

In this letter, we use a novel 3-D model, earlier calibrated with experimental results on standard gate commutated thyristors (GCTs), with the aim to explain the physics behind the high-power technology (HPT) GCT, to investigate what impact this design would have on 24 mm diameter GCTs, and to clarify the mechanisms that limit safe switching at different dc-link voltages. The 3-D simulation results show that the HPT design can increase the maximum controllable current in 24 mm diameter devices beyond the realm of GCT switching, known as the hard-drive limit. It is proposed that the maximum controllable current becomes independent of the dc-link voltage for the complete range of operating voltage. © 1980-2012 IEEE.