Readout schemes for low noise single-photon avalanche diodes fabricated in conventional HV-CMOS technologies

Three different pixels based on single-photon avalanche diodes for triggered applications, such as fluorescence lifetime measurements and high energy physics experiments, are presented. Each pixel consists of a 20µm x 100µm (width x length) single photon avalanche diode and a monolithically integrated readout circuit. The sensors are operated in the gated mode of acquisition to reduce the probability to detect noise counts interferring with real radiation events. Each pixel includes a different readout circuit that allows to use low reverse bias overvoltages. Experimental results demonstrate that the three pixels present a similar behaviour. The pixels get rid of afterpulses and present a reduced dark count probability by applying the gated operation. Noise figures are further improved by using low reverse bias overvoltages. The detectors exhibit an input dynamic range of 13.35 bits with short gated"on" periods of 10ns and a reverse bias overvoltage of 0.5V. The three pixels have been fabricated in a standard HV-CMOS process.

Readout electronics for low dark count pixel detectors based on geiger mode avalanche photodiodes fabricated in conventional CMOS technologies for future linear colliders

The high sensitivity and excellent timing accuracy of Geiger mode avalanche photodiodes makes them ideal sensors as pixel detectors for particle tracking in high energy physics experiments to be performed in future linear colliders. Nevertheless, it is well known that these sensors suffer from dark counts and afterpulsing noise, which induce false hits (indistinguishable from event detection) as well as an increase of the necessary area of the readout system. In this work, we present a comparison between APDs fabricated in a high voltage 0.35 µm and a high integration 0.13 µm commercially available CMOS technologies that has been performed to determine which of them best fits the particle collider requirements. In addition, a readout circuit that allows low noise operation is introduced. Experimental characterization of the proposed pixel is also presented in this work.

Field-Programmable Gate Array Card for Readout and Control of Cryoelectronics

The main goal of the present Master’s Thesis project was to create a field-programmable gate array (FPGA) based system for the control of single-electron transistors or other cryoelectronic devices. The FPGA and similar technologies are studied in the present work. The fixed and programmable logic are compared with each other. The main features and limitations of the hardware used in the project are investigated. The hardware and software connections of the device to the computer are shown in detail. The software development techniques for FPGA-based design are described. The steps of design for programmable logic are considered. Furthermore, the results of filters implemented in the software are illustrated.

Readout Electronics for Gas Electron Multiplier Detectors

The European Organization for Nuclear Research (CERN) operates the largest particle collider in the world. This particle collider is called the Large Hadron Collider (LHC) and it will undergo a maintenance break sometime in 2017 or 2018. During the break, the particle detectors, which operate around the particle collider, will be serviced and upgraded. Following the improvement in performance of the particle collider, the requirements for the detector electronics will be more demanding. In particular, the high amount of radiation during the operation of the particle collider sets requirements for the electronics that are uncommon in commercial electronics. Electronics that are built to function in the challenging environment of the collider have been designed at CERN. In order to meet the future challenges of data transmission, a GigaBit Transceiver data transmission module and an E-Link data bus have been developed. The next generation of readout electronics is designed to benefit from these technologies. However, the current readout electronics chips are not compatible with these technologies. As a result, in addition to new Gas Electron Multiplier (GEM) detectors and other technology, a new compatible chip is developed to function within the GEMs for the Compact Muon Solenoid (CMS) project. In this thesis, the objective was to study a data transmission interface that will be located on the readout chip between the E-Link bus and the control logic of the chip. The function of the module is to handle data transmission between the chip and the E-Link. In the study, a model of the interface was implemented with the Verilog hardware description language. This process was simulated by using chip design software by Cadence. State machines and operating principles with alternative possibilities for implementation are introduced in the E-Link interface design procedure. The functionality of the designed logic is demonstrated in simulation results, in which the implemented model is proven to be suitable for its task. Finally, suggestions that should be considered for improving the design have been presented.

Potential and Challenges of Analog Reconfigurable Computation in Modern and Future CMOS

In this work, the feasibility of the floating-gate technology in analog computing platforms in a scaled down general-purpose CMOS technology is considered. When the technology is scaled down the performance of analog circuits tends to get worse because the process parameters are optimized for digital transistors and the scaling involves the reduction of supply voltages. Generally, the challenge in analog circuit design is that all salient design metrics such as power, area, bandwidth and accuracy are interrelated. Furthermore, poor flexibility, i.e. lack of reconfigurability, the reuse of IP etc., can be considered the most severe weakness of analog hardware. On this account, digital calibration schemes are often required for improved performance or yield enhancement, whereas high flexibility/reconfigurability can not be easily achieved. Here, it is discussed whether it is possible to work around these obstacles by using floating-gate transistors (FGTs), and analyze problems associated with the practical implementation. FGT technology is attractive because it is electrically programmable and also features a charge-based built-in non-volatile memory. Apart from being ideal for canceling the circuit non-idealities due to process variations, the FGTs can also be used as computational or adaptive elements in analog circuits. The nominal gate oxide thickness in the deep sub-micron (DSM) processes is too thin to support robust charge retention and consequently the FGT becomes leaky. In principle, non-leaky FGTs can be implemented in a scaled down process without any special masks by using “double”-oxide transistors intended for providing devices that operate with higher supply voltages than general purpose devices. However, in practice the technology scaling poses several challenges which are addressed in this thesis. To provide a sufficiently wide-ranging survey, six prototype chips with varying complexity were implemented in four different DSM process nodes and investigated from this perspective. The focus is on non-leaky FGTs, but the presented autozeroing floating-gate amplifier (AFGA) demonstrates that leaky FGTs may also find a use. The simplest test structures contain only a few transistors, whereas the most complex experimental chip is an implementation of a spiking neural network (SNN) which comprises thousands of active and passive devices. More precisely, it is a fully connected (256 FGT synapses) two-layer spiking neural network (SNN), where the adaptive properties of FGT are taken advantage of. A compact realization of Spike Timing Dependent Plasticity (STDP) within the SNN is one of the key contributions of this thesis. Finally, the considerations in this thesis extend beyond CMOS to emerging nanodevices. To this end, one promising emerging nanoscale circuit element - memristor - is reviewed and its applicability for analog processing is considered. Furthermore, it is discussed how the FGT technology can be used to prototype computation paradigms compatible with these emerging two-terminal nanoscale devices in a mature and widely available CMOS technology.

Modeling Front End Electronics for a Gas Electron Multiplier Detector

The Large Hadron Collider (LHC) in The European Organization for Nuclear Research (CERN) will have a Long Shutdown sometime during 2017 or 2018. During this time there will be maintenance and a possibility to install new detectors. After the shutdown the LHC will have a higher luminosity. A promising new type of detector for this high luminosity phase is a Triple-GEM detector. During the shutdown these detectors will be installed at the Compact Muon Solenoid (CMS) experiment. The Triple-GEM detectors are now being developed at CERN and alongside also a readout ASIC chip for the detector. In this thesis a simulation model was developed for the ASICs analog front end. The model will help to carry out more extensive simulations and also simulate the whole chip before the whole design is finished. The proper functioning of the model was tested with simulations, which are also presented in the thesis.

Readout architectures for hybrid pixel detector readout chips

The original contribution of this thesis to knowledge are novel digital readout architectures for hybrid pixel readout chips. The thesis presents asynchronous bus-based architecture, a data-node based column architecture and a network-based pixel matrix architecture for data transportation. It is shown that the data-node architecture achieves readout efficiency 99% with half the output rate as a bus-based system. The network-based solution avoids “broken” columns due to some manufacturing errors, and it distributes internal data traffic more evenly across the pixel matrix than column-based architectures. An improvement of > 10% to the efficiency is achieved with uniform and non-uniform hit occupancies. Architectural design has been done using transaction level modeling (TLM) and sequential high-level design techniques for reducing the design and simulation time. It has been possible to simulate tens of column and full chip architectures using the high-level techniques. A decrease of > 10 in run-time is observed using these techniques compared to register transfer level (RTL) design technique. Reduction of 50% for lines-of-code (LoC) for the high-level models compared to the RTL description has been achieved. Two architectures are then demonstrated in two hybrid pixel readout chips. The first chip, Timepix3 has been designed for the Medipix3 collaboration. According to the measurements, it consumes < 1 W/cm^2. It also delivers up to 40 Mhits/s/cm^2 with 10-bit time-over-threshold (ToT) and 18-bit time-of-arrival (ToA) of 1.5625 ns. The chip uses a token-arbitrated, asynchronous two-phase handshake column bus for internal data transfer. It has also been successfully used in a multi-chip particle tracking telescope. The second chip, VeloPix, is a readout chip being designed for the upgrade of Vertex Locator (VELO) of the LHCb experiment at CERN. Based on the simulations, it consumes < 1.5 W/cm^2 while delivering up to 320 Mpackets/s/cm^2, each packet containing up to 8 pixels. VeloPix uses a node-based data fabric for achieving throughput of 13.3 Mpackets/s from the column to the EoC. By combining Monte Carlo physics data with high-level simulations, it has been demonstrated that the architecture meets requirements of the VELO (260 Mpackets/s/cm^2 with efficiency of 99%).

Synthetic studies on prostaglandins: "synthesis of a new thia-PGEI analog"

A PGE1 analog, namely (±)-trans-2-(6'-carbomethoxyhexyl)-3- (E-3"-thia-1 "-octene)-4-hydroxycyclopentanone 71, has been prepared for the first time. Towards the synthesis of this compound, several synthetic approaches aimed at the preparation of the required acetylenic and E-halovinylic sulfides as building blocks were investigated. Among all the methods examined, it appeared evident that the best route to ethynyl n.pentyl sulfide 81 is via a double dehydrohalogenation of the corresponding 1,2-dibromoethyl sulfide with sodium amide in liquid ammonia. In addition, the isomerically pure E-2-iodoethenyl n.pentyl sulfide 85 is conveniently prepared in high yield and stereoselectivity by hydrozirconation-iodination of the terminal ethynyl sulfide 81. The classical hydroalumination and hydroboration reactions for the preparation of vinyl halides from alkynes gave only small yields when applied as methods towards the synthesis of 85 . The building block 2-(6'-carbomethoxyhexyl)-4-hydroxy-2- cyclopentenone (±)-1 carrying the upper side-chain of prostaglandin E 1 was prepared by a step-wise synthesis involving transformations of compounds possessing the required carbocyclic framework (see scheme 27). The synthesis proved to be convenient and gave a good overall yield of (±)-1 which was protected as the TH P-derivative 37 or the siloxy derivative 38. With the required building blocks 81 and 37 in hand, the target 1S-thia-PGE1 analog (±)-71 was prepared via the in situ higher cuprate formation-conjugate addition reaction. This method proved to be convenient and stereospecific. The standard cuprate method, involving an organocuprate reagent generated from an isolated vinyl iodide, did not work well in our case and gave a complicated mixture of products. The target compound will be submitted for assessment of bio log ical activity.

??Juegue con sus hijos! : adivinanzas, acertijos, analog??as, problemas de l??gica, m??mica, creatividad, juegos de palabras y muchos m??s entrenamientos para divertir y educar a los ni??os

Repertorio de juegos dirigidos a padres y educadores para conseguir una estimulaci??n intelectual, ling????stica y creativa en ni??os con dificultades en el desarrollo. Se incluyen las tipolog??as siguientes: juegos de l??gica, juegos de creatividad, juegos con cuentos, juegos de matem??ticas, juegos de conocimientos, juegos de sociabilidad, m??mica y simb??licos, juegos de transformaciones y ordenaciones, juegos de memoria, juegos de vocabulario, juegos de pronunciaci??n, fluidez, morfolog??a y sintaxis, juegos metaling????sticos, juegos para el desarrollo ??tico y moral. Adjunta un anexo sobre la manera de hablar de los ni??os y recomendaciones de lo que no se debe hacer a la hora de educar a un ni??o desde la m??s temprana edad.

Case based reasoning as an extension of fault dictionary methods for linear electronic analog circuits diagnosis

El test de circuits és una fase del procés de producció que cada vegada pren més importància quan es desenvolupa un nou producte. Les tècniques de test i diagnosi per a circuits digitals han estat desenvolupades i automatitzades amb èxit, mentre que aquest no és encara el cas dels circuits analògics. D'entre tots els mètodes proposats per diagnosticar circuits analògics els més utilitzats són els diccionaris de falles. En aquesta tesi se'n descriuen alguns, tot analitzant-ne els seus avantatges i inconvenients. Durant aquests últims anys, les tècniques d'Intel·ligència Artificial han esdevingut un dels camps de recerca més importants per a la diagnosi de falles. Aquesta tesi desenvolupa dues d'aquestes tècniques per tal de cobrir algunes de les mancances que presenten els diccionaris de falles. La primera proposta es basa en construir un sistema fuzzy com a eina per identificar. Els resultats obtinguts son força bons, ja que s'aconsegueix localitzar la falla en un elevat tant percent dels casos. Per altra banda, el percentatge d'encerts no és prou bo quan a més a més s'intenta esbrinar la desviació. Com que els diccionaris de falles es poden veure com una aproximació simplificada al Raonament Basat en Casos (CBR), la segona proposta fa una extensió dels diccionaris de falles cap a un sistema CBR. El propòsit no és donar una solució general del problema sinó contribuir amb una nova metodologia. Aquesta consisteix en millorar la diagnosis dels diccionaris de falles mitjançant l'addició i l'adaptació dels nous casos per tal d'esdevenir un sistema de Raonament Basat en Casos. Es descriu l'estructura de la base de casos així com les tasques d'extracció, de reutilització, de revisió i de retenció, fent èmfasi al procés d'aprenentatge. En el transcurs del text s'utilitzen diversos circuits per mostrar exemples dels mètodes de test descrits, però en particular el filtre biquadràtic és l'utilitzat per provar les metodologies plantejades, ja que és un dels benchmarks proposats en el context dels circuits analògics. Les falles considerades son paramètriques, permanents, independents i simples, encara que la metodologia pot ser fàcilment extrapolable per a la diagnosi de falles múltiples i catastròfiques. El mètode es centra en el test dels components passius, encara que també es podria extendre per a falles en els actius.

What is the function of nail biting: an analog assessment study

Objective: To compare the frequency of nail biting in 4 settings (interventions) designed to elicit the functions of nail biting and to compare the results with a self-report questionnaire about the functions of nail biting. Design: Randomised allocation of participants to order of conditions. Setting: University Psychology Department. Subjects: Forty undergraduates who reported biting their nails. Interventions: Left alone (boredom), solving maths problems (frustration), reprimanded for nail biting (contingent attention), continuous conversation (noncontingent attention). Main Outcome measures: Number of times the undergraduates bit their nails. Results: Nail biting occurred most often in two conditions, boredom and frustration. Conclusion: Nail biting in young adults occurs as a result of boredom or working on difficult problems, which may reflect a particular emotional state. It occurs least often when people are engaged in social interaction or when they are reprimanded for the behavior. (c) 2006 Elsevier Ltd. All rights reserved.