Bericht über die Reise nach Nkónya und Boëm vom 4. Januar bis 4. Februar 1887

von Peter Hall

Berlin, Germany, 1748 (Image 1 of 4) (Raster Image)

This layer is a georeferenced raster image of the historic paper map entitled: Plan de la ville de Berlin : levé et dessiné par ordre et privilege privatif du Roy sous la direction du Marchall Comte de Schmettau, par Hildner approuvé par l'Academie Royale de Science â Berlin ; gravé sous la direction de G.F. Schmidt Graveur du Roy. It was published by l'Academie Royale de Science â Berlin in 1748. Scale [ca. 1:6,500]. Covers Berlin, Germany. This layer is image 1 of 4 total images of the four sheet source map, representing the northeast portion of the map. Map in French and German.The image inside the map neatline is georeferenced to the surface of the earth and fit to the Deutsches Hauptdreiecksnetz (DHDN) 3-degree Gauss-Kruger Zone 4 coordinate system. All map collar and inset information is also available as part of the raster image, including any inset maps, profiles, statistical tables, directories, text, illustrations, index maps, legends, or other information associated with the principal map. This map shows features such as roads, drainage, built-up areas and selected buildings, fortification, parks, cemeteries, ground cover, and more. Relief shown by hachures. Includes also view and inset engravings: Prospect du Stadt Berlin von Süden gegen Norden -- 1. Prospect des grossen Platzes von Opera Hausse 2. der Cathol. Kirche St. Hedwig 3. und einer Seite des Marggraff Henrich. Pallais -- Prospect der Neuen Schloss u Dohm Kirche -- Prospect des Neuen Königl. Printz Heinrich. Pallais den Opern Hausse gegen über.This layer is part of a selection of digitally scanned and georeferenced historic maps from the Harvard Map Collection. These maps typically portray both natural and manmade features. The selection represents a range of originators, ground condition dates, scales, and map purposes.

Berlin, Germany, 1748 (Image 2 of 4) (Raster Image)

This layer is a georeferenced raster image of the historic paper map entitled: Plan de la ville de Berlin : levé et dessiné par ordre et privilege privatif du Roy sous la direction du Marchall Comte de Schmettau, par Hildner approuvé par l'Academie Royale de Science â Berlin ; gravé sous la direction de G.F. Schmidt Graveur du Roy. It was published by l'Academie Royale de Science â Berlin in 1748. Scale [ca. 1:6,500]. Covers Berlin, Germany. This layer is image 2 of 4 total images of the four sheet source map, representing the southeast portion of the map. Map in French and German.The image inside the map neatline is georeferenced to the surface of the earth and fit to the Deutsches Hauptdreiecksnetz (DHDN) 3-degree Gauss-Kruger Zone 4 coordinate system. All map collar and inset information is also available as part of the raster image, including any inset maps, profiles, statistical tables, directories, text, illustrations, index maps, legends, or other information associated with the principal map. This map shows features such as roads, drainage, built-up areas and selected buildings, fortification, parks, cemeteries, ground cover, and more. Relief shown by hachures. Includes also view and inset engravings: Prospect du Stadt Berlin von Süden gegen Norden -- 1. Prospect des grossen Platzes von Opera Hausse 2. der Cathol. Kirche St. Hedwig 3. und einer Seite des Marggraff Henrich. Pallais -- Prospect der Neuen Schloss u Dohm Kirche -- Prospect des Neuen Königl. Printz Heinrich. Pallais den Opern Hausse gegen über.This layer is part of a selection of digitally scanned and georeferenced historic maps from the Harvard Map Collection. These maps typically portray both natural and manmade features. The selection represents a range of originators, ground condition dates, scales, and map purposes.

Berlin, Germany, 1748 (Image 3 of 4) (Raster Image)

This layer is a georeferenced raster image of the historic paper map entitled: Plan de la ville de Berlin : levé et dessiné par ordre et privilege privatif du Roy sous la direction du Marchall Comte de Schmettau, par Hildner approuvé par l'Academie Royale de Science â Berlin ; gravé sous la direction de G.F. Schmidt Graveur du Roy. It was published by l'Academie Royale de Science â Berlin in 1748. Scale [ca. 1:6,500]. Covers Berlin, Germany. This layer is image 3 of 4 total images of the four sheet source map, representing the northwest portion of the map. Map in French and German.The image inside the map neatline is georeferenced to the surface of the earth and fit to the Deutsches Hauptdreiecksnetz (DHDN) 3-degree Gauss-Kruger Zone 4 coordinate system. All map collar and inset information is also available as part of the raster image, including any inset maps, profiles, statistical tables, directories, text, illustrations, index maps, legends, or other information associated with the principal map. This map shows features such as roads, drainage, built-up areas and selected buildings, fortification, parks, cemeteries, ground cover, and more. Relief shown by hachures. Includes also view and inset engravings: Prospect du Stadt Berlin von Süden gegen Norden -- 1. Prospect des grossen Platzes von Opera Hausse 2. der Cathol. Kirche St. Hedwig 3. und einer Seite des Marggraff Henrich. Pallais -- Prospect der Neuen Schloss u Dohm Kirche -- Prospect des Neuen Königl. Printz Heinrich. Pallais den Opern Hausse gegen über.This layer is part of a selection of digitally scanned and georeferenced historic maps from the Harvard Map Collection. These maps typically portray both natural and manmade features. The selection represents a range of originators, ground condition dates, scales, and map purposes.

Berlin, Germany, 1748 (Image 4 of 4) (Raster Image)

This layer is a georeferenced raster image of the historic paper map entitled: Plan de la ville de Berlin : levé et dessiné par ordre et privilege privatif du Roy sous la direction du Marchall Comte de Schmettau, par Hildner approuvé par l'Academie Royale de Science â Berlin ; gravé sous la direction de G.F. Schmidt Graveur du Roy. It was published by l'Academie Royale de Science â Berlin in 1748. Scale [ca. 1:6,500]. Covers Berlin, Germany. This layer is image 4 of 4 total images of the four sheet source map, representing the southwest portion of the map. Map in French and German.The image inside the map neatline is georeferenced to the surface of the earth and fit to the Deutsches Hauptdreiecksnetz (DHDN) 3-degree Gauss-Kruger Zone 4 coordinate system. All map collar and inset information is also available as part of the raster image, including any inset maps, profiles, statistical tables, directories, text, illustrations, index maps, legends, or other information associated with the principal map. This map shows features such as roads, drainage, built-up areas and selected buildings, fortification, parks, cemeteries, ground cover, and more. Relief shown by hachures. Includes also view and inset engravings: Prospect du Stadt Berlin von Süden gegen Norden -- 1. Prospect des grossen Platzes von Opera Hausse 2. der Cathol. Kirche St. Hedwig 3. und einer Seite des Marggraff Henrich. Pallais -- Prospect der Neuen Schloss u Dohm Kirche -- Prospect des Neuen Königl. Printz Heinrich. Pallais den Opern Hausse gegen über.This layer is part of a selection of digitally scanned and georeferenced historic maps from the Harvard Map Collection. These maps typically portray both natural and manmade features. The selection represents a range of originators, ground condition dates, scales, and map purposes.

System der volkswirthschaft; ein hand- und lesebuch für geschäftsmänner und studierende,

Each vol. has also special t.-p.

Packing lambda-fold complete multipartite graphs with 4-cycles

A maximum packing of any lambda-fold complete multipartite graph (where there are lambda edges between any two vertices in different parts) with edge-disjoint 4- cycles is obtained and the size of each minimum leave is given. Moreover, when lambda =2, maximum 4-cycle packings are found for all possible leaves.

Varieties of algebras arising from K-perfect m-cycle systems

A class of algebras forms a variety if it is characterised by a collection of identities. There is a well-known method, often called the standard construction, which gives rise to algebras from m-cycle systems. It is known that the algebras arising from {1}-perfect m-cycle systems form a variety for m is an element of {3, 5} only, and that the algebras arising from {1, 2}-perfect m-cycle systems form a variety for m is an element of {3, 5, 7} only. Here we give, for any set K of positive integers, necessary and sufficient conditions under which the algebras arising from K-perfect m-cycle systems form a variety. (c) 2006 Elsevier B.V. All rights reserved.

System-on-a-Chip (SoC) based hardware acceleration in Register Transfer Level (RTL) design

Today, modern System-on-a-Chip (SoC) systems have grown rapidly due to the increased processing power, while maintaining the size of the hardware circuit. The number of transistors on a chip continues to increase, but current SoC designs may not be able to exploit the potential performance, especially with energy consumption and chip area becoming two major concerns. Traditional SoC designs usually separate software and hardware. Thus, the process of improving the system performance is a complicated task for both software and hardware designers. The aim of this research is to develop hardware acceleration workflow for software applications. Thus, system performance can be improved with constraints of energy consumption and on-chip resource costs. The characteristics of software applications can be identified by using profiling tools. Hardware acceleration can have significant performance improvement for highly mathematical calculations or repeated functions. The performance of SoC systems can then be improved, if the hardware acceleration method is used to accelerate the element that incurs performance overheads. The concepts mentioned in this study can be easily applied to a variety of sophisticated software applications. The contributions of SoC-based hardware acceleration in the hardware-software co-design platform include the following: (1) Software profiling methods are applied to H.264 Coder-Decoder (CODEC) core. The hotspot function of aimed application is identified by using critical attributes such as cycles per loop, loop rounds, etc. (2) Hardware acceleration method based on Field-Programmable Gate Array (FPGA) is used to resolve system bottlenecks and improve system performance. The identified hotspot function is then converted to a hardware accelerator and mapped onto the hardware platform. Two types of hardware acceleration methods – central bus design and co-processor design, are implemented for comparison in the proposed architecture. (3) System specifications, such as performance, energy consumption, and resource costs, are measured and analyzed. The trade-off of these three factors is compared and balanced. Different hardware accelerators are implemented and evaluated based on system requirements. 4) The system verification platform is designed based on Integrated Circuit (IC) workflow. Hardware optimization techniques are used for higher performance and less resource costs. Experimental results show that the proposed hardware acceleration workflow for software applications is an efficient technique. The system can reach 2.8X performance improvements and save 31.84% energy consumption by applying the Bus-IP design. The Co-processor design can have 7.9X performance and save 75.85% energy consumption.

Die landwirthschaftliche Betriebsleitung in Bezug auf richtige Zeiteintheilung, zweckentsprechende Verwendung und Beaufsichtigung der Arbeitskräfte auf Feld und Hof : für ausübende und angehende Landwirthe, Verwalter, Volontaire, Lehrlinge etc. : mit in den Text gedruckten Abbildungen und 4 Tafeln Feldplänen

herausgegeben von Friedr. Aug. Pinckert, prakt. Oekonom und Gutsbesitzer, Inhaber der dem Sachsen-Ernestinischen Hausorden affiliirten Verdienstmedaille, correspondirendes Mitglied der k.k. patr. ökonomischen Gesellschaft im Königreich Böhmen ...

Immune System Approaches to Intrusion Detection - A Review

The use of artificial immune systems in intrusion detection is an appealing concept for two reasons. Firstly, the human immune system provides the human body with a high level of protection from invading pathogens, in a robust, self-organised and distributed manner. Secondly, current techniques used in computer security are not able to cope with the dynamic and increasingly complex nature of computer systems and their security. It is hoped that biologically inspired approaches in this area, including the use of immune-based systems will be able to meet this challenge. Here we review the algorithms used, the development of the systems and the outcome of their implementation. We provide an introduction and analysis of the key developments within this field, in addition to making suggestions for future research.

Primary biliary cirrhosis: proposal for a new simple histological scoring system

International audience

Novel Automotive Waste Heat Recovery Techniques

The United States transportation industry is predicted to consume approximately 13 million barrels of liquid fuel per day by 2025. If one percent of the fuel energy were salvaged through waste heat recovery, there would be a reduction of 130 thousand barrels of liquid fuel per day. This dissertation focuses on automotive waste heat recovery techniques with an emphasis on two novel techniques. The first technique investigated was a combination coolant and exhaust-based Rankine cycle system, which utilized a patented piston-in-piston engine technology. The research scope included a simulation of the maximum mass flow rate of steam (700 K and 5.5 MPa) from two heat exchangers, the potential power generation from the secondary piston steam chambers, and the resulting steam quality within the steam chamber. The secondary piston chamber provided supplemental steam power strokes during the engine's compression and exhaust strokes to reduce the pumping work of the engine. A Class-8 diesel engine, operating at 1,500 RPM at full load, had a maximum increase in the brake fuel conversion efficiency of 3.1%. The second technique investigated the implementation of thermoelectric generators on the outer cylinder walls of a liquid-cooled internal combustion engine. The research scope focused on the energy generation, fuel energy distribution, and cylinder wall temperatures. The analysis was conducted over a range of engine speeds and loads in a two cylinder, 19.4 kW, liquid-cooled, spark-ignition engine. The cylinder wall temperatures increased by 17% to 44% which correlated well to the 4.3% to 9.5% decrease in coolant heat transfer. Only 23.3% to 28.2% of the heat transfer to the coolant was transferred through the TEG and TEG surrogate material. The gross indicated work decreased by 0.4% to 1.0%. The exhaust gas energy decreased by 0.8% to 5.9%. Due to coolant contamination, the TEG output was not able to be obtained. TEG output was predicted from cylinder wall temperatures and manufacturer documentation, which was less than 0.1% of the cumulative heat release. Higher TEG conversion efficiencies, combined with greater control of heat transfer paths, would be needed to improve energy output and make this a viable waste heat recovery technique.

System-on-a-Chip (SoC) based Hardware Acceleration in Register Transfer Level (RTL) Design

Today, modern System-on-a-Chip (SoC) systems have grown rapidly due to the increased processing power, while maintaining the size of the hardware circuit. The number of transistors on a chip continues to increase, but current SoC designs may not be able to exploit the potential performance, especially with energy consumption and chip area becoming two major concerns. Traditional SoC designs usually separate software and hardware. Thus, the process of improving the system performance is a complicated task for both software and hardware designers. The aim of this research is to develop hardware acceleration workflow for software applications. Thus, system performance can be improved with constraints of energy consumption and on-chip resource costs. The characteristics of software applications can be identified by using profiling tools. Hardware acceleration can have significant performance improvement for highly mathematical calculations or repeated functions. The performance of SoC systems can then be improved, if the hardware acceleration method is used to accelerate the element that incurs performance overheads. The concepts mentioned in this study can be easily applied to a variety of sophisticated software applications. The contributions of SoC-based hardware acceleration in the hardware-software co-design platform include the following: (1) Software profiling methods are applied to H.264 Coder-Decoder (CODEC) core. The hotspot function of aimed application is identified by using critical attributes such as cycles per loop, loop rounds, etc. (2) Hardware acceleration method based on Field-Programmable Gate Array (FPGA) is used to resolve system bottlenecks and improve system performance. The identified hotspot function is then converted to a hardware accelerator and mapped onto the hardware platform. Two types of hardware acceleration methods – central bus design and co-processor design, are implemented for comparison in the proposed architecture. (3) System specifications, such as performance, energy consumption, and resource costs, are measured and analyzed. The trade-off of these three factors is compared and balanced. Different hardware accelerators are implemented and evaluated based on system requirements. 4) The system verification platform is designed based on Integrated Circuit (IC) workflow. Hardware optimization techniques are used for higher performance and less resource costs. Experimental results show that the proposed hardware acceleration workflow for software applications is an efficient technique. The system can reach 2.8X performance improvements and save 31.84% energy consumption by applying the Bus-IP design. The Co-processor design can have 7.9X performance and save 75.85% energy consumption.

Sistema de multiprocessamento para simulação de N-corpos em FPGA

Trabalho Final de Mestrado para obtenção do grau de Mestre em Engenharia de Electrónica e Telecomunicações