Design and fabrication of compact nonblocking 4X4 optical matrix switch on silicon-on-insulator by anisotropic chemical etching

A folding nonblocking 4 X 4 optical matrix switch in simplified-tree architecture was designed and fabricated on a silicon-on-insulator wafer. To compress chip size, switch elements (SEs) were connected by total internal reflection mirrors instead of conventional S-bends. For obtaining smooth interfaces, potassium hydroxide (KOH) anisotropic chemical etching of silicon was employed. The device has a compact size of 20 X 3.2 mm(2) and a fast response of 8 +/- 1 mu s. Power consumption of 2 x 2 SE and excess loss per mirror were 145 mW and -1.1 dB, respectively. (c) 2005 Society of Photo-Optical Instrumentation Engineers.

Design and analysis of 1.3 mu m GaAs-based quantum dot vertical-cavity surface-emitting lasers

A theoretical study on 1.3 mu m GaAs-based quantum dot vertical-cavity surface-emitting lasers (VCSELs) was made. Investigation of the influence of VCSELs on the optical confinement factors and the optical loss and the calculation of the material gain of the assembled InGaAs/GaAs quantum dots. Analysis of the threshold characteristic was made and the multi-wavelength cavity and multilayer quantum-dot stack structure is found to be more suitable for quantum dot VCSELs.

Design and fabrication of 1.06 mu m resonant-cavity enhanced reflective modulator with GaInAs/GaAs quantum wells

A resonant-cavity enhanced reflective optical modulator is designed and frabricated, with three groups of three highly strained InGaAS/GaAs quantum wells in the cavity, for the low voltage and high contrast ratio operation. The quantum wells are positioned in antinodes of the optical standing wave. The modulator is grown in a single growth step in an molecular beam epitaxy system, using GaAs/AIAs distributed Bragg reflectors as both the top and bottom mirrors. Results show that the reflection device has a modulation extinction of 3 dB at -4.5 V bias.

The design and verification of FPGA CAD toolset

This paper introduces a complete CAD toolset for the implementation of digital logic in a Field-Programmable Gate Array (FPGA) platform. Compared with existing academic toolsets, this toolset introduces formal verification in each step of the tool flow, especially the formal verification of the configuration bitstream. The FPGA CAD tool verification flow using Formality is presented in detail. Using plug-in technology, we have developed an integrated FPGA design kit to incorporate all tools together.

Design and performance of monolithic integrated electro-absorption modulated distributed feedback laser - art. no. 67820Y

High performance InGaAsP/InGaAsP strained compensated multiple-quantum-well (MQW) electroabsorption modulators (EAM) monolithically integrated with a DFB laser diode have been designed and realized by ultra low metal-organic vapor phase epitaxy (MOVPE) based on a novel butt joint scheme. The optimization thickness of upper SCH layer for DFB and EAM was obtained of the proposed MQW structure of the EAM through numerical simulation and experiment. The device containing 250(mu m) DFB and 170(mu m) EAM shows good material quality and exhibits a threshold current of 17mA, an extinction ratio of higher than 30 dB and a very high modulation efficiency (12dB/V) from 0V to 1V. By adopting a high-mesa ridge waveguide and buried polyimide, the capacitance of the modulator is reduced to about 0.30 pF corresponding to a 3dB bandwidth more than 20GHz.

Design and Realization of Index-Coupled DFB Laser with Sampled Grating

An index-coupled distributed feedback laser with the sampled grating has been designed and fabricated. The +1(st) order reflection of the sampled grating is utilized for laser single mode operation, which is 1.5329 mu m in the experiment. The sampled grating is formed by a conventional holographic exposure combined with the usual photolithography. The typical threshold current of DFB laser with the sampled grating is 25mA, and the optical output is about 10mW at the injected current of 100mA.

Design and Verification of the Programming Circuit in an Application-Specific FPGA

In this paper we present a methodology and its implementation for the design and verification of programming circuit used in a family of application-specific FPGAs that share a common architecture. Each member of the family is different either in the types of functional blocks contained or in the number of blocks of each type. The parametrized design methodology is presented here to achieve this goal. Even though our focus is on the programming circuitry that provides the interface between the FPGA core circuit and the external programming hardware, the parametrized design method can be generalized to the design of entire chip for all members in the FPGA family. The method presented here covers the generation of the design RTL files and the support files for synthesis, place-and-route layout and simulations. The proposed method is proven to work smoothly within the complete chip design methodology. We will describe the implementation of this method to the design of the programming circuit in details including the design flow from the behavioral-level design to the final layout as well as the verification. Different package options and different programming modes are included in the description of the design. The circuit design implementation is based on SMIC 0.13-micron CMOS technology.

Design and Fabrication of a Photonic Crystal Channel Drop Filter Based on an Asymmetric Silicon-on-Insulator Slab

We report on the design and fabrication of a photonic crystal (PC) channel drop filter based on an asymmetric silicon-on-insulator (SOI) slab. The filter is composed of two symmetric stick-shape micro-cavities between two single-line-defect (W1) waveguides in a triangular lattice, and the phase matching condition for the filter to improve the drop efficiency is satisfied by modifying the positions and radii of the air holes around the micro-cavities. A sample is then fabricated by using electron beam lithography (EBL) and inductively coupled plasma (ICP) etching processes. The measured 0 factor of the filter is about 1140, and the drop efficiency is estimated to be 73% +/- 5% by fitting the transmission spectrum.

Design and path planning for a remote-brained service robot

This paper presents a novel robot named "TUT03-A" with expert systems, speech interaction, vision systems etc. based on remote-brained approach. The robot is designed to have the brain and body separated. There is a cerebellum in the body. The brain with the expert systems is in charge of decision and the cerebellum control motion of the body. The brain-body. interface has many kinds of structure. It enables a brain to control one or more cerebellums. The brain controls all modules in the system and coordinates their work. The framework of the robot allows us to carry out different kinds of robotics research in an environment that can be shared and inherited over generations. Then we discuss the path planning method for the robot based on ant colony algorithm. The mathematical model is established and the algorithm is achieved with the Starlogo simulating environment. The simulation result shows that it has strong robustness and eligible pathfinding efficiency.

Design and path planning for a remote-brained service robot

This article introduced an effective design method of robot called remote-brain, which is made the brain and body separated. It leaves the brain in the mother environment, by which we mean the environment in which the brain's software is developed, and talks with its body by wireless links. It also presents a real robot TUT06-B based on this method which has human-machine interaction, vision systems, manipulator etc. Then it discussed the path planning method for the robot based on ant colony algorithm in details, especially the Ant-cycle model. And it also analyzed the parameter of the algorithm which can affect the convergence. Finally, it gives the program flow chat of this algorithm.

On the design and simulation of high speed electro-optic modulator based on SOI waveguide MOS dual capacitor structure

zhangdi于2010-03-29批量导入

Design and Fabrication of Low-microwave loss Coplannar Waveguide and precise V groove on Silicon Substrate for Optoelectronic Packaging - art. no. 601938

Optoelectronic packaging has become a most important factor that influences the final performance and cost of the module. In this paper, low microwave loss coplanar waveguide(CPW) on high resistivity silicon(HRS) and precise V groove in silicon substrate were successfully fabricated. The microwave attenuation of the CPW made on HRS with the simple process is lower than 2 dB/cm in the frequency range of 0 similar to 26GHz, and V groove has the accuracy in micro level and smooth surface. These two techniques built a good foundation for high frequency packaging and passive coupling of the optoelectronic devices. Based on these two techniques, a simple high resistivity silicon substrate that integrated V groove and CPW for flip-chip packaging of lasers was completed. It set a good example for more complicate optoelectronic packaging.

Circuit design and simulation of a CMOS-based preamplifier for brain neural signals

A novel CMOS-based preamplifier for amplifying brain neural signal obtained by scalp electrodes in brain-computer interface (BCI) is presented in this paper. By means of constructing effective equivalent input circuit structure of the preamplifier, two capacitors of 5 pF are included to realize the DC suppression compared to conventional preamplifiers. Then this preamplifier is designed and simulated using the standard 0.6 mu m MOS process technology model parameters with a supply voltage of 5 volts. With differential input structures adopted, simulation results of the preamplifier show that the input impedance amounts to more than 2 Gohm with brain neural signal frequency of 0.5 Hz-100 Hz. The equivalent input noise voltage is 18 nV/Hz(1/2). The common mode rejection ratio (CMRR) of 112 dB and the open-loop differential gain of 90 dB are achieved.

Design and Simulation Analysis of Spot-Size Converter in Silicon-On-Insulator

Submitted by 阎军 (yanj@red.semi.ac.cn) on 2010-06-04T08:02:20Z No. of bitstreams: 1 Design and Simulation Analysis of Spot-Size Converter in Silicon-On-Insulator.pdf: 239163 bytes, checksum: 82db1386c266d0c07442a972348da08c (MD5)

Design and Characterization of Evanescently Coupled Uni-Traveling Carrier Photodiodes with a Multimode Diluted Waveguide Structure

A new evanescently coupled uni-traveling carrier photodiode (EC-UTC-PD) is designed, fabricated and characterized, which incorporates a multimode diluted waveguide structure and UTC active waveguide structure together. A high responsivity of 0.68A/W at 1.55-mu m without an anti-reflection coating, a linear photocurrent responsivity of more than 21 mA, and a large-1 dB vertical alignment tolerance of 2.5 mu m are achieved.