Learning -dependent plasticity of movement representations in the primate primary motor cortex

Primary motor cortex (M1) is involved in the production of voluntary movement and contains a complete functional representation, or map, of the skeletal musculature. This functional map can be altered by pathological experiences, such as peripheral nerve injury or stroke, by pharmacological manipulation, and by behavioral experience. The process by which experience-dependent alterations of cortical function occur is termed plasticity. In this thesis, plasticity of M1 functional organization as a consequence of behavioral experience was examined in adult primates (squirrel monkeys). Maps of movement representations were derived under anesthesia using intracortical microstimulation, whereby a microelectrode was inserted into the cortex to electrically stimulate corticospinal neurons at low current levels and evoke movements of the forelimb, principally of the hand. Movement representations were examined before and at several times after training on behavioral tasks that emphasized use of the fingers. Two behavioral tasks were utilized that dissociated the repetition of motor activity from the acquisition of motor skills. One task was easy to perform, and as such promoted repetitive motor activity without learning. The other task was more difficult, requiring the acquisition of motor skills for successful performance. Kinematic analysis indicated that monkeys used a consistent set of forelimb movements during pellet extractions. Functional mapping revealed that repetitive motor activity during the easier task did not produce plastic changes in movement representations. Instead, map plasticity, in the form of selective expansions of task-related movement representations, was only produced following skill acquisition on the difficult task. Additional studies revealed that, in general, map plasticity persisted without further training for up to three months, in parallel with the retention of task-related motor skills. Also, extensive additional training on the small well task produced further improvements in performance, and further changes in movement maps. In sum, these experiments support the following three conclusions regarding the role of M1 in motor learning. First, behaviorally-driven plasticity is learning-dependent, not activity-dependent. Second, plastic changes in M1 functional representations represent a neural correlate of acquired motor skills. Third, the persistence of map plasticity suggests that M1 is part of the neural substrate for the memory of motor skills. ^

Use of echocardiography reveals reestablishment of ventricular pumping efficiency and partial ventricular wall motion recovery upon ventricular cryoinjury in the zebrafish

AIMS While zebrafish embryos are amenable to in vivo imaging, allowing the study of morphogenetic processes during development, intravital imaging of adults is hampered by their small size and loss of transparency. The use of adult zebrafish as a vertebrate model of cardiac disease and regeneration is increasing at high speed. It is therefore of great importance to establish appropriate and robust methods to measure cardiac function parameters. METHODS AND RESULTS Here we describe the use of 2D-echocardiography to study the fractional volume shortening and segmental wall motion of the ventricle. Our data show that 2D-echocardiography can be used to evaluate cardiac injury and also to study recovery of cardiac function. Interestingly, our results show that while global systolic function recovered following cardiac cryoinjury, ventricular wall motion was only partially restored. CONCLUSION Cryoinjury leads to long-lasting impairment of cardiac contraction, partially mimicking the consequences of myocardial infarction in humans. Functional assessment of heart regeneration by echocardiography allows a deeper understanding of the mechanisms of cardiac regeneration and has the advantage of being easily transferable to other cardiovascular zebrafish disease models.

Brain structural and functional recovery following initiation of combination antiretroviral therapy

NeuroAIDS persists in the era of combination antiretroviral therapies. We describe here the recovery of brain structure and function following 6 months of therapy in a treatment-naive patient presenting with HIV-associated dementia. The patient’s neuropsychological test performance improved and his total brain volume increased by more than 5 %. Neuronal functional connectivity measured by magnetoencephalography changed from a pattern identical to that observed in other HIV-infected individuals to one that was indistinguishable from that of uninfected control subjects. These data suggest that at least some of the effects of HIV on the brain can be fully reversed with treatment.

Parametric and structural self-adaptation of embedded systems using evolvable hardware

Los sistemas empotrados han sido concebidos tradicionalmente como sistemas de procesamiento específicos que realizan una tarea fija durante toda su vida útil. Para cumplir con requisitos estrictos de coste, tamaño y peso, el equipo de diseño debe optimizar su funcionamiento para condiciones muy específicas. Sin embargo, la demanda de mayor versatilidad, un funcionamiento más inteligente y, en definitiva, una mayor capacidad de procesamiento comenzaron a chocar con estas limitaciones, agravado por la incertidumbre asociada a entornos de operación cada vez más dinámicos donde comenzaban a ser desplegados progresivamente. Esto trajo como resultado una necesidad creciente de que los sistemas pudieran responder por si solos a eventos inesperados en tiempo diseño tales como: cambios en las características de los datos de entrada y el entorno del sistema en general; cambios en la propia plataforma de cómputo, por ejemplo debido a fallos o defectos de fabricación; y cambios en las propias especificaciones funcionales causados por unos objetivos del sistema dinámicos y cambiantes. Como consecuencia, la complejidad del sistema aumenta, pero a cambio se habilita progresivamente una capacidad de adaptación autónoma sin intervención humana a lo largo de la vida útil, permitiendo que tomen sus propias decisiones en tiempo de ejecución. Éstos sistemas se conocen, en general, como sistemas auto-adaptativos y tienen, entre otras características, las de auto-configuración, auto-optimización y auto-reparación. Típicamente, la parte soft de un sistema es mayoritariamente la única utilizada para proporcionar algunas capacidades de adaptación a un sistema. Sin embargo, la proporción rendimiento/potencia en dispositivos software como microprocesadores en muchas ocasiones no es adecuada para sistemas empotrados. En este escenario, el aumento resultante en la complejidad de las aplicaciones está siendo abordado parcialmente mediante un aumento en la complejidad de los dispositivos en forma de multi/many-cores; pero desafortunadamente, esto hace que el consumo de potencia también aumente. Además, la mejora en metodologías de diseño no ha sido acorde como para poder utilizar toda la capacidad de cómputo disponible proporcionada por los núcleos. Por todo ello, no se están satisfaciendo adecuadamente las demandas de cómputo que imponen las nuevas aplicaciones. La solución tradicional para mejorar la proporción rendimiento/potencia ha sido el cambio a unas especificaciones hardware, principalmente usando ASICs. Sin embargo, los costes de un ASIC son altamente prohibitivos excepto en algunos casos de producción en masa y además la naturaleza estática de su estructura complica la solución a las necesidades de adaptación. Los avances en tecnologías de fabricación han hecho que la FPGA, una vez lenta y pequeña, usada como glue logic en sistemas mayores, haya crecido hasta convertirse en un dispositivo de cómputo reconfigurable de gran potencia, con una cantidad enorme de recursos lógicos computacionales y cores hardware empotrados de procesamiento de señal y de propósito general. Sus capacidades de reconfiguración han permitido combinar la flexibilidad propia del software con el rendimiento del procesamiento en hardware, lo que tiene la potencialidad de provocar un cambio de paradigma en arquitectura de computadores, pues el hardware no puede ya ser considerado más como estático. El motivo es que como en el caso de las FPGAs basadas en tecnología SRAM, la reconfiguración parcial dinámica (DPR, Dynamic Partial Reconfiguration) es posible. Esto significa que se puede modificar (reconfigurar) un subconjunto de los recursos computacionales en tiempo de ejecución mientras el resto permanecen activos. Además, este proceso de reconfiguración puede ser ejecutado internamente por el propio dispositivo. El avance tecnológico en dispositivos hardware reconfigurables se encuentra recogido bajo el campo conocido como Computación Reconfigurable (RC, Reconfigurable Computing). Uno de los campos de aplicación más exóticos y menos convencionales que ha posibilitado la computación reconfigurable es el conocido como Hardware Evolutivo (EHW, Evolvable Hardware), en el cual se encuentra enmarcada esta tesis. La idea principal del concepto consiste en convertir hardware que es adaptable a través de reconfiguración en una entidad evolutiva sujeta a las fuerzas de un proceso evolutivo inspirado en el de las especies biológicas naturales, que guía la dirección del cambio. Es una aplicación más del campo de la Computación Evolutiva (EC, Evolutionary Computation), que comprende una serie de algoritmos de optimización global conocidos como Algoritmos Evolutivos (EA, Evolutionary Algorithms), y que son considerados como algoritmos universales de resolución de problemas. En analogía al proceso biológico de la evolución, en el hardware evolutivo el sujeto de la evolución es una población de circuitos que intenta adaptarse a su entorno mediante una adecuación progresiva generación tras generación. Los individuos pasan a ser configuraciones de circuitos en forma de bitstreams caracterizados por descripciones de circuitos reconfigurables. Seleccionando aquellos que se comportan mejor, es decir, que tienen una mejor adecuación (o fitness) después de ser evaluados, y usándolos como padres de la siguiente generación, el algoritmo evolutivo crea una nueva población hija usando operadores genéticos como la mutación y la recombinación. Según se van sucediendo generaciones, se espera que la población en conjunto se aproxime a la solución óptima al problema de encontrar una configuración del circuito adecuada que satisfaga las especificaciones. El estado de la tecnología de reconfiguración después de que la familia de FPGAs XC6200 de Xilinx fuera retirada y reemplazada por las familias Virtex a finales de los 90, supuso un gran obstáculo para el avance en hardware evolutivo; formatos de bitstream cerrados (no conocidos públicamente); dependencia de herramientas del fabricante con soporte limitado de DPR; una velocidad de reconfiguración lenta; y el hecho de que modificaciones aleatorias del bitstream pudieran resultar peligrosas para la integridad del dispositivo, son algunas de estas razones. Sin embargo, una propuesta a principios de los años 2000 permitió mantener la investigación en el campo mientras la tecnología de DPR continuaba madurando, el Circuito Virtual Reconfigurable (VRC, Virtual Reconfigurable Circuit). En esencia, un VRC en una FPGA es una capa virtual que actúa como un circuito reconfigurable de aplicación específica sobre la estructura nativa de la FPGA que reduce la complejidad del proceso reconfiguración y aumenta su velocidad (comparada con la reconfiguración nativa). Es un array de nodos computacionales especificados usando descripciones HDL estándar que define recursos reconfigurables ad-hoc: multiplexores de rutado y un conjunto de elementos de procesamiento configurables, cada uno de los cuales tiene implementadas todas las funciones requeridas, que pueden seleccionarse a través de multiplexores tal y como ocurre en una ALU de un microprocesador. Un registro grande actúa como memoria de configuración, por lo que la reconfiguración del VRC es muy rápida ya que tan sólo implica la escritura de este registro, el cual controla las señales de selección del conjunto de multiplexores. Sin embargo, esta capa virtual provoca: un incremento de área debido a la implementación simultánea de cada función en cada nodo del array más los multiplexores y un aumento del retardo debido a los multiplexores, reduciendo la frecuencia de funcionamiento máxima. La naturaleza del hardware evolutivo, capaz de optimizar su propio comportamiento computacional, le convierten en un buen candidato para avanzar en la investigación sobre sistemas auto-adaptativos. Combinar un sustrato de cómputo auto-reconfigurable capaz de ser modificado dinámicamente en tiempo de ejecución con un algoritmo empotrado que proporcione una dirección de cambio, puede ayudar a satisfacer los requisitos de adaptación autónoma de sistemas empotrados basados en FPGA. La propuesta principal de esta tesis está por tanto dirigida a contribuir a la auto-adaptación del hardware de procesamiento de sistemas empotrados basados en FPGA mediante hardware evolutivo. Esto se ha abordado considerando que el comportamiento computacional de un sistema puede ser modificado cambiando cualquiera de sus dos partes constitutivas: una estructura hard subyacente y un conjunto de parámetros soft. De esta distinción, se derivan dos lineas de trabajo. Por un lado, auto-adaptación paramétrica, y por otro auto-adaptación estructural. El objetivo perseguido en el caso de la auto-adaptación paramétrica es la implementación de técnicas de optimización evolutiva complejas en sistemas empotrados con recursos limitados para la adaptación paramétrica online de circuitos de procesamiento de señal. La aplicación seleccionada como prueba de concepto es la optimización para tipos muy específicos de imágenes de los coeficientes de los filtros de transformadas wavelet discretas (DWT, DiscreteWavelet Transform), orientada a la compresión de imágenes. Por tanto, el objetivo requerido de la evolución es una compresión adaptativa y más eficiente comparada con los procedimientos estándar. El principal reto radica en reducir la necesidad de recursos de supercomputación para el proceso de optimización propuesto en trabajos previos, de modo que se adecúe para la ejecución en sistemas empotrados. En cuanto a la auto-adaptación estructural, el objetivo de la tesis es la implementación de circuitos auto-adaptativos en sistemas evolutivos basados en FPGA mediante un uso eficiente de sus capacidades de reconfiguración nativas. En este caso, la prueba de concepto es la evolución de tareas de procesamiento de imagen tales como el filtrado de tipos desconocidos y cambiantes de ruido y la detección de bordes en la imagen. En general, el objetivo es la evolución en tiempo de ejecución de tareas de procesamiento de imagen desconocidas en tiempo de diseño (dentro de un cierto grado de complejidad). En este caso, el objetivo de la propuesta es la incorporación de DPR en EHW para evolucionar la arquitectura de un array sistólico adaptable mediante reconfiguración cuya capacidad de evolución no había sido estudiada previamente. Para conseguir los dos objetivos mencionados, esta tesis propone originalmente una plataforma evolutiva que integra un motor de adaptación (AE, Adaptation Engine), un motor de reconfiguración (RE, Reconfiguration Engine) y un motor computacional (CE, Computing Engine) adaptable. El el caso de adaptación paramétrica, la plataforma propuesta está caracterizada por: • un CE caracterizado por un núcleo de procesamiento hardware de DWT adaptable mediante registros reconfigurables que contienen los coeficientes de los filtros wavelet • un algoritmo evolutivo como AE que busca filtros wavelet candidatos a través de un proceso de optimización paramétrica desarrollado específicamente para sistemas caracterizados por recursos de procesamiento limitados • un nuevo operador de mutación simplificado para el algoritmo evolutivo utilizado, que junto con un mecanismo de evaluación rápida de filtros wavelet candidatos derivado de la literatura actual, asegura la viabilidad de la búsqueda evolutiva asociada a la adaptación de wavelets. En el caso de adaptación estructural, la plataforma propuesta toma la forma de: • un CE basado en una plantilla de array sistólico reconfigurable de 2 dimensiones compuesto de nodos de procesamiento reconfigurables • un algoritmo evolutivo como AE que busca configuraciones candidatas del array usando un conjunto de funcionalidades de procesamiento para los nodos disponible en una biblioteca accesible en tiempo de ejecución • un RE hardware que explota la capacidad de reconfiguración nativa de las FPGAs haciendo un uso eficiente de los recursos reconfigurables del dispositivo para cambiar el comportamiento del CE en tiempo de ejecución • una biblioteca de elementos de procesamiento reconfigurables caracterizada por bitstreams parciales independientes de la posición, usados como el conjunto de configuraciones disponibles para los nodos de procesamiento del array Las contribuciones principales de esta tesis se pueden resumir en la siguiente lista: • Una plataforma evolutiva basada en FPGA para la auto-adaptación paramétrica y estructural de sistemas empotrados compuesta por un motor computacional (CE), un motor de adaptación (AE) evolutivo y un motor de reconfiguración (RE). Esta plataforma se ha desarrollado y particularizado para los casos de auto-adaptación paramétrica y estructural. • En cuanto a la auto-adaptación paramétrica, las contribuciones principales son: – Un motor computacional adaptable mediante registros que permite la adaptación paramétrica de los coeficientes de una implementación hardware adaptativa de un núcleo de DWT. – Un motor de adaptación basado en un algoritmo evolutivo desarrollado específicamente para optimización numérica, aplicada a los coeficientes de filtros wavelet en sistemas empotrados con recursos limitados. – Un núcleo IP de DWT auto-adaptativo en tiempo de ejecución para sistemas empotrados que permite la optimización online del rendimiento de la transformada para compresión de imágenes en entornos específicos de despliegue, caracterizados por tipos diferentes de señal de entrada. – Un modelo software y una implementación hardware de una herramienta para la construcción evolutiva automática de transformadas wavelet específicas. • Por último, en cuanto a la auto-adaptación estructural, las contribuciones principales son: – Un motor computacional adaptable mediante reconfiguración nativa de FPGAs caracterizado por una plantilla de array sistólico en dos dimensiones de nodos de procesamiento reconfigurables. Es posible mapear diferentes tareas de cómputo en el array usando una biblioteca de elementos sencillos de procesamiento reconfigurables. – Definición de una biblioteca de elementos de procesamiento apropiada para la síntesis autónoma en tiempo de ejecución de diferentes tareas de procesamiento de imagen. – Incorporación eficiente de la reconfiguración parcial dinámica (DPR) en sistemas de hardware evolutivo, superando los principales inconvenientes de propuestas previas como los circuitos reconfigurables virtuales (VRCs). En este trabajo también se comparan originalmente los detalles de implementación de ambas propuestas. – Una plataforma tolerante a fallos, auto-curativa, que permite la recuperación funcional online en entornos peligrosos. La plataforma ha sido caracterizada desde una perspectiva de tolerancia a fallos: se proponen modelos de fallo a nivel de CLB y de elemento de procesamiento, y usando el motor de reconfiguración, se hace un análisis sistemático de fallos para un fallo en cada elemento de procesamiento y para dos fallos acumulados. – Una plataforma con calidad de filtrado dinámica que permite la adaptación online a tipos de ruido diferentes y diferentes comportamientos computacionales teniendo en cuenta los recursos de procesamiento disponibles. Por un lado, se evolucionan filtros con comportamientos no destructivos, que permiten esquemas de filtrado en cascada escalables; y por otro, también se evolucionan filtros escalables teniendo en cuenta requisitos computacionales de filtrado cambiantes dinámicamente. Este documento está organizado en cuatro partes y nueve capítulos. La primera parte contiene el capítulo 1, una introducción y motivación sobre este trabajo de tesis. A continuación, el marco de referencia en el que se enmarca esta tesis se analiza en la segunda parte: el capítulo 2 contiene una introducción a los conceptos de auto-adaptación y computación autonómica (autonomic computing) como un campo de investigación más general que el muy específico de este trabajo; el capítulo 3 introduce la computación evolutiva como la técnica para dirigir la adaptación; el capítulo 4 analiza las plataformas de computación reconfigurables como la tecnología para albergar hardware auto-adaptativo; y finalmente, el capítulo 5 define, clasifica y hace un sondeo del campo del hardware evolutivo. Seguidamente, la tercera parte de este trabajo contiene la propuesta, desarrollo y resultados obtenidos: mientras que el capítulo 6 contiene una declaración de los objetivos de la tesis y la descripción de la propuesta en su conjunto, los capítulos 7 y 8 abordan la auto-adaptación paramétrica y estructural, respectivamente. Finalmente, el capítulo 9 de la parte 4 concluye el trabajo y describe caminos de investigación futuros. ABSTRACT Embedded systems have traditionally been conceived to be specific-purpose computers with one, fixed computational task for their whole lifetime. Stringent requirements in terms of cost, size and weight forced designers to highly optimise their operation for very specific conditions. However, demands for versatility, more intelligent behaviour and, in summary, an increased computing capability began to clash with these limitations, intensified by the uncertainty associated to the more dynamic operating environments where they were progressively being deployed. This brought as a result an increasing need for systems to respond by themselves to unexpected events at design time, such as: changes in input data characteristics and system environment in general; changes in the computing platform itself, e.g., due to faults and fabrication defects; and changes in functional specifications caused by dynamically changing system objectives. As a consequence, systems complexity is increasing, but in turn, autonomous lifetime adaptation without human intervention is being progressively enabled, allowing them to take their own decisions at run-time. This type of systems is known, in general, as selfadaptive, and are able, among others, of self-configuration, self-optimisation and self-repair. Traditionally, the soft part of a system has mostly been so far the only place to provide systems with some degree of adaptation capabilities. However, the performance to power ratios of software driven devices like microprocessors are not adequate for embedded systems in many situations. In this scenario, the resulting rise in applications complexity is being partly addressed by rising devices complexity in the form of multi and many core devices; but sadly, this keeps on increasing power consumption. Besides, design methodologies have not been improved accordingly to completely leverage the available computational power from all these cores. Altogether, these factors make that the computing demands new applications pose are not being wholly satisfied. The traditional solution to improve performance to power ratios has been the switch to hardware driven specifications, mainly using ASICs. However, their costs are highly prohibitive except for some mass production cases and besidesthe static nature of its structure complicates the solution to the adaptation needs. The advancements in fabrication technologies have made that the once slow, small FPGA used as glue logic in bigger systems, had grown to be a very powerful, reconfigurable computing device with a vast amount of computational logic resources and embedded, hardened signal and general purpose processing cores. Its reconfiguration capabilities have enabled software-like flexibility to be combined with hardware-like computing performance, which has the potential to cause a paradigm shift in computer architecture since hardware cannot be considered as static anymore. This is so, since, as is the case with SRAMbased FPGAs, Dynamic Partial Reconfiguration (DPR) is possible. This means that subsets of the FPGA computational resources can now be changed (reconfigured) at run-time while the rest remains active. Besides, this reconfiguration process can be triggered internally by the device itself. This technological boost in reconfigurable hardware devices is actually covered under the field known as Reconfigurable Computing. One of the most exotic fields of application that Reconfigurable Computing has enabled is the known as Evolvable Hardware (EHW), in which this dissertation is framed. The main idea behind the concept is turning hardware that is adaptable through reconfiguration into an evolvable entity subject to the forces of an evolutionary process, inspired by that of natural, biological species, that guides the direction of change. It is yet another application of the field of Evolutionary Computation (EC), which comprises a set of global optimisation algorithms known as Evolutionary Algorithms (EAs), considered as universal problem solvers. In analogy to the biological process of evolution, in EHW the subject of evolution is a population of circuits that tries to get adapted to its surrounding environment by progressively getting better fitted to it generation after generation. Individuals become circuit configurations representing bitstreams that feature reconfigurable circuit descriptions. By selecting those that behave better, i.e., with a higher fitness value after being evaluated, and using them as parents of the following generation, the EA creates a new offspring population by using so called genetic operators like mutation and recombination. As generations succeed one another, the whole population is expected to approach to the optimum solution to the problem of finding an adequate circuit configuration that fulfils system objectives. The state of reconfiguration technology after Xilinx XC6200 FPGA family was discontinued and replaced by Virtex families in the late 90s, was a major obstacle for advancements in EHW; closed (non publicly known) bitstream formats; dependence on manufacturer tools with highly limiting support of DPR; slow speed of reconfiguration; and random bitstream modifications being potentially hazardous for device integrity, are some of these reasons. However, a proposal in the first 2000s allowed to keep investigating in this field while DPR technology kept maturing, the Virtual Reconfigurable Circuit (VRC). In essence, a VRC in an FPGA is a virtual layer acting as an application specific reconfigurable circuit on top of an FPGA fabric that reduces the complexity of the reconfiguration process and increases its speed (compared to native reconfiguration). It is an array of computational nodes specified using standard HDL descriptions that define ad-hoc reconfigurable resources; routing multiplexers and a set of configurable processing elements, each one containing all the required functions, which are selectable through functionality multiplexers as in microprocessor ALUs. A large register acts as configuration memory, so VRC reconfiguration is very fast given it only involves writing this register, which drives the selection signals of the set of multiplexers. However, large overheads are introduced by this virtual layer; an area overhead due to the simultaneous implementation of every function in every node of the array plus the multiplexers, and a delay overhead due to the multiplexers, which also reduces maximum frequency of operation. The very nature of Evolvable Hardware, able to optimise its own computational behaviour, makes it a good candidate to advance research in self-adaptive systems. Combining a selfreconfigurable computing substrate able to be dynamically changed at run-time with an embedded algorithm that provides a direction for change, can help fulfilling requirements for autonomous lifetime adaptation of FPGA-based embedded systems. The main proposal of this thesis is hence directed to contribute to autonomous self-adaptation of the underlying computational hardware of FPGA-based embedded systems by means of Evolvable Hardware. This is tackled by considering that the computational behaviour of a system can be modified by changing any of its two constituent parts: an underlying hard structure and a set of soft parameters. Two main lines of work derive from this distinction. On one side, parametric self-adaptation and, on the other side, structural self-adaptation. The goal pursued in the case of parametric self-adaptation is the implementation of complex evolutionary optimisation techniques in resource constrained embedded systems for online parameter adaptation of signal processing circuits. The application selected as proof of concept is the optimisation of Discrete Wavelet Transforms (DWT) filters coefficients for very specific types of images, oriented to image compression. Hence, adaptive and improved compression efficiency, as compared to standard techniques, is the required goal of evolution. The main quest lies in reducing the supercomputing resources reported in previous works for the optimisation process in order to make it suitable for embedded systems. Regarding structural self-adaptation, the thesis goal is the implementation of self-adaptive circuits in FPGA-based evolvable systems through an efficient use of native reconfiguration capabilities. In this case, evolution of image processing tasks such as filtering of unknown and changing types of noise and edge detection are the selected proofs of concept. In general, evolving unknown image processing behaviours (within a certain complexity range) at design time is the required goal. In this case, the mission of the proposal is the incorporation of DPR in EHW to evolve a systolic array architecture adaptable through reconfiguration whose evolvability had not been previously checked. In order to achieve the two stated goals, this thesis originally proposes an evolvable platform that integrates an Adaptation Engine (AE), a Reconfiguration Engine (RE) and an adaptable Computing Engine (CE). In the case of parametric adaptation, the proposed platform is characterised by: • a CE featuring a DWT hardware processing core adaptable through reconfigurable registers that holds wavelet filters coefficients • an evolutionary algorithm as AE that searches for candidate wavelet filters through a parametric optimisation process specifically developed for systems featured by scarce computing resources • a new, simplified mutation operator for the selected EA, that together with a fast evaluation mechanism of candidate wavelet filters derived from existing literature, assures the feasibility of the evolutionary search involved in wavelets adaptation In the case of structural adaptation, the platform proposal takes the form of: • a CE based on a reconfigurable 2D systolic array template composed of reconfigurable processing nodes • an evolutionary algorithm as AE that searches for candidate configurations of the array using a set of computational functionalities for the nodes available in a run time accessible library • a hardware RE that exploits native DPR capabilities of FPGAs and makes an efficient use of the available reconfigurable resources of the device to change the behaviour of the CE at run time • a library of reconfigurable processing elements featured by position-independent partial bitstreams used as the set of available configurations for the processing nodes of the array Main contributions of this thesis can be summarised in the following list. • An FPGA-based evolvable platform for parametric and structural self-adaptation of embedded systems composed of a Computing Engine, an evolutionary Adaptation Engine and a Reconfiguration Engine. This platform is further developed and tailored for both parametric and structural self-adaptation. • Regarding parametric self-adaptation, main contributions are: – A CE adaptable through reconfigurable registers that enables parametric adaptation of the coefficients of an adaptive hardware implementation of a DWT core. – An AE based on an Evolutionary Algorithm specifically developed for numerical optimisation applied to wavelet filter coefficients in resource constrained embedded systems. – A run-time self-adaptive DWT IP core for embedded systems that allows for online optimisation of transform performance for image compression for specific deployment environments characterised by different types of input signals. – A software model and hardware implementation of a tool for the automatic, evolutionary construction of custom wavelet transforms. • Lastly, regarding structural self-adaptation, main contributions are: – A CE adaptable through native FPGA fabric reconfiguration featured by a two dimensional systolic array template of reconfigurable processing nodes. Different processing behaviours can be automatically mapped in the array by using a library of simple reconfigurable processing elements. – Definition of a library of such processing elements suited for autonomous runtime synthesis of different image processing tasks. – Efficient incorporation of DPR in EHW systems, overcoming main drawbacks from the previous approach of virtual reconfigurable circuits. Implementation details for both approaches are also originally compared in this work. – A fault tolerant, self-healing platform that enables online functional recovery in hazardous environments. The platform has been characterised from a fault tolerance perspective: fault models at FPGA CLB level and processing elements level are proposed, and using the RE, a systematic fault analysis for one fault in every processing element and for two accumulated faults is done. – A dynamic filtering quality platform that permits on-line adaptation to different types of noise and different computing behaviours considering the available computing resources. On one side, non-destructive filters are evolved, enabling scalable cascaded filtering schemes; and on the other, size-scalable filters are also evolved considering dynamically changing computational filtering requirements. This dissertation is organized in four parts and nine chapters. First part contains chapter 1, the introduction to and motivation of this PhD work. Following, the reference framework in which this dissertation is framed is analysed in the second part: chapter 2 features an introduction to the notions of self-adaptation and autonomic computing as a more general research field to the very specific one of this work; chapter 3 introduces evolutionary computation as the technique to drive adaptation; chapter 4 analyses platforms for reconfigurable computing as the technology to hold self-adaptive hardware; and finally chapter 5 defines, classifies and surveys the field of Evolvable Hardware. Third part of the work follows, which contains the proposal, development and results obtained: while chapter 6 contains an statement of the thesis goals and the description of the proposal as a whole, chapters 7 and 8 address parametric and structural self-adaptation, respectively. Finally, chapter 9 in part 4 concludes the work and describes future research paths.

CENP-E is an essential kinetochore motor in maturing oocytes and is masked during Mos-dependent, cell cycle arrest at metaphase II

CENP-E, a kinesin-like protein that is known to associate with kinetochores during all phases of mitotic chromosome movement, is shown here to be a component of meiotic kinetochores as well. CENP-E is detected at kinetochores during metaphase I in both mice and frogs, and, as in mitosis, is relocalized to the midbody during telophase. CENP-E function is essential for meiosis I because injection of an antibody to CENP-E into mouse oocytes in prophase completely prevented progression of those oocytes past metaphase I. Beyond this, CENP-E is modified or masked during the natural, Mos-dependent, cell cycle arrest that occurs at metaphase II, although it is readily detectable at the kinetochores in metaphase II oocytes derived from mos-deficient (MOS−/−) mice that fail to arrest at metaphase II. This must reflect a masking of some CENP-E epitopes, not the absence of CENP-E, in meiosis II because a different polyclonal antibody raised to the tail of CENP-E detects CENP-E at kinetochores of metaphase II-arrested eggs and because CENP-E reappears in telophase of mouse oocytes activated in the absence of protein synthesis.

Inactivation of the survival motor neuron gene, a candidate gene for human spinal muscular atrophy, leads to massive cell death in early mouse embryos

Proximal spinal muscular atrophy is an autosomal recessive human disease of spinal motor neurons leading to muscular weakness with onset predominantly in infancy and childhood. With an estimated heterozygote frequency of 1/40 it is the most common monogenic disorder lethal to infants; milder forms represent the second most common pediatric neuromuscular disorder. Two candidate genes—survival motor neuron (SMN) and neuronal apoptosis inhibitory protein have been identified on chromosome 5q13 by positional cloning. However, the functional impact of these genes and the mechanism leading to a degeneration of motor neurons remain to be defined. To analyze the role of the SMN gene product in vivo we generated SMN-deficient mice. In contrast to the human genome, which contains two copies, the mouse genome contains only one SMN gene. Mice with homozygous SMN disruption display massive cell death during early embryonic development, indicating that the SMN gene product is necessary for cellular survival and function.

CM101-mediated recovery of walking ability in adult mice paralyzed by spinal cord injury

CM101, an antiangiogenic polysaccharide derived from group B streptococcus, was administered by i.v. injection 1 hr post-spinal-cord crush injury in an effort to prevent inflammatory angiogenesis and gliosis (scarring) in a mouse model. We postulated that gliosis would sterically prevent the reestablishment of neuronal connectivity; thus, treatment with CM101 was repeated every other day for five more infusions for the purpose of facilitating regeneration of neuronal function. Twenty-five of 26 mice treated with CM101 survived 28 days after surgery, and 24 of 26 recovered walking ability within 2–12 days. Only 6 of 14 mice in the control groups survived 24 hr after spinal cord injury, and none recovered function in paralyzed limbs. MRI analysis of injured untreated and treated animals showed that CM101 reduced the area of damage at the site of spinal cord compression, which was corroborated by histological analysis of spinal cord sections from treated and control animals. Electrophysiologic measurements on isolated central nervous system and neurons in culture showed that CM101 protected axons from Wallerian degeneration; reversed γ-aminobutyrate-mediated depolarization occurring in traumatized neurons; and improved recovery of neuronal conductivity of isolated central nervous system in culture.

Requirement of poly(ADP-ribose) polymerase in recovery from DNA damage in mice and in cells

Poly(ADP-ribose) polymerase [PARP; NAD+ ADP-ribosyltransferase; NAD+: poly(adenosine-diphosphate-d-ribosyl)-acceptor ADP-d-ribosyltransferase, EC 2.4.2.30] is a zinc-finger DNA-binding protein that detects specifically DNA strand breaks generated by genotoxic agents. To determine its biological function, we have inactivated both alleles by gene targeting in mice. Treatment of PARP−/− mice either by the alkylating agent N-methyl-N-nitrosourea (MNU) or by γ-irradiation revealed an extreme sensitivity and a high genomic instability to both agents. Following whole body γ-irradiation (8 Gy) mutant mice died rapidly from acute radiation toxicity to the small intestine. Mice-derived PARP−/− cells displayed a high sensitivity to MNU exposure: a G2/M arrest in mouse embryonic fibroblasts and a rapid apoptotic response and a p53 accumulation were observed in splenocytes. Altogether these results demonstrate that PARP is a survival factor playing an essential and positive role during DNA damage recovery.

Long-term expression of protein kinase C in adult mouse hearts improves postischemic recovery

Activation of protein kinase C (PKC) protects the heart from ischemic injury; however, its mechanism of action is unknown, in part because no model for chronic activation of PKC has been available. To test whether chronic, mild elevation of PKC activity in adult mouse hearts results in myocardial protection during ischemia or reperfusion, hearts isolated from transgenic mice expressing a low level of activated PKCβ throughout adulthood (β-Tx) were compared with control hearts before ischemia, during 12 or 28 min of no-flow ischemia, and during reperfusion. Left-ventricular-developed pressure in isolated isovolumic hearts, normalized to heart weight, was similar in the two groups at baseline. However, recovery of contractile function was markedly improved in β-Tx hearts after either 12 (97 ± 3% vs. 69 ± 4%) or 28 min of ischemia (76 ± 8% vs. 48 ± 3%). Chelerythrine, a PKC inhibitor, abolished the difference between the two groups, indicating that the beneficial effect was PKC-mediated. 31P NMR spectroscopy was used to test whether modification of intracellular pH and/or preservation of high-energy phosphate levels during ischemia contributed to the cardioprotection in β-Tx hearts. No difference in intracellular pH or high-energy phosphate levels was found between the β-Tx and control hearts at baseline or during ischemia. Thus, long-term modest increase in PKC activity in adult mouse hearts did not alter baseline function but did lead to improved postischemic recovery. Furthermore, our results suggest that mechanisms other than reduced acidification and preservation of high-energy phosphate levels during ischemia contribute to the improved recovery.

A Developmentally Regulated Kinesin-related Motor Protein from Dictyostelium discoideum

The cellular slime mold Dictyostelium discoideum is an attractive system for studying the roles of microtubule-based motility in cell development and differentiation. In this work, we report the first molecular characterization of kinesin-related proteins (KRPs) in Dictyostelium. A PCR-based strategy was used to isolate DNA fragments encoding six KRPs, several of which are induced during the developmental program that is initiated by starvation. The complete sequence of one such developmentally regulated KRP (designated K7) was determined and found to be a novel member of the kinesin superfamily. The motor domain of K7 is most similar to that of conventional kinesin, but unlike conventional kinesin, K7 is not predicted to have an extensive α-helical coiled-coil domain. The nonmotor domain is unusual and is rich in Asn, Gln, and Thr residues; similar sequences are found in other developmentally regulated genes in Dictyostelium. K7, expressed in Escherichia coli, supports plus end–directed microtubule motility in vitro at a speed of 0.14 μm/s, indicating that it is a bona fide motor protein. The K7 motor is found only in developing cells and reaches a peak level of expression between 12 and 16 h after starvation. By immunofluorescence microscopy, K7 localizes to a membranous perinuclear structure. To examine K7 function, we prepared a null cell line but found that these cells show no gross developmental abnormalities. However, when cultivated in the presence of wild-type cells, the K7-null cells are mostly absent from the prestalk zone of the slug. This result suggests that in a population composed largely of wild-type cells, the absence of the K7 motor protein interferes either with the ability of the cells to localize to the prestalk zone or to differentiate into prestalk cells.

The Involvement of the Intermediate Chain of Cytoplasmic Dynein in Binding the Motor Complex to Membranous Organelles of Xenopus Oocytes

Cytoplasmic dynein is one of the major motor proteins involved in intracellular transport. It is a protein complex consisting of four subunit classes: heavy chains, intermediate chains (ICs), light intermediate chains, and light chains. In a previous study, we had generated new monoclonal antibodies to the ICs and mapped the ICs to the base of the motor. Because the ICs have been implicated in targeting the motor to cargo, we tested whether these new antibodies to the intermediate chain could block the function of cytoplasmic dynein. When cytoplasmic extracts of Xenopus oocytes were incubated with either one of the monoclonal antibodies (m74–1, m74–2), neither organelle movement nor network formation was observed. Network formation and membrane transport was blocked at an antibody concentration as low as 15 μg/ml. In contrast to these observations, no effect was observed on organelle movement and tubular network formation in the presence of a control antibody at concentrations as high as 0.5 mg/ml. After incubating cytoplasmic extracts or isolated membranes with the monoclonal antibodies m74–1 and m74–2, the dynein IC polypeptide was no longer detectable in the membrane fraction by SDS-PAGE immunoblot, indicating a loss of cytoplasmic dynein from the membrane. We used a panel of dynein IC truncation mutants and mapped the epitopes of both antibodies to the N-terminal coiled-coil domain, in close proximity to the p150Glued binding domain. In an IC affinity column binding assay, both antibodies inhibited the IC–p150Glued interaction. Thus these findings demonstrate that direct IC–p150Glued interaction is required for the proper attachment of cytoplasmic dynein to membranes.

Deficits in memory and motor performance in synaptotagmin IV mutant mice

Synaptotagmin (Syt) IV is a synaptic vesicle protein. Syt IV expression is induced in the rat hippocampus after systemic kainic acid treatment. To examine the functional role of this protein in vivo, we derived Syt IV null [Syt IV(−/−)] mutant mice. Studies with the rotorod revealed that the Syt IV mutants have impaired motor coordination, a result consistent with constitutive Syt IV expression in the cerebellum. Because Syt IV is thought to modulate synaptic function, we also have examined Syt IV mutant mice in learning and memory tests. Our studies show that the Syt IV mutation disrupts contextual fear conditioning, a learning task sensitive to hippocampal and amygdala lesions. In contrast, cued fear conditioning is normal in the Syt IV mutants, suggesting that this mutation did not disrupt amygdala function. Conditioned taste aversion, which also depends on the amygdala, is normal in the Syt IV mutants. Consistent with the idea that the Syt IV mutation preferentially affects hippocampal function, Syt IV mutant mice also display impaired social transmission of food preference. These studies demonstrate that Syt IV is critical for brain function and suggest that the Syt IV mutation affects hippocampal-dependent learning and memory, as well as motor coordination.

Survival motor neuron protein modulates neuron-specific apoptosis

Spinal muscular atrophy (SMA) is attributed to mutations in the SMN1 gene, leading to loss of spinal cord motor neurons. The neurotropic Sindbis virus vector system was used to investigate a role for the survival motor neuron (SMN) protein in regulating neuronal apoptosis. Here we show that SMN protects primary neurons and differentiated neuron-like stem cells, but not cultured cell lines from virus-induced apoptotic death. SMN also protects neurons in vivo and increases survival of virus-infected mice. SMN mutants (SMNΔ7 and SMN-Y272C) found in patients with SMA not only lack antiapoptotic activity but also are potently proapoptotic, causing increased neuronal apoptosis and animal mortality. Full-length SMN is proteolytically processed in brains undergoing apoptosis or after ischemic injury. Mutation of an Asp-252 of SMN abolished cleavage of SMN and increased the antiapoptotic function of full-length SMN in neurons. Taken together, deletions or mutations of the C terminus of SMN that result from proteolysis, splicing (SMNΔ7), or germ-line mutations (e.g., Y272C), produce a proapoptotic form of SMN that may contribute to neuronal death in SMA and perhaps other neurodegenerative disorders.

Recovery of hearing and vocal behavior after hair-cell regeneration

Postmitotic hair-cell regeneration in the inner ear of birds provides an opportunity to study the effect of renewed auditory input on auditory perception, vocal production, and vocal learning in a vertebrate. We used behavioral conditioning to test both perception and vocal production in a small Australian parrot, the budgerigar. Results show that both auditory perception and vocal production are disrupted when hair cells are damaged or lost but that these behaviors return to near normal over time. Precision in vocal production completely recovers well before recovery of full auditory function. These results may have particular relevance for understanding the relation between hearing loss and human speech production especially where there is consideration of an auditory prosthetic device. The present results show, at least for a bird, that even limited recovery of auditory input soon after deafening can support full recovery of vocal precision.

Spontaneous corticospinal axonal plasticity and functional recovery after adult central nervous system injury

Although it is believed that little recovery occurs after adult mammalian spinal cord injury, in fact significant spontaneous functional improvement commonly occurs after spinal cord injury in humans. To investigate potential mechanisms underlying spontaneous recovery, lesions of defined components of the corticospinal motor pathway were made in adult rats in the rostral cervical spinal cord or caudal medulla. Following complete lesions of the dorsal corticospinal motor pathway, which contains more than 95% of all corticospinal axons, spontaneous sprouting from the ventral corticospinal tract occurred onto medial motoneuron pools in the cervical spinal cord; this sprouting was paralleled by functional recovery. Combined lesions of both dorsal and ventral corticospinal tract components eliminated sprouting and functional recovery. In addition, functional recovery was also abolished if dorsal corticospinal tract lesions were followed 5 weeks later by ventral corticospinal tract lesions. We found extensive spontaneous structural plasticity as a mechanism correlating with functional recovery in motor systems in the adult central nervous system. Experimental enhancement of spontaneous plasticity may be useful to promote further recovery after adult central nervous system injury.