Lanthanide luminescent logic gate mimics in soft matter: [H(+)] and [F(-)] dual-input device in a polymer gel with potential for selective component release

The non-covalent incorporation of responsive luminescent lanthanide, Ln(iii), complexes with orthogonal outputs from Eu(iii) and Tb(iii) in a gel matrix allows for in situ logic operation with colorimetric outputs. Herein, we report an exemplar system with two inputs ([H(+)] and [F(-)]) within a p(HEMA-co-MMA) polymer organogel acting as a dual-responsive device and identify future potential for such systems.

Energy versus data integrity trade-offs in embedded high-density logic compatible dynamic memories

Current variation aware design methodologies, tuned for worst-case scenarios, are becoming increasingly pessimistic from the perspective of power and performance. A good example of such pessimism is setting the refresh rate of DRAMs according to the worst-case access statistics, thereby resulting in very frequent refresh cycles, which are responsible for the majority of the standby power consumption of these memories. However, such a high refresh rate may not be required, either due to extremely low probability of the actual occurrence of such a worst-case, or due to the inherent error resilient nature of many applications that can tolerate a certain number of potential failures. In this paper, we exploit and quantify the possibilities that exist in dynamic memory design by shifting to the so-called approximate computing paradigm in order to save power and enhance yield at no cost. The statistical characteristics of the retention time in dynamic memories were revealed by studying a fabricated 2kb CMOS compatible embedded DRAM (eDRAM) memory array based on gain-cells. Measurements show that up to 73% of the retention power can be saved by altering the refresh time and setting it such that a small number of failures is allowed. We show that these savings can be further increased by utilizing known circuit techniques, such as body biasing, which can help, not only in extending, but also in preferably shaping the retention time distribution. Our approach is one of the first attempts to access the data integrity and energy tradeoffs achieved in eDRAMs for utilizing them in error resilient applications and can prove helpful in the anticipated shift to approximate computing.

Passive Intermodulation in Distributed Circuits with Cascaded Discrete Nonlinearities

The principle aspects of passive intermodulation (PIM) characterisation in distributed printed circuits with cascaded lumped nonlinearities are presented. Mechanisms of PIM generations have been investigated experimentally and modelled using the formalism of X-parameters. The devised equivalent circuit models are applied to the analysis of microstrip lines with distributed and cascaded lumped sources of nonlinearity. The dynamic measurements have revealed that PIM generation rates in straight and meandered microstrip lines differ and significantly deviate from those expected for the respective discrete sources of nonlinearity. The obtained results indicate that multiple physical sources of nonlinearity contribute to PIM generation in printed circuits. Finally, it is demonstrated that the electrical discontinuities can have significant effect on the overall PIM response of the distributed passive circuits and cause PIM product leakage and parasitic coupling between isolated circuit elements.

Logic Brightens My Day: Evidence for Implicit Sensitivity to Logical Validity.

A key assumption of dual process theory is that reasoning is an explicit, effortful, deliberative process. The present study offers evidence for an implicit, possibly intuitive component of reasoning. Participants were shown sentences embedded in logically valid or invalid arguments. Participants were not asked to reason but instead rated the sentences for liking (Experiment 1) and physical brightness (Experiments 2-3). Sentences that followed logically from preceding sentences were judged to be more likable and brighter. Two other factors thought to be linked to implicit processing-sentence believability and facial expression-had similar effects on liking and brightness ratings. The authors conclude that sensitivity to logical structure was implicit, occurring potentially automatically and outside of awareness. They discuss the results within a fluency misattribution framework and make reference to the literature on discourse comprehension. 

Logic Programming and Artificial Neural Networks in Pharmacological Screening of Schinus Essential Oils

Some plants of genus Schinus have been used in the folk medicine as topical antiseptic, digestive, purgative, diuretic, analgesic or antidepressant, and also for respiratory and urinary infections. Chemical composition of essential oils of S. molle and S. terebinthifolius had been evaluated and presented high variability according with the part of the plant studied and with the geographic and climatic regions. The pharmacological properties, namely antimicrobial, anti-tumoural and anti-inflammatory activities are conditioned by chemical composition of essential oils. Taking into account the difficulty to infer the pharmacological properties of Schinus essential oils without hard experimental approach, this work will focus on the development of a decision support system, in terms of its knowledge representation and reasoning procedures, under a formal framework based on Logic Programming, complemented with an approach to computing centered on Artificial Neural Networks and the respective Degree-of-Confidence that one has on such an occurrence.

Synchronisation in high-performance integrated circuits

A distribui ção de um sinal relógio, com elevada precisão espacial (baixo skew) e temporal (baixo jitter ), em sistemas sí ncronos de alta velocidade tem-se revelado uma tarefa cada vez mais demorada e complexa devido ao escalonamento da tecnologia. Com a diminuição das dimensões dos dispositivos e a integração crescente de mais funcionalidades nos Circuitos Integrados (CIs), a precisão associada as transições do sinal de relógio tem sido cada vez mais afectada por varia ções de processo, tensão e temperatura. Esta tese aborda o problema da incerteza de rel ogio em CIs de alta velocidade, com o objetivo de determinar os limites do paradigma de desenho sí ncrono. Na prossecu ção deste objectivo principal, esta tese propõe quatro novos modelos de incerteza com âmbitos de aplicação diferentes. O primeiro modelo permite estimar a incerteza introduzida por um inversor est atico CMOS, com base em parâmetros simples e su cientemente gen éricos para que possa ser usado na previsão das limitações temporais de circuitos mais complexos, mesmo na fase inicial do projeto. O segundo modelo, permite estimar a incerteza em repetidores com liga ções RC e assim otimizar o dimensionamento da rede de distribui ção de relógio, com baixo esfor ço computacional. O terceiro modelo permite estimar a acumula ção de incerteza em cascatas de repetidores. Uma vez que este modelo tem em considera ção a correla ção entre fontes de ruí do, e especialmente util para promover t ecnicas de distribui ção de rel ogio e de alimentação que possam minimizar a acumulação de incerteza. O quarto modelo permite estimar a incerteza temporal em sistemas com m ultiplos dom ínios de sincronismo. Este modelo pode ser facilmente incorporado numa ferramenta autom atica para determinar a melhor topologia para uma determinada aplicação ou para avaliar a tolerância do sistema ao ru ído de alimentação. Finalmente, usando os modelos propostos, são discutidas as tendências da precisão de rel ogio. Conclui-se que os limites da precisão do rel ogio são, em ultima an alise, impostos por fontes de varia ção dinâmica que se preveem crescentes na actual l ogica de escalonamento dos dispositivos. Assim sendo, esta tese defende a procura de solu ções em outros ní veis de abstração, que não apenas o ní vel f sico, que possam contribuir para o aumento de desempenho dos CIs e que tenham um menor impacto nos pressupostos do paradigma de desenho sí ncrono.

Nonlinear behavioral modeling of mixed signal RF-digital I/O devices

Esta tese investiga a caracterização (e modelação) de dispositivos que realizam o interface entre os domínios digital e analógico, tal como os buffers de saída dos circuitos integrados (CI). Os terminais sem fios da atualidade estão a ser desenvolvidos tendo em vista o conceito de rádio-definido-por-software introduzido por Mitola. Idealmente esta arquitetura tira partido de poderosos processadores e estende a operação dos blocos digitais o mais próximo possível da antena. Neste sentido, não é de estranhar que haja uma crescente preocupação, no seio da comunidade científica, relativamente à caracterização dos blocos que fazem o interface entre os domínios analógico e digital, sendo os conversores digital-analógico e analógico-digital dois bons exemplos destes circuitos. Dentro dos circuitos digitais de alta velocidade, tais como as memórias Flash, um papel semelhante é desempenhado pelos buffers de saída. Estes realizam o interface entre o domínio digital (núcleo lógico) e o domínio analógico (encapsulamento dos CI e parasitas associados às linhas de transmissão), determinando a integridade do sinal transmitido. Por forma a acelerar a análise de integridade do sinal, aquando do projeto de um CI, é fundamental ter modelos que são simultaneamente eficientes (em termos computacionais) e precisos. Tipicamente a extração/validação dos modelos para buffers de saída é feita usando dados obtidos da simulação de um modelo detalhado (ao nível do transístor) ou a partir de resultados experimentais. A última abordagem não envolve problemas de propriedade intelectual; contudo é raramente mencionada na literatura referente à caracterização de buffers de saída. Neste sentido, esta tese de Doutoramento foca-se no desenvolvimento de uma nova configuração de medição para a caracterização e modelação de buffers de saída de alta velocidade, com a natural extensão aos dispositivos amplificadores comutados RF-CMOS. Tendo por base um procedimento experimental bem definido, um modelo estado-da-arte é extraído e validado. A configuração de medição desenvolvida aborda não apenas a integridade dos sinais de saída mas também do barramento de alimentação. Por forma a determinar a sensibilidade das quantias estimadas (tensão e corrente) aos erros presentes nas diversas variáveis associadas ao procedimento experimental, uma análise de incerteza é também apresentada.

A frequency-domain receiver for asynchronous systems employing CP-assisted DS-CDMA schemes

In this paper we consider the uplink transmission within CP-assisted (Cyclic Pre¯x) DS-CDMA (Direct Sequence Code Division Multiple Access) systems and we present a frequency-domain MUD (MultiUser Detection) receiver with iterative estimation and compensation of residual frequency errors. The proposed receiver is suitable for broadband wireless systems, with performances that can be close to the single-user MFB (Matched Filter Bound), even for fully loaded systems and/or in the presence of strong interfering signals. The receiver is powerful enough for typical asynchronous scenarios, requiring only a coarse synchronization between users.

South Carolina/Common Pleas Court Circuits Meeting Benchmark

This is a list of the courts in all the circuits of South Carolina and the percentage of cases disposed of in 365 day or less. None of the courts met the 80% benchmark.

South Carolina/Common Pleas Court Circuits Meeting Benchmark ... as of August 31, 2014

This is a list of the courts in all the circuits of South Carolina and the percentage of cases disposed of in 365 day or less as of August 31, 2014. None of the courts met the 80% benchmark.

South Carolina/common pleas court circuits meeting benchmark 80% of Pending Docket 365 Days or Less From Placement on the Trial Docket as of February 28, 2015

This is a list of the courts in all the circuits of South Carolina and the percentage of cases disposed of in 365 day or less. Only three courts met the 80% benchmark.

South Carolina/general sessions court circuits meeting benchmark : 80% of pending docket 365 days or less as of February 28, 2015

This document provides statistics on criminal and general sessions courts meeting the benchmark of 80% of pending dockets broken down by circuits and counties.

South Carolina/family court circuits meeting benchmark : 80% of pending docket 365 days or less as of February 28, 2015

This is a diagram broken down by circuits of the percentage of family courts meeting the benchmark of 80% of disposing of cases within a year.

Categorising Asynchronous Discussion Threads: Improving the Quality of Student Learning

My paper will focus on the generative potential of categorising asynchronous discussion threads as one strategy for improving the quality of students’ learning in a blended learning module. The approach to categorisation is based on social network analysis using intuitively simple descriptors of message posting patterns e.g. passive facilitator, dominant facilitator, unresponsive star and formulaic discussion. The intention is to produce descriptively vivid illustrative examples of the categories and to begin to suggest affordances of the different participation patterns. Looking forward to the beginning of the next module, it is anticipated that discussion during the module of approaches to participating in asynchronous discussion will contribute to effective engagement patterns and deeper learning.