Mechanisms of transcription inhibition by 8-amino-adenosine

Nucleoside analogs are a class of chemotherapeutic agents with tremendous utility in treating viral infections and cancers. Traditional nucleoside analogs are DNA-directed. However, there is a new group of nucleoside analogs that induce cell death by a direct effect on RNA synthesis. The adenosine analog, 8-chloroadenosine, is incorporated into RNA and is currently in clinical trials. Another congener, 8-amino-adenosine has demonstrated toxicity in multiple myeloma cell lines. Like other nucleoside analogs, 8-amino-adenosine must be metabolized to its triphosphate to elicit a cytotoxic effect. Furthermore, 8-amino-adenosine causes a decline of the intracellular ATP pool and inhibits mRNA poly(A) adenylation. ^ Because of the previously known adenosine analog mechanism as well as the scope of the RNA directed nucleoside analog field, I hypothesized there are multiple mechanisms of transcription inhibition mediating 8-amino-adenosine-induced cell death. Prior to investigating these mechanisms, cell death by 8-amino-adenosine was characterized. 8-Amino-adenosine activates PARP cleavage and induces the caspase cascade. 8-Amino-adenosine increases Annexin V binding and the mitochondrial membrane permeability in wild-type MEF cells. In BAX/BAK deficient MEF cells, 8-amino-adenosine decreases the mitochondrial membrane permeability and induces autophagy. ^ Once cell death was characterized, the mechanisms of 8-amino-adenosine transcription inhibition were assessed. It was established that 8-aminoadenosine treatment causes 8-amino-ATP accumulation and decreases the intracellular ATP concentration, resulting in RNA synthesis inhibition. Several other mechanisms are identified. First, a relationship between ATP decline by 8-amino-adenosine or other known ATP synthesis inhibitors and RNA synthesis is established indicating that effects on cellular bioenergy, regardless of the mechanism of ATP decline, can decrease RNA synthesis. Second, 8-aminoadenosine treatment decreases the phosphorylation of serine residues on the RNA polymerase II C-terminal domain which regulates transcription initiation and elongation. Third, evidence is provided to demonstrate 8-amino-ATP is a substrate for RNA synthesis. Fourth, 8-amino-ATP is incorporated at the 3'-terminal position leading to chain termination. Finally, in vitro transcription assays show that 8-amino-ATP may compete with ATP to decrease de novo mRNA synthesis. Overall, this work demonstrates 8-amino-adenosine is a cytotoxic nucleoside analog that functions to inhibit RNA transcription through multiple mechanisms. ^

Chemical analysis and argon geochronology from dive SAR_1 on Cornacya seamount of the Sardinia Channel

Sarcya 1 dive explored a previously unknown 12 My old submerged volcano, labelled Cornacya. A well developed fracturation is characterised by the following directions: N 170 to N-S, N 20 to N 40, N 90 to N 120, N 50 to N 70, which corresponds to the fracturation pattern of the Sardinian margin. The sampled lavas exhibit features of shoshonitic suites of intermediate composition and include amphibole-and mica-bearing lamprophyric xenoliths which are geochemically similar to Ti-poor lamproites. Mica compositions reflect chemical exchanges between the lamprophyre and its shoshonitic host rock suggesting their simultaneous emplacement. Nd compositions of the Cornacya K-rich suite indicate that continental crust was largely involved in the genesis of these rocks. The spatial association of the lamprophyre with the shoshonitic rocks is geochemically similar to K-rich and TiO2-poor igneous suites, emplaced in post-collisional settings. Among shoshonitic rocks, sample SAR 1-01 has been dated at 12.6±0.3 My using the 40Ar/39Ar method with a laser microprobe on single grains. The age of the Cornacya shoshonitic suite is similar to that of the Sisco lamprophyre from Corsica, which similarly is located on the western margin of the Tyrrhenian Sea. Thus, the Cornacya shoshonitic rocks and their lamprophyric xenolith and the Sisco lamprophyre could represent post-collisional suites emplaced during the lithospheric extension of the Corsica-Sardinia block, just after its rotation and before the Tyrrhenian sea opening. Drilling on the Sardinia margin (ODP Leg 107) shows that the upper levels of the present day margin (Hole 654) suffered tectonic subsidence before the lower part (Hole 652). The structure of this lower part is interpreted as the result of an eastward migration of the extension during Late Miocene and Early Pliocene times. Data of Cornacya volcano are in good agreement with this model and provide good chronological constraints for the beginning of the phenomenon.

Chronostratigraphic framework at sites GeoB14403 and GeoB14414 from the Gela Basin, Sicily Channel

A multi-proxy chronological framework along with sequence-stratigraphic interpretations unveils composite Milankovitch cyclicity in the sedimentary records of the Last GlacialeInterglacial cycle at NE Gela Basin on the Sicilian continental margin. Chronostratigraphic data (including foraminifera-based eco-biostratigraphy and d18O records, tephrochronological markers and 14C AMS radiometric datings) was derived from the shallow-shelf drill sites GeoB14403 (54.6 m recovery) and GeoB14414 (27.5 m), collected with both gravity and drilled MeBo cores in 193 m and 146 m water depth, respectively. The recovered intervals record Marine Isotope Stages and Substages (MIS) from MIS 5 to MIS 1, thus comprising major stratigraphic parts of the progradational deposits that form the last 100-ka depositional sequence. Calibration of shelf sedimentary units with borehole stratigraphies indicates the impact of higher-frequency (20-ka) sea level cycles punctuating this 100-ka cycle. This becomes most evident in the alternation of thick interstadial highstand (HST) wedges and thinner glacial forced-regression (FSST) units mirroring seaward shifts in coastal progradation. Albeit their relatively short-lived depositional phase, these subordinate HST units form the bulk of the 100-ka depositional sequence. Two mechanisms are proposed that likely account for enhanced sediment accumulation ratios (SAR) of up to 200 cm/ka during these intervals: (1) intensified activity of deep and intermediate Levantine Intermediate Water (LIW) associated to the drowning of Mediterranean shelves, and (2) amplified sediment flux along the flooded shelf in response to hyperpycnal plumes that generate through extreme precipitation events during overall arid conditions. Equally, the latter mechanism is thought to be at the origin of undulated features resolved in the acoustic records of MIS 5 Interstadials, which bear a striking resemblance to modern equivalents forming on late-Holocene prodeltas of other Mediterranean shallow-shelf settings.

A common mechanism of defective channel trafficking underlying DFNA2 hearing loss result in different cell surface expression levels of KCNQ4 mutants

KCNQ4 mutations underlie DFNA2, a subtype of autosomal dominant hearing loss. We had previously identified the pore-region p.G296S mutation that impaired channel activity in two manners: it greatly reduced surface expression and abolished channel function. Moreover, G296S mutant exerted a strong dominant-negative effect on potassium currents by reducing the channel expression at the cell surface representing the first study to identify a trafficking-dependent dominant mechanism for the loss of KCNQ4 channel function in DFNA2. Here, we have investigated the pathogenic mechanism associated with all the described KCNQ4 mutations (F182L, W242X, E260K, D262V, L274H, W276S, L281S, G285C, G285S and G321S) that are located in different domains of the channel protein. F182L mutant showed a wild type-like cell-surface distribution in transiently transfected NIH3T3 fibroblasts and the recorded currents in Xenopus oocytes resembled those of the wild-type. The remaining KCNQ4 mutants abolished potassium currents, but displayed distinct levels of defective cell-surface expression in NIH3T3 as quantified by flow citometry. Co-localization studies revealed these mutants were retained in the ER, unless W242X, which showed a clear co-localization with Golgi apparatus. Interestingly, this mutation results in a truncated KCNQ4 protein at the S5 transmembrane domain, before the pore region, that escapes the protein quality control in the ER but does not reach the cell surface at normal levels. Currently we are investigating the trafficking behaviour and electrophysiological properties of several KCNQ4 truncated proteins artificially generated in order to identify specific motifs involved in channel retention/exportation. Altogether, our results indicate that a defect in KCNQ4 trafficking is the common mechanism underlying DFNA2

Developmental Expression of Kv Potassium Channels at the Axon Initial Segment of Cultured Hippocampal Neurons

Axonal outgrowth and the formation of the axon initial segment (AIS) are early events in the acquisition of neuronal polarity. The AIS is characterized by a high concentration of voltage-dependent sodium and potassium channels. However, the specific ion channel subunits present and their precise localization in this axonal subdomain vary both during development and among the types of neurons, probably determining their firing characteristics in response to stimulation. Here, we characterize the developmental expression of different subfamilies of voltage-gated potassium channels in the AISs of cultured mouse hippocampal neurons, including subunits Kv1.2, Kv2.2 and Kv7.2. In contrast to the early appearance of voltage-gated sodium channels and the Kv7.2 subunit at the AIS, Kv1.2 and Kv2.2 subunits were tethered at the AIS only after 10 days in vitro. Interestingly, we observed different patterns of Kv1.2 and Kv2.2 subunit expression, with each confined to distinct neuronal populations. The accumulation of Kv1.2 and Kv2.2 subunits at the AIS was dependent on ankyrin G tethering, it was not affected by disruption of the actin cytoskeleton and it was resistant to detergent extraction, as described previously for other AIS proteins. This distribution of potassium channels in the AIS further emphasizes the heterogeneity of this structure in different neuronal populations, as proposed previously, and suggests corresponding differences in action potential regulation.

Side-Channel Attack Protection Techniques in FPGA Systems using Enhanced Dual-Rail Solutions

Esta tesis doctoral se centra principalmente en técnicas de ataque y contramedidas relacionadas con ataques de canal lateral (SCA por sus siglas en inglés), que han sido propuestas dentro del campo de investigación académica desde hace 17 años. Las investigaciones relacionadas han experimentado un notable crecimiento en las últimas décadas, mientras que los diseños enfocados en la protección sólida y eficaz contra dichos ataques aún se mantienen como un tema de investigación abierto, en el que se necesitan iniciativas más confiables para la protección de la información persona de empresa y de datos nacionales. El primer uso documentado de codificación secreta se remonta a alrededor de 1700 B.C., cuando los jeroglíficos del antiguo Egipto eran descritos en las inscripciones. La seguridad de la información siempre ha supuesto un factor clave en la transmisión de datos relacionados con inteligencia diplomática o militar. Debido a la evolución rápida de las técnicas modernas de comunicación, soluciones de cifrado se incorporaron por primera vez para garantizar la seguridad, integridad y confidencialidad de los contextos de transmisión a través de cables sin seguridad o medios inalámbricos. Debido a las restricciones de potencia de cálculo antes de la era del ordenador, la técnica de cifrado simple era un método más que suficiente para ocultar la información. Sin embargo, algunas vulnerabilidades algorítmicas pueden ser explotadas para restaurar la regla de codificación sin mucho esfuerzo. Esto ha motivado nuevas investigaciones en el área de la criptografía, con el fin de proteger el sistema de información ante sofisticados algoritmos. Con la invención de los ordenadores se ha acelerado en gran medida la implementación de criptografía segura, que ofrece resistencia eficiente encaminada a obtener mayores capacidades de computación altamente reforzadas. Igualmente, sofisticados cripto-análisis han impulsado las tecnologías de computación. Hoy en día, el mundo de la información ha estado involucrado con el campo de la criptografía, enfocada a proteger cualquier campo a través de diversas soluciones de cifrado. Estos enfoques se han fortalecido debido a la unificación optimizada de teorías matemáticas modernas y prácticas eficaces de hardware, siendo posible su implementación en varias plataformas (microprocesador, ASIC, FPGA, etc.). Las necesidades y requisitos de seguridad en la industria son las principales métricas de conducción en el diseño electrónico, con el objetivo de promover la fabricación de productos de gran alcance sin sacrificar la seguridad de los clientes. Sin embargo, una vulnerabilidad en la implementación práctica encontrada por el Prof. Paul Kocher, et al en 1996 implica que un circuito digital es inherentemente vulnerable a un ataque no convencional, lo cual fue nombrado posteriormente como ataque de canal lateral, debido a su fuente de análisis. Sin embargo, algunas críticas sobre los algoritmos criptográficos teóricamente seguros surgieron casi inmediatamente después de este descubrimiento. En este sentido, los circuitos digitales consisten típicamente en un gran número de celdas lógicas fundamentales (como MOS - Metal Oxide Semiconductor), construido sobre un sustrato de silicio durante la fabricación. La lógica de los circuitos se realiza en función de las innumerables conmutaciones de estas células. Este mecanismo provoca inevitablemente cierta emanación física especial que puede ser medida y correlacionada con el comportamiento interno del circuito. SCA se puede utilizar para revelar datos confidenciales (por ejemplo, la criptografía de claves), analizar la arquitectura lógica, el tiempo e incluso inyectar fallos malintencionados a los circuitos que se implementan en sistemas embebidos, como FPGAs, ASICs, o tarjetas inteligentes. Mediante el uso de la comparación de correlación entre la cantidad de fuga estimada y las fugas medidas de forma real, información confidencial puede ser reconstruida en mucho menos tiempo y computación. Para ser precisos, SCA básicamente cubre una amplia gama de tipos de ataques, como los análisis de consumo de energía y radiación ElectroMagnética (EM). Ambos se basan en análisis estadístico y, por lo tanto, requieren numerosas muestras. Los algoritmos de cifrado no están intrínsecamente preparados para ser resistentes ante SCA. Es por ello que se hace necesario durante la implementación de circuitos integrar medidas que permitan camuflar las fugas a través de "canales laterales". Las medidas contra SCA están evolucionando junto con el desarrollo de nuevas técnicas de ataque, así como la continua mejora de los dispositivos electrónicos. Las características físicas requieren contramedidas sobre la capa física, que generalmente se pueden clasificar en soluciones intrínsecas y extrínsecas. Contramedidas extrínsecas se ejecutan para confundir la fuente de ataque mediante la integración de ruido o mala alineación de la actividad interna. Comparativamente, las contramedidas intrínsecas están integradas en el propio algoritmo, para modificar la aplicación con el fin de minimizar las fugas medibles, o incluso hacer que dichas fugas no puedan ser medibles. Ocultación y Enmascaramiento son dos técnicas típicas incluidas en esta categoría. Concretamente, el enmascaramiento se aplica a nivel algorítmico, para alterar los datos intermedios sensibles con una máscara de manera reversible. A diferencia del enmascaramiento lineal, las operaciones no lineales que ampliamente existen en criptografías modernas son difíciles de enmascarar. Dicho método de ocultación, que ha sido verificado como una solución efectiva, comprende principalmente la codificación en doble carril, que está ideado especialmente para aplanar o eliminar la fuga dependiente de dato en potencia o en EM. En esta tesis doctoral, además de la descripción de las metodologías de ataque, se han dedicado grandes esfuerzos sobre la estructura del prototipo de la lógica propuesta, con el fin de realizar investigaciones enfocadas a la seguridad sobre contramedidas de arquitectura a nivel lógico. Una característica de SCA reside en el formato de las fuentes de fugas. Un típico ataque de canal lateral se refiere al análisis basado en la potencia, donde la capacidad fundamental del transistor MOS y otras capacidades parásitas son las fuentes esenciales de fugas. Por lo tanto, una lógica robusta resistente a SCA debe eliminar o mitigar las fugas de estas micro-unidades, como las puertas lógicas básicas, los puertos I/O y las rutas. Las herramientas EDA proporcionadas por los vendedores manipulan la lógica desde un nivel más alto, en lugar de realizarlo desde el nivel de puerta, donde las fugas de canal lateral se manifiestan. Por lo tanto, las implementaciones clásicas apenas satisfacen estas necesidades e inevitablemente atrofian el prototipo. Por todo ello, la implementación de un esquema de diseño personalizado y flexible ha de ser tomado en cuenta. En esta tesis se presenta el diseño y la implementación de una lógica innovadora para contrarrestar SCA, en la que se abordan 3 aspectos fundamentales: I. Se basa en ocultar la estrategia sobre el circuito en doble carril a nivel de puerta para obtener dinámicamente el equilibrio de las fugas en las capas inferiores; II. Esta lógica explota las características de la arquitectura de las FPGAs, para reducir al mínimo el gasto de recursos en la implementación; III. Se apoya en un conjunto de herramientas asistentes personalizadas, incorporadas al flujo genérico de diseño sobre FPGAs, con el fin de manipular los circuitos de forma automática. El kit de herramientas de diseño automático es compatible con la lógica de doble carril propuesta, para facilitar la aplicación práctica sobre la familia de FPGA del fabricante Xilinx. En este sentido, la metodología y las herramientas son flexibles para ser extendido a una amplia gama de aplicaciones en las que se desean obtener restricciones mucho más rígidas y sofisticadas a nivel de puerta o rutado. En esta tesis se realiza un gran esfuerzo para facilitar el proceso de implementación y reparación de lógica de doble carril genérica. La viabilidad de las soluciones propuestas es validada mediante la selección de algoritmos criptográficos ampliamente utilizados, y su evaluación exhaustiva en comparación con soluciones anteriores. Todas las propuestas están respaldadas eficazmente a través de ataques experimentales con el fin de validar las ventajas de seguridad del sistema. El presente trabajo de investigación tiene la intención de cerrar la brecha entre las barreras de implementación y la aplicación efectiva de lógica de doble carril. En esencia, a lo largo de esta tesis se describirá un conjunto de herramientas de implementación para FPGAs que se han desarrollado para trabajar junto con el flujo de diseño genérico de las mismas, con el fin de lograr crear de forma innovadora la lógica de doble carril. Un nuevo enfoque en el ámbito de la seguridad en el cifrado se propone para obtener personalización, automatización y flexibilidad en el prototipo de circuito de bajo nivel con granularidad fina. Las principales contribuciones del presente trabajo de investigación se resumen brevemente a continuación: Lógica de Precharge Absorbed-DPL logic: El uso de la conversión de netlist para reservar LUTs libres para ejecutar la señal de precharge y Ex en una lógica DPL. Posicionamiento entrelazado Row-crossed con pares idénticos de rutado en redes de doble carril, lo que ayuda a aumentar la resistencia frente a la medición EM selectiva y mitigar los impactos de las variaciones de proceso. Ejecución personalizada y herramientas de conversión automática para la generación de redes idénticas para la lógica de doble carril propuesta. (a) Para detectar y reparar conflictos en las conexiones; (b) Detectar y reparar las rutas asimétricas. (c) Para ser utilizado en otras lógicas donde se requiere un control estricto de las interconexiones en aplicaciones basadas en Xilinx. Plataforma CPA de pruebas personalizadas para el análisis de EM y potencia, incluyendo la construcción de dicha plataforma, el método de medición y análisis de los ataques. Análisis de tiempos para cuantificar los niveles de seguridad. División de Seguridad en la conversión parcial de un sistema de cifrado complejo para reducir los costes de la protección. Prueba de concepto de un sistema de calefacción auto-adaptativo para mitigar los impactos eléctricos debido a la variación del proceso de silicio de manera dinámica. La presente tesis doctoral se encuentra organizada tal y como se detalla a continuación: En el capítulo 1 se abordan los fundamentos de los ataques de canal lateral, que abarca desde conceptos básicos de teoría de modelos de análisis, además de la implementación de la plataforma y la ejecución de los ataques. En el capítulo 2 se incluyen las estrategias de resistencia SCA contra los ataques de potencia diferencial y de EM. Además de ello, en este capítulo se propone una lógica en doble carril compacta y segura como contribución de gran relevancia, así como también se presentará la transformación lógica basada en un diseño a nivel de puerta. Por otra parte, en el Capítulo 3 se abordan los desafíos relacionados con la implementación de lógica en doble carril genérica. Así mismo, se describirá un flujo de diseño personalizado para resolver los problemas de aplicación junto con una herramienta de desarrollo automático de aplicaciones propuesta, para mitigar las barreras de diseño y facilitar los procesos. En el capítulo 4 se describe de forma detallada la elaboración e implementación de las herramientas propuestas. Por otra parte, la verificación y validaciones de seguridad de la lógica propuesta, así como un sofisticado experimento de verificación de la seguridad del rutado, se describen en el capítulo 5. Por último, un resumen de las conclusiones de la tesis y las perspectivas como líneas futuras se incluyen en el capítulo 6. Con el fin de profundizar en el contenido de la tesis doctoral, cada capítulo se describe de forma más detallada a continuación: En el capítulo 1 se introduce plataforma de implementación hardware además las teorías básicas de ataque de canal lateral, y contiene principalmente: (a) La arquitectura genérica y las características de la FPGA a utilizar, en particular la Xilinx Virtex-5; (b) El algoritmo de cifrado seleccionado (un módulo comercial Advanced Encryption Standard (AES)); (c) Los elementos esenciales de los métodos de canal lateral, que permiten revelar las fugas de disipación correlacionadas con los comportamientos internos; y el método para recuperar esta relación entre las fluctuaciones físicas en los rastros de canal lateral y los datos internos procesados; (d) Las configuraciones de las plataformas de pruebas de potencia / EM abarcadas dentro de la presente tesis. El contenido de esta tesis se amplia y profundiza a partir del capítulo 2, en el cual se abordan varios aspectos claves. En primer lugar, el principio de protección de la compensación dinámica de la lógica genérica de precarga de doble carril (Dual-rail Precharge Logic-DPL) se explica mediante la descripción de los elementos compensados a nivel de puerta. En segundo lugar, la lógica PA-DPL es propuesta como aportación original, detallando el protocolo de la lógica y un caso de aplicación. En tercer lugar, dos flujos de diseño personalizados se muestran para realizar la conversión de doble carril. Junto con ello, se aclaran las definiciones técnicas relacionadas con la manipulación por encima de la netlist a nivel de LUT. Finalmente, una breve discusión sobre el proceso global se aborda en la parte final del capítulo. El Capítulo 3 estudia los principales retos durante la implementación de DPLs en FPGAs. El nivel de seguridad de las soluciones de resistencia a SCA encontradas en el estado del arte se ha degenerado debido a las barreras de implantación a través de herramientas EDA convencionales. En el escenario de la arquitectura FPGA estudiada, se discuten los problemas de los formatos de doble carril, impactos parásitos, sesgo tecnológico y la viabilidad de implementación. De acuerdo con estas elaboraciones, se plantean dos problemas: Cómo implementar la lógica propuesta sin penalizar los niveles de seguridad, y cómo manipular un gran número de celdas y automatizar el proceso. El PA-DPL propuesto en el capítulo 2 se valida con una serie de iniciativas, desde características estructurales como doble carril entrelazado o redes de rutado clonadas, hasta los métodos de aplicación tales como las herramientas de personalización y automatización de EDA. Por otra parte, un sistema de calefacción auto-adaptativo es representado y aplicado a una lógica de doble núcleo, con el fin de ajustar alternativamente la temperatura local para equilibrar los impactos negativos de la variación del proceso durante la operación en tiempo real. El capítulo 4 se centra en los detalles de la implementación del kit de herramientas. Desarrollado sobre una API third-party, el kit de herramientas personalizado es capaz de manipular los elementos de la lógica de circuito post P&R ncd (una versión binaria ilegible del xdl) convertido al formato XDL Xilinx. El mecanismo y razón de ser del conjunto de instrumentos propuestos son cuidadosamente descritos, que cubre la detección de enrutamiento y los enfoques para la reparación. El conjunto de herramientas desarrollado tiene como objetivo lograr redes de enrutamiento estrictamente idénticos para la lógica de doble carril, tanto para posicionamiento separado como para el entrelazado. Este capítulo particularmente especifica las bases técnicas para apoyar las implementaciones en los dispositivos de Xilinx y su flexibilidad para ser utilizado sobre otras aplicaciones. El capítulo 5 se enfoca en la aplicación de los casos de estudio para la validación de los grados de seguridad de la lógica propuesta. Se discuten los problemas técnicos detallados durante la ejecución y algunas nuevas técnicas de implementación. (a) Se discute el impacto en el proceso de posicionamiento de la lógica utilizando el kit de herramientas propuesto. Diferentes esquemas de implementación, tomando en cuenta la optimización global en seguridad y coste, se verifican con los experimentos con el fin de encontrar los planes de posicionamiento y reparación optimizados; (b) las validaciones de seguridad se realizan con los métodos de correlación y análisis de tiempo; (c) Una táctica asintótica se aplica a un núcleo AES sobre BCDL estructurado para validar de forma sofisticada el impacto de enrutamiento sobre métricas de seguridad; (d) Los resultados preliminares utilizando el sistema de calefacción auto-adaptativa sobre la variación del proceso son mostrados; (e) Se introduce una aplicación práctica de las herramientas para un diseño de cifrado completa. Capítulo 6 incluye el resumen general del trabajo presentado dentro de esta tesis doctoral. Por último, una breve perspectiva del trabajo futuro se expone, lo que puede ampliar el potencial de utilización de las contribuciones de esta tesis a un alcance más allá de los dominios de la criptografía en FPGAs. ABSTRACT This PhD thesis mainly concentrates on countermeasure techniques related to the Side Channel Attack (SCA), which has been put forward to academic exploitations since 17 years ago. The related research has seen a remarkable growth in the past decades, while the design of solid and efficient protection still curiously remain as an open research topic where more reliable initiatives are required for personal information privacy, enterprise and national data protections. The earliest documented usage of secret code can be traced back to around 1700 B.C., when the hieroglyphs in ancient Egypt are scribed in inscriptions. Information security always gained serious attention from diplomatic or military intelligence transmission. Due to the rapid evolvement of modern communication technique, crypto solution was first incorporated by electronic signal to ensure the confidentiality, integrity, availability, authenticity and non-repudiation of the transmitted contexts over unsecure cable or wireless channels. Restricted to the computation power before computer era, simple encryption tricks were practically sufficient to conceal information. However, algorithmic vulnerabilities can be excavated to restore the encoding rules with affordable efforts. This fact motivated the development of modern cryptography, aiming at guarding information system by complex and advanced algorithms. The appearance of computers has greatly pushed forward the invention of robust cryptographies, which efficiently offers resistance relying on highly strengthened computing capabilities. Likewise, advanced cryptanalysis has greatly driven the computing technologies in turn. Nowadays, the information world has been involved into a crypto world, protecting any fields by pervasive crypto solutions. These approaches are strong because of the optimized mergence between modern mathematical theories and effective hardware practices, being capable of implement crypto theories into various platforms (microprocessor, ASIC, FPGA, etc). Security needs from industries are actually the major driving metrics in electronic design, aiming at promoting the construction of systems with high performance without sacrificing security. Yet a vulnerability in practical implementation found by Prof. Paul Kocher, et al in 1996 implies that modern digital circuits are inherently vulnerable to an unconventional attack approach, which was named as side-channel attack since then from its analysis source. Critical suspicions to theoretically sound modern crypto algorithms surfaced almost immediately after this discovery. To be specifically, digital circuits typically consist of a great number of essential logic elements (as MOS - Metal Oxide Semiconductor), built upon a silicon substrate during the fabrication. Circuit logic is realized relying on the countless switch actions of these cells. This mechanism inevitably results in featured physical emanation that can be properly measured and correlated with internal circuit behaviors. SCAs can be used to reveal the confidential data (e.g. crypto-key), analyze the logic architecture, timing and even inject malicious faults to the circuits that are implemented in hardware system, like FPGA, ASIC, smart Card. Using various comparison solutions between the predicted leakage quantity and the measured leakage, secrets can be reconstructed at much less expense of time and computation. To be precisely, SCA basically encloses a wide range of attack types, typically as the analyses of power consumption or electromagnetic (EM) radiation. Both of them rely on statistical analyses, and hence require a number of samples. The crypto algorithms are not intrinsically fortified with SCA-resistance. Because of the severity, much attention has to be taken into the implementation so as to assemble countermeasures to camouflage the leakages via "side channels". Countermeasures against SCA are evolving along with the development of attack techniques. The physical characteristics requires countermeasures over physical layer, which can be generally classified into intrinsic and extrinsic vectors. Extrinsic countermeasures are executed to confuse the attacker by integrating noise, misalignment to the intra activities. Comparatively, intrinsic countermeasures are built into the algorithm itself, to modify the implementation for minimizing the measurable leakage, or making them not sensitive any more. Hiding and Masking are two typical techniques in this category. Concretely, masking applies to the algorithmic level, to alter the sensitive intermediate values with a mask in reversible ways. Unlike the linear masking, non-linear operations that widely exist in modern cryptographies are difficult to be masked. Approved to be an effective counter solution, hiding method mainly mentions dual-rail logic, which is specially devised for flattening or removing the data-dependent leakage in power or EM signatures. In this thesis, apart from the context describing the attack methodologies, efforts have also been dedicated to logic prototype, to mount extensive security investigations to countermeasures on logic-level. A characteristic of SCA resides on the format of leak sources. Typical side-channel attack concerns the power based analysis, where the fundamental capacitance from MOS transistors and other parasitic capacitances are the essential leak sources. Hence, a robust SCA-resistant logic must eliminate or mitigate the leakages from these micro units, such as basic logic gates, I/O ports and routings. The vendor provided EDA tools manipulate the logic from a higher behavioral-level, rather than the lower gate-level where side-channel leakage is generated. So, the classical implementations barely satisfy these needs and inevitably stunt the prototype. In this case, a customized and flexible design scheme is appealing to be devised. This thesis profiles an innovative logic style to counter SCA, which mainly addresses three major aspects: I. The proposed logic is based on the hiding strategy over gate-level dual-rail style to dynamically overbalance side-channel leakage from lower circuit layer; II. This logic exploits architectural features of modern FPGAs, to minimize the implementation expenses; III. It is supported by a set of assistant custom tools, incorporated by the generic FPGA design flow, to have circuit manipulations in an automatic manner. The automatic design toolkit supports the proposed dual-rail logic, facilitating the practical implementation on Xilinx FPGA families. While the methodologies and the tools are flexible to be expanded to a wide range of applications where rigid and sophisticated gate- or routing- constraints are desired. In this thesis a great effort is done to streamline the implementation workflow of generic dual-rail logic. The feasibility of the proposed solutions is validated by selected and widely used crypto algorithm, for thorough and fair evaluation w.r.t. prior solutions. All the proposals are effectively verified by security experiments. The presented research work attempts to solve the implementation troubles. The essence that will be formalized along this thesis is that a customized execution toolkit for modern FPGA systems is developed to work together with the generic FPGA design flow for creating innovative dual-rail logic. A method in crypto security area is constructed to obtain customization, automation and flexibility in low-level circuit prototype with fine-granularity in intractable routings. Main contributions of the presented work are summarized next: Precharge Absorbed-DPL logic: Using the netlist conversion to reserve free LUT inputs to execute the Precharge and Ex signal in a dual-rail logic style. A row-crossed interleaved placement method with identical routing pairs in dual-rail networks, which helps to increase the resistance against selective EM measurement and mitigate the impacts from process variations. Customized execution and automatic transformation tools for producing identical networks for the proposed dual-rail logic. (a) To detect and repair the conflict nets; (b) To detect and repair the asymmetric nets. (c) To be used in other logics where strict network control is required in Xilinx scenario. Customized correlation analysis testbed for EM and power attacks, including the platform construction, measurement method and attack analysis. A timing analysis based method for quantifying the security grades. A methodology of security partitions of complex crypto systems for reducing the protection cost. A proof-of-concept self-adaptive heating system to mitigate electrical impacts over process variations in dynamic dual-rail compensation manner. The thesis chapters are organized as follows: Chapter 1 discusses the side-channel attack fundamentals, which covers from theoretic basics to analysis models, and further to platform setup and attack execution. Chapter 2 centers to SCA-resistant strategies against generic power and EM attacks. In this chapter, a major contribution, a compact and secure dual-rail logic style, will be originally proposed. The logic transformation based on bottom-layer design will be presented. Chapter 3 is scheduled to elaborate the implementation challenges of generic dual-rail styles. A customized design flow to solve the implementation problems will be described along with a self-developed automatic implementation toolkit, for mitigating the design barriers and facilitating the processes. Chapter 4 will originally elaborate the tool specifics and construction details. The implementation case studies and security validations for the proposed logic style, as well as a sophisticated routing verification experiment, will be described in Chapter 5. Finally, a summary of thesis conclusions and perspectives for future work are included in Chapter 5. To better exhibit the thesis contents, each chapter is further described next: Chapter 1 provides the introduction of hardware implementation testbed and side-channel attack fundamentals, and mainly contains: (a) The FPGA generic architecture and device features, particularly of Virtex-5 FPGA; (b) The selected crypto algorithm - a commercially and extensively used Advanced Encryption Standard (AES) module - is detailed; (c) The essentials of Side-Channel methods are profiled. It reveals the correlated dissipation leakage to the internal behaviors, and the method to recover this relationship between the physical fluctuations in side-channel traces and the intra processed data; (d) The setups of the power/EM testing platforms enclosed inside the thesis work are given. The content of this thesis is expanded and deepened from chapter 2, which is divided into several aspects. First, the protection principle of dynamic compensation of the generic dual-rail precharge logic is explained by describing the compensated gate-level elements. Second, the novel DPL is originally proposed by detailing the logic protocol and an implementation case study. Third, a couple of custom workflows are shown next for realizing the rail conversion. Meanwhile, the technical definitions that are about to be manipulated above LUT-level netlist are clarified. A brief discussion about the batched process is given in the final part. Chapter 3 studies the implementation challenges of DPLs in FPGAs. The security level of state-of-the-art SCA-resistant solutions are decreased due to the implementation barriers using conventional EDA tools. In the studied FPGA scenario, problems are discussed from dual-rail format, parasitic impact, technological bias and implementation feasibility. According to these elaborations, two problems arise: How to implement the proposed logic without crippling the security level; and How to manipulate a large number of cells and automate the transformation. The proposed PA-DPL in chapter 2 is legalized with a series of initiatives, from structures to implementation methods. Furthermore, a self-adaptive heating system is depicted and implemented to a dual-core logic, assumed to alternatively adjust local temperature for balancing the negative impacts from silicon technological biases on real-time. Chapter 4 centers to the toolkit system. Built upon a third-party Application Program Interface (API) library, the customized toolkit is able to manipulate the logic elements from post P&R circuit (an unreadable binary version of the xdl one) converted to Xilinx xdl format. The mechanism and rationale of the proposed toolkit are carefully convoyed, covering the routing detection and repairing approaches. The developed toolkit aims to achieve very strictly identical routing networks for dual-rail logic both for separate and interleaved placement. This chapter particularly specifies the technical essentials to support the implementations in Xilinx devices and the flexibility to be expanded to other applications. Chapter 5 focuses on the implementation of the case studies for validating the security grades of the proposed logic style from the proposed toolkit. Comprehensive implementation techniques are discussed. (a) The placement impacts using the proposed toolkit are discussed. Different execution schemes, considering the global optimization in security and cost, are verified with experiments so as to find the optimized placement and repair schemes; (b) Security validations are realized with correlation, timing methods; (c) A systematic method is applied to a BCDL structured module to validate the routing impact over security metric; (d) The preliminary results using the self-adaptive heating system over process variation is given; (e) A practical implementation of the proposed toolkit to a large design is introduced. Chapter 6 includes the general summary of the complete work presented inside this thesis. Finally, a brief perspective for the future work is drawn which might expand the potential utilization of the thesis contributions to a wider range of implementation domains beyond cryptography on FPGAs.

Sophisticated security verification on routing repaired balanced cell-based dual-rail logic against side channel analysis

Conventional dual-rail precharge logic suffers from difficult implementations of dual-rail structure for obtaining strict compensation between the counterpart rails. As a light-weight and high-speed dual-rail style, balanced cell-based dual-rail logic (BCDL) uses synchronised compound gates with global precharge signal to provide high resistance against differential power or electromagnetic analyses. BCDL can be realised from generic field programmable gate array (FPGA) design flows with constraints. However, routings still exist as concerns because of the deficient flexibility on routing control, which unfavourably results in bias between complementary nets in security-sensitive parts. In this article, based on a routing repair technique, novel verifications towards routing effect are presented. An 8 bit simplified advanced encryption processing (AES)-co-processor is executed that is constructed on block random access memory (RAM)-based BCDL in Xilinx Virtex-5 FPGAs. Since imbalanced routing are major defects in BCDL, the authors can rule out other influences and fairly quantify the security variants. A series of asymptotic correlation electromagnetic (EM) analyses are launched towards a group of circuits with consecutive routing schemes to be able to verify routing impact on side channel analyses. After repairing the non-identical routings, Mutual information analyses are executed to further validate the concrete security increase obtained from identical routing pairs in BCDL.

Induction of epithelial chloride secretion by channel-forming cryptdins 2 and 3

Salt and water secretion from intestinal epithelia requires enhancement of anion permeability across the apical membrane of Cl− secreting cells lining the crypt, the secretory gland of the intestine. Paneth cells located at the base of the small intestinal crypt release enteric defensins (cryptdins) apically into the lumen. Because cryptdins are homologs of molecules known to form anion conductive pores in phospholipid bilayers, we tested whether these endogenous antimicrobial peptides could act as soluble inducers of channel-like activity when applied to apical membranes of intestinal Cl− secreting epithelial cells in culture. Of the six peptides tested, cryptdins 2 and 3 stimulated Cl− secretion from polarized monolayers of human intestinal T84 cells. The response was reversible and dose dependent. In contrast, cryptdins 1, 4, 5, and 6 lacked this activity, demonstrating that Paneth cell defensins with very similar primary structures may exhibit a high degree of specificity in their capacity to elicit Cl− secretion. The secretory response was not inhibited by pretreatment with 8-phenyltheophyline (1 μM), or dependent on a concomitant rise in intracellular cAMP or cGMP, indicating that the apically located adenosine and guanylin receptors were not involved. On the other hand, cryptdin 3 elicited a secretory response that correlated with the establishment of an apically located anion conductive channel permeable to carboxyfluorescein. Thus cryptdins 2 and 3 can selectively permeabilize the apical cell membrane of epithelial cells in culture to elicit a physiologic Cl− secretory response. These data define the capability of cryptdins 2 and 3 to function as novel intestinal secretagogues, and suggest a previously undescribed mechanism of paracrine signaling that in vivo may involve the reversible formation of ion conductive channels by peptides released into the crypt microenvironment.

Type II regulatory subunits are not required for the anchoring-dependent modulation of Ca2+ channel activity by cAMP-dependent protein kinase

Preferential phosphorylation of specific proteins by cAMP-dependent protein kinase (PKA) may be mediated in part by the anchoring of PKA to a family of A-kinase anchor proteins (AKAPs) positioned in close proximity to target proteins. This interaction is thought to depend on binding of the type II regulatory (RII) subunits to AKAPs and is essential for PKA-dependent modulation of the α-amino-3-hydroxy-5-methyl-4-isoxazolepropionic acid/kainate receptor, the L-type Ca2+ channel, and the KCa channel. We hypothesized that the targeted disruption of the gene for the ubiquitously expressed RIIα subunit would reveal those tissues and signaling events that require anchored PKA. RIIα knockout mice appear normal and healthy. In adult skeletal muscle, RIα protein levels increased to partially compensate for the loss of RIIα. Nonetheless, a reduction in both catalytic (C) subunit protein levels and total kinase activity was observed. Surprisingly, the anchored PKA-dependent potentiation of the L-type Ca2+ channel in RIIα knockout skeletal muscle was unchanged compared with wild type although it was more sensitive to inhibitors of PKA–AKAP interactions. The C subunit colocalized with the L-type Ca2+ channel in transverse tubules in wild-type skeletal muscle and retained this localization in knockout muscle. The RIα subunit was shown to bind AKAPs, although with a 500-fold lower affinity than the RIIα subunit. The potentiation of the L-type Ca2+ channel in RIIα knockout mouse skeletal muscle suggests that, despite a lower affinity for AKAP binding, RIα is capable of physiologically relevant anchoring interactions.

Abnormalities of pancreatic islets by targeted expression of a dominant-negative KATP channel

ATP-sensitive K+ (KATP) channels are known to play important roles in various cellular functions, but the direct consequences of disruption of KATP channel function are largely unknown. We have generated transgenic mice expressing a dominant-negative form of the KATP channel subunit Kir6.2 (Kir6.2G132S, substitution of glycine with serine at position 132) in pancreatic beta cells. Kir6.2G132S transgenic mice develop hypoglycemia with hyperinsulinemia in neonates and hyperglycemia with hypoinsulinemia and decreased beta cell population in adults. KATP channel function is found to be impaired in the beta cells of transgenic mice with hyperglycemia. In addition, both resting membrane potential and basal calcium concentrations are shown to be significantly elevated in the beta cells of transgenic mice. We also found a high frequency of apoptotic beta cells before the appearance of hyperglycemia in the transgenic mice, suggesting that the KATP channel might play a significant role in beta cell survival in addition to its role in the regulation of insulin secretion.

Patch-clamp and amperometric recordings from norepinephrine transporters: Channel activity and voltage-dependent uptake

Transporters for the biogenic amines dopamine, norepinephrine, epinephrine and serotonin are largely responsible for transmitter inactivation after release. They also serve as high-affinity targets for a number of clinically relevant psychoactive agents, including antidepressants, cocaine, and amphetamines. Despite their prominent role in neurotransmitter inactivation and drug responses, we lack a clear understanding of the permeation pathway or regulation mechanisms at the single transporter level. The resolution of radiotracer-based flux techniques limits the opportunities to dissect these problems. Here we combine patch-clamp recording techniques with microamperometry to record the transporter-mediated flux of norepinephrine across isolated membrane patches. These data reveal voltage-dependent norepinephrine flux that correlates temporally with antidepressant-sensitive transporter currents in the same patch. Furthermore, we resolve unitary flux events linked with bursts of transporter channel openings. These findings indicate that norepinephrine transporters are capable of transporting neurotransmitter across the membrane in discrete shots containing hundreds of molecules. Amperometry is used widely to study neurotransmitter distribution and kinetics in the nervous system and to detect transmitter release during vesicular exocytosis. Of interest regarding the present application is the use of amperometry on inside-out patches with synchronous recording of flux and current. Thus, our results further demonstrate a powerful method to assess transporter function and regulation.

Genetically determined chloride-sensitive hypertension and stroke

The stroke-prone spontaneously hypertensive rat (SHRSP) is a genetically determined model of “salt-sensitive” stroke and hypertension whose full phenotypic expression is said to require a diet high in Na+ and low in K+. We tested the hypothesis that dietary Cl− determines the phenotypic expression of the SHRSP. In the SHRSP fed a normal NaCl diet, supplementing dietary K+ with KCl exacerbated hypertension, whereas supplementing either KHCO3 or potassium citrate (KB/C) attenuated hypertension, when blood pressure (BP) was measured radiotelemetrically, directly and continually. Supplemental KCl, but not KB/C, induced strokes, which occurred in all and only those rats in the highest quartiles of both BP and plasma renin activity (PRA). PRA was higher with KCl than with KB/C. These observations demonstrate that with respect to both severity of hypertension and frequency of stroke the phenotypic expression of the SHRSP is (i) either increased or decreased, depending on whether the anionic component of the potassium salt supplemented is, or is not, Cl−; (ii) increased by supplementing Cl− without supplementing Na+, and despite supplementing K+; and hence (iii) both selectively Cl−-sensitive and Cl−-determined. The observations suggest that in the SHRSP selectively supplemented with Cl− the likelihood of stroke depends on the extent to which both BP and PRA increase.

Construction of a high-affinity receptor site for dihydropyridine agonists and antagonists by single amino acid substitutions in a non-l-type Ca2+ channel

The activity of l-type Ca2+ channels is increased by dihydropyridine (DHP) agonists and inhibited by DHP antagonists, which are widely used in the therapy of cardiovascular disease. These drugs bind to the pore-forming α1 subunits of l-type Ca2+ channels. To define the minimal requirements for DHP binding and action, we constructed a high-affinity DHP receptor site by substituting a total of nine amino acid residues from DHP-sensitive l-type α1 subunits into the S5 and S6 transmembrane segments of domain III and the S6 transmembrane segment of domain IV of the DHP-insensitive P/Q-type α1A subunit. The resulting chimeric α1A/DHPS subunit bound DHP antagonists with high affinity in radioligand binding assays and was inhibited by DHP antagonists with high affinity in voltage clamp experiments. Substitution of these nine amino acid residues yielded 86% of the binding energy of the l-type α1C subunit and 92% of the binding energy of the l-type α1S subunit for the high-affinity DHP antagonist PN200–110. The activity of chimeric Ca2+ channels containing α1A/DHPS was increased 3.5 ± 0.7-fold by the DHP agonist (−)Bay K8644. The effect of this agonist was stereoselective as in l-type Ca2+ channels since (+) Bay K8644 inhibited the activity of α1A/DHPS. The results show conclusively that DHP agonists and antagonists bind to a single receptor site at which they have opposite effects on Ca2+ channel activity. This site contains essential components from both domains III and IV, consistent with a domain interface model for binding and allosteric modulation of Ca2+ channel activity by DHPs.

An Arabidopsis mutant that requires increased calcium for potassium nutrition and salt tolerance

Potassium (K+) nutrition and salt tolerance are key factors controlling plant productivity. However, the mechanisms by which plants regulate K+ nutrition and salt tolerance are poorly understood. We report here the identification of an Arabidopsis thaliana mutant, sos3 (salt-overly-sensitive 3), which is hypersensitive to Na+ and Li+ stresses. The mutation is recessive and is in a nuclear gene that maps to chromosome V. The sos3 mutation also renders the plant unable to grow on low K+. Surprisingly, increased extracellular Ca2+ suppresses the growth defect of sos3 plants on low K+ or 50 mM NaCl. In contrast, high concentrations of external Ca2+ do not rescue the growth of the salt-hypersensitive sos1 mutant on low K+ or 50 mM NaCl. Under NaCl stress, sos3 seedlings accumulated more Na+ and less K+ than the wild type. Increased external Ca2+ improved K+/Na+ selectivity of both sos3 and wild-type plants. However, this Ca2+ effect in sos3 is more than twice as much as that in the wild type. In addition to defining the first plant mutant with an altered calcium response, these results demonstrate that the SOS3 locus is essential for K+ nutrition, K+/Na+ selectivity, and salt tolerance in higher plants.