Performance of buildings with masonry infill walls during the 2011 Lorca earthquake

On Wednesday 11th May 2011 at 6:47 pm (local time) a magnitude 5.1 Mw earthquake occurred 6 km northeast of Lorca with a depth of around 5 km. As a consequence of the shallow depth and the small epicentral distance, important damage was produced in several masonry constructions and even led to the collapse of one of them. Pieces of the facades of several buildings fell down onto the sidewalk, being one of the reasons for the killing of a total of 9 people. The objective of this paper is to describe and analyze the failure patterns observed in reinforced concrete frame buildings with masonry infill walls ranging from 3 to 8 floors in height. Structural as well as non-structural masonry walls suffered important damage that led to redistributions of forces causing in some cases the failure of columns. The importance of the interaction between the structural frames and the infill panels is analyzed by means of non-linear Finite Element Models. The resulting load levels are compared with the member capacities and the changes of the mechanical properties during the seismic event are described and discussed. In the light of the results obtained the observed failure patterns are explained. Some comments are stated concerning the adequacy of the numerical models that are usually used during the design phase for the seismic analysis.

Teamwork, motivational profiles and academic performance in computer science engineering

The present work is aimed at discussing several issues related to the teamwork generic competence, motivational profiles and academic performance. In particular, we study the improvement of teamwork attitude, the predominant types of motivation in different contexts and some correlations among these three components of the learning process. The above-mentioned aspects are of great importance. Currently, the professional profile of engineers has a strong teamwork component and the motivational profile of students determines both their tendencies when they come to work as part of a team, as well as their performance at work. Taking these issues into consideration, we suggest four hypotheses: (H1) students improve their teamwork capacity through specific training and carrying out of a set of activities integrated into an active learning process; (H2) students with higher mastery motivation have a better attitude towards teamwork; (H3) students with different types of motivations reach different levels of academic performance; and (H4) students show different motivation profiles in different circumstances: type of courses, teaching methodologies, different times of the learning process. This study was carried out with Computer Science Engineering students from two Spanish universities. The first results point to an improvement in teamwork competence of students if they have previously received specific training in facets of that competence. Other results indicate that there is a correlation between the motivational profiles of students and their perception of teamwork competence. Finally, results point to a clear relationship between some kind of motivation and academic performance. In particular, four kinds of motivation are analyzed and students are classified into two groups according to them. After analyzing several marks obtained in compulsory courses, we perceive that those students that show higher motivation for avoiding failure obtain, in general, worse academic performance.

Inluence of source and level of glycerin in the diet on growth performance, liver characteristics, and nturient digestibility in broilers from hatching to 21 days of age

The influence of source and level of inclusion of raw glycerin (GLYC) in the diet on growth performance, digestive traits, total tract apparent retention (TTAR), and apparent ileal digestibility of nutrients was studied in broilers from 1 to 21 d of age. There was a control diet based on corn and soybean meal and 8 additional diets that formed a 2 × 4 factorial with 2 sources of GLYC and 4 levels of inclusion (2.5, 5.0, 7.5, and 10%). The GLYC used were obtained from the same original batch of soy oil that was dried under different processing conditions and contained 87.5 or 81.6% glycerol, respectively. Type of processing of the GLYC did not affect any of the variables studied except DM and organic matter retention (P < 0.05) that was higher for the 87.5% glycerol diet. From d 1 to 21, feed conversion ratio (FCR) improved linearly (L, P ≤ 0.01) as the GLYC content of the diet increased, but ADG was not affected. On d 21, the relative weight (% BW) of the liver and the digestive tract increased (L, P < 0.01) as the level of GLYC in the diet increased, but lipid concentration in the liver was not affected. The TTAR of DM and organic matter increased quadratically (Q, P < 0.05) and the AMEn content of the diet increased linearly (L, P < 0.01) with increases in dietary GLYC. Also, the apparent ileal digestibility of DM (L, P < 0.05; Q, P = 0.07) and gross energy (L, P < 0.01) increased as the GLYC content of the diet increased. It is concluded that raw GLYC from the biodiesel industry can be used efficiently, up to 10% of the diet, as a source of energy for broilers from 1 to 21 d of age and that the energy content of well-processed raw GLYC depends primarily on its glycerol content.

Performance profiles of football teams in the UEFA Champions League considering situational efficiency

Performance of football teams varies constantly due to the dynamic nature of this sport, whilst the typical performance and its spread can be represented by profiles combining different performance-related variables based on data from multiple matches. The current study aims to use a profiling technique to evaluate and compare match performance of football teams in the UEFA Champions League incorporating three situational variables (i.e. strength of team and opponent, match outcome and match location). Match statistics of 72 teams, 496 games across four seasons (2008-09 to 2012-13) of this competition were analysed. Sixteen performance-related events were included: shots, shots on target, shots from open play, shots from set piece, shots from counter attack, passes, pass accuracy (%), crosses, through balls, corners, dribbles, possession, aerial success (%), fouls, tackles, and yellow cards. Teams were classified into three levels of strength by a k-cluster analysis. Profiles of overall performance and profiles incorporating three situational variables for teams of all three levels of strength were set up by presenting the mean, standard deviation, median, lower and upper quartiles of the counts of each event to represent their typical performances and spreads. Means were compared by using one-way ANOVA and independent sample t test (for match location, home and away differences), and were plotted into the same radar charts after unifying all the event counts by standardised score. Established profiles can present straightforwardly typical performances of football teams of different levels playing in different situations, which could provide detailed references for coaches and analysts to evaluate performances of upcoming opposition and of their own.

Shake-table tests of a reinforced concrete frame designed following modern codes: seismic performance and damage evaluation

This paper presents shake-table tests conducted on a two-fifths-scale reinforced concrete frame representing a conventional construction design under current building code provisions in the Mediterranean area. The structure was subjected to a sequence of dynamic tests including free vibrations and four seismic simulations in which a historical ground motion record was scaled to levels of increasing intensity until collapse. Each seismic simulation was associated with a different level of seismic hazard, representing very frequent, frequent, rare and very rare earthquakes. The structure remained basically undamaged and within the inter-story drift limits of the "immediate occupancy" performance level for the very frequent and frequent earthquakes. For the rare earthquake, the specimen sustained significant damage with chord rotations of up to 28% of its ultimate capacity and approached the upper bound limit of inter-story drift associated with "life safety". The specimen collapsed at the beginning of the "very rare" seismic simulation. Besides summarizing the experimental program, this paper evaluates the damage quantitatively at the global and local levels in terms of chord rotation and other damage indexes, together with the energy dissipation demands for each level of seismic hazard. Further, the ratios of column-to-beam moment capacity recommended by Eurocode 8 and ACI-318 to guarantee the formation of a strong column-weak beam mechanism are examined.

Seismic performance and damage evaluation of a reinforced concrete frame with hysteretic dampers through shake-table tests

Passive energy dissipation devices are increasingly implemented in frame structures to improve their performance under seismic loading. Most guidelines for designing this type of system retain the requirements applicable to frames without dampers, and this hinders taking full advantage of the benefits of implementing dampers. Further, assessing the extent of damage suffered by the frame and by the dampers for different levels of seismic hazard is of paramount importance in the framework of performance-based design. This paper presents an experimental investigation whose objectives are to provide empirical data on the response of reinforced concrete (RC) frames equipped with hysteretic dampers (dynamic response and damage) and to evaluate the need for the frame to form a strong column-weak beam mechanism and dissipate large amounts of plastic strain energy. To this end, shake-table tests were conducted on a 2/5-scale RC frame with hysteretic dampers. The frame was designed only for gravitational loads. The dampers provided lateral strength and stiffness, respectively, three and 12 times greater than those of the frame. The test structure was subjected to a sequence of seismic simulations that represented different levels of seismic hazard. The RC frame showed a performance level of "immediate occupancy", with maximum rotation demands below 20% of the ultimate capacity. The dampers dissipated most of the energy input by the earthquake. It is shown that combining hysteretic dampers with flexible reinforced concrete frames leads to structures with improved seismic performance and that requirements of conventional RC frames (without dampers) can be relieved.

Power Converter Topologies for a High Performance Transformer Rectifier Unit in Aircraft Applications

This paper presents some power converter architectures and circuit topologies, which can be used to achieve the requirements of the high performance transformer rectifier unit in aircraft applications, mainly as: high power factor with low THD, high efficiency and high power density. The voltage and the power levels demanded for this application are: three-phase line-to-neutral input voltage of 115 or 230V AC rms (360 – 800Hz), output voltage of 28V DC or 270V DC(new grid value) and the output power up to tens of kilowatts.

Productive performance of brown-egg laying pullets from hatching to 5 weeks of age as affected by fiber inclusion, feed form, and energy concentration of the diet

The effects of fiber inclusion, feed form, and energy concentration of the diet on the growth performance of pullets from hatching to 5 wk age were studied in 2 experiments. In Experiment 1, there was a control diet based on cereals and soybean meal, and 6 extra diets that included 2 or 4% of cereal straw, sugar beet pulp (SBP), or sunflower hulls (SFHs) at the expense (wt/wt) of the whole control diet. From hatching to 5 wk age fiber inclusion increased (P < 0.05) ADG and ADFI, and improved (P < 0.05) energy efficiency (EnE; kcal AMEn/g ADG), but body weight (BW) uniformity was not affected. Pullets fed SFH tended to have higher ADG than pullets fed SBP (P = 0.072) with pullets fed straw being intermediate. The feed conversion ratio (FCR) was better (P < 0.05) with 2% than with 4% fiber inclusion. In Experiment 2, 10 diets were arranged as a 2×5 factorial with 2 feed forms (mash vs. crumbles) and 5 levels of AMEn (2,850, 2,900, 2,950, 3,000, and 3,050 kcal/kg). Pullets fed crumbles were heavier and had better FCR than pullets fed mash (P < 0.001). An increase in the energy content of the crumble diets reduced ADFI and improved FCR linearly, but no effects were detected with the mash diets (P < 0.01 and P < 0.05 for the interactions). Feeding crumbles tended to improve BW uniformity at 5 wk age (P = 0.077) but no effects were detected with increases in energy concentration of the diet. In summary, the inclusion of moderate amounts of fiber in the diet improves pullet performance from hatching to 5 wk age. The response of pullets to increases in energy content of the diet depends on feed form with a decrease in feed intake when fed crumbles but no changes when fed mash. Feeding crumbles might be preferred to feeding mash in pullets from hatching to 5 wk age.

Feed form and energy concentration of the diet affect growth performance and digestive tract traits of brown-egg laying pullets from hatching to 17 weeks of age

The influence of feed form and energy concentration of the diet on growth performance and the development of the gastrointestinal tract (GIT) was studied in brown-egg laying pullets. Diets formed a 2 x 5 factorial with 2 feed forms (mash vs. crumbles) and 5 levels of energy differing in 50 kcal AMEn/kg. For the entire study (0 to 17 wk of age) feeding crumbles increased ADFI (52.9 vs. 49.7 g; P < 0.001) and ADG (12.7 vs. 11.6 g; P < 0.001) and improved feed conversion ratio (FCR; 4.18 vs. 4.27; P < 0.001). An increase in the energy content of the diet decreased ADFI linearly (P < 0.001) and improved FCR quadratically (P < 0.01) but energy intake (kcal AMEn/d) was not affected. BW uniformity was higher (P < 0.05) in pullets fed crumbles than in those fed mash but was not affected (P > 0.05) by energy content of the diet. At 5, 10, and 17 wk of age, the relative weight (RW, % BW) of the GIT and the gizzard, and gizzard digesta content were lower (P < 0.05 to P < 0.001) and gizzard pH was higher (P < 0.05 to P < 0.001) in pullets fed crumbles than in pullets fed mash. Energy concentration of the diet did not affect any of the GIT variables studied. In summary, feeding crumbles improved pullet performance and reduced the RW of the GIT and gizzard, and increased gizzard pH at all ages. An increase in the energy content of the diet improved FCR from 0 to 17 wk of age. The use of crumbles and the increase in the AMEn content of the diet might be used adventageously when the objetive is to increase the BW of the pullets. However, crumbles affected the development and weight of the organs of the GIT, which might have negative effects on feed intake and egg production at the beginning of the egg laying cycle.

Run-Time Dynamically-Adaptable FPGA-Based Architecture for High-Performance Autonomous Distributed Systems

Esta tesis doctoral se enmarca dentro del campo de los sistemas embebidos reconfigurables, redes de sensores inalámbricas para aplicaciones de altas prestaciones, y computación distribuida. El documento se centra en el estudio de alternativas de procesamiento para sistemas embebidos autónomos distribuidos de altas prestaciones (por sus siglas en inglés, High-Performance Autonomous Distributed Systems (HPADS)), así como su evolución hacia el procesamiento de alta resolución. El estudio se ha llevado a cabo tanto a nivel de plataforma como a nivel de las arquitecturas de procesamiento dentro de la plataforma con el objetivo de optimizar aspectos tan relevantes como la eficiencia energética, la capacidad de cómputo y la tolerancia a fallos del sistema. Los HPADS son sistemas realimentados, normalmente formados por elementos distribuidos conectados o no en red, con cierta capacidad de adaptación, y con inteligencia suficiente para llevar a cabo labores de prognosis y/o autoevaluación. Esta clase de sistemas suele formar parte de sistemas más complejos llamados sistemas ciber-físicos (por sus siglas en inglés, Cyber-Physical Systems (CPSs)). Los CPSs cubren un espectro enorme de aplicaciones, yendo desde aplicaciones médicas, fabricación, o aplicaciones aeroespaciales, entre otras muchas. Para el diseño de este tipo de sistemas, aspectos tales como la confiabilidad, la definición de modelos de computación, o el uso de metodologías y/o herramientas que faciliten el incremento de la escalabilidad y de la gestión de la complejidad, son fundamentales. La primera parte de esta tesis doctoral se centra en el estudio de aquellas plataformas existentes en el estado del arte que por sus características pueden ser aplicables en el campo de los CPSs, así como en la propuesta de un nuevo diseño de plataforma de altas prestaciones que se ajuste mejor a los nuevos y más exigentes requisitos de las nuevas aplicaciones. Esta primera parte incluye descripción, implementación y validación de la plataforma propuesta, así como conclusiones sobre su usabilidad y sus limitaciones. Los principales objetivos para el diseño de la plataforma propuesta se enumeran a continuación: • Estudiar la viabilidad del uso de una FPGA basada en RAM como principal procesador de la plataforma en cuanto a consumo energético y capacidad de cómputo. • Propuesta de técnicas de gestión del consumo de energía en cada etapa del perfil de trabajo de la plataforma. •Propuestas para la inclusión de reconfiguración dinámica y parcial de la FPGA (por sus siglas en inglés, Dynamic Partial Reconfiguration (DPR)) de forma que sea posible cambiar ciertas partes del sistema en tiempo de ejecución y sin necesidad de interrumpir al resto de las partes. Evaluar su aplicabilidad en el caso de HPADS. Las nuevas aplicaciones y nuevos escenarios a los que se enfrentan los CPSs, imponen nuevos requisitos en cuanto al ancho de banda necesario para el procesamiento de los datos, así como en la adquisición y comunicación de los mismos, además de un claro incremento en la complejidad de los algoritmos empleados. Para poder cumplir con estos nuevos requisitos, las plataformas están migrando desde sistemas tradicionales uni-procesador de 8 bits, a sistemas híbridos hardware-software que incluyen varios procesadores, o varios procesadores y lógica programable. Entre estas nuevas arquitecturas, las FPGAs y los sistemas en chip (por sus siglas en inglés, System on Chip (SoC)) que incluyen procesadores embebidos y lógica programable, proporcionan soluciones con muy buenos resultados en cuanto a consumo energético, precio, capacidad de cómputo y flexibilidad. Estos buenos resultados son aún mejores cuando las aplicaciones tienen altos requisitos de cómputo y cuando las condiciones de trabajo son muy susceptibles de cambiar en tiempo real. La plataforma propuesta en esta tesis doctoral se ha denominado HiReCookie. La arquitectura incluye una FPGA basada en RAM como único procesador, así como un diseño compatible con la plataforma para redes de sensores inalámbricas desarrollada en el Centro de Electrónica Industrial de la Universidad Politécnica de Madrid (CEI-UPM) conocida como Cookies. Esta FPGA, modelo Spartan-6 LX150, era, en el momento de inicio de este trabajo, la mejor opción en cuanto a consumo y cantidad de recursos integrados, cuando además, permite el uso de reconfiguración dinámica y parcial. Es importante resaltar que aunque los valores de consumo son los mínimos para esta familia de componentes, la potencia instantánea consumida sigue siendo muy alta para aquellos sistemas que han de trabajar distribuidos, de forma autónoma, y en la mayoría de los casos alimentados por baterías. Por esta razón, es necesario incluir en el diseño estrategias de ahorro energético para incrementar la usabilidad y el tiempo de vida de la plataforma. La primera estrategia implementada consiste en dividir la plataforma en distintas islas de alimentación de forma que sólo aquellos elementos que sean estrictamente necesarios permanecerán alimentados, cuando el resto puede estar completamente apagado. De esta forma es posible combinar distintos modos de operación y así optimizar enormemente el consumo de energía. El hecho de apagar la FPGA para ahora energía durante los periodos de inactividad, supone la pérdida de la configuración, puesto que la memoria de configuración es una memoria volátil. Para reducir el impacto en el consumo y en el tiempo que supone la reconfiguración total de la plataforma una vez encendida, en este trabajo, se incluye una técnica para la compresión del archivo de configuración de la FPGA, de forma que se consiga una reducción del tiempo de configuración y por ende de la energía consumida. Aunque varios de los requisitos de diseño pueden satisfacerse con el diseño de la plataforma HiReCookie, es necesario seguir optimizando diversos parámetros tales como el consumo energético, la tolerancia a fallos y la capacidad de procesamiento. Esto sólo es posible explotando todas las posibilidades ofrecidas por la arquitectura de procesamiento en la FPGA. Por lo tanto, la segunda parte de esta tesis doctoral está centrada en el diseño de una arquitectura reconfigurable denominada ARTICo3 (Arquitectura Reconfigurable para el Tratamiento Inteligente de Cómputo, Confiabilidad y Consumo de energía) para la mejora de estos parámetros por medio de un uso dinámico de recursos. ARTICo3 es una arquitectura de procesamiento para FPGAs basadas en RAM, con comunicación tipo bus, preparada para dar soporte para la gestión dinámica de los recursos internos de la FPGA en tiempo de ejecución gracias a la inclusión de reconfiguración dinámica y parcial. Gracias a esta capacidad de reconfiguración parcial, es posible adaptar los niveles de capacidad de procesamiento, energía consumida o tolerancia a fallos para responder a las demandas de la aplicación, entorno, o métricas internas del dispositivo mediante la adaptación del número de recursos asignados para cada tarea. Durante esta segunda parte de la tesis se detallan el diseño de la arquitectura, su implementación en la plataforma HiReCookie, así como en otra familia de FPGAs, y su validación por medio de diferentes pruebas y demostraciones. Los principales objetivos que se plantean la arquitectura son los siguientes: • Proponer una metodología basada en un enfoque multi-hilo, como las propuestas por CUDA (por sus siglas en inglés, Compute Unified Device Architecture) u Open CL, en la cual distintos kernels, o unidades de ejecución, se ejecuten en un numero variable de aceleradores hardware sin necesidad de cambios en el código de aplicación. • Proponer un diseño y proporcionar una arquitectura en la que las condiciones de trabajo cambien de forma dinámica dependiendo bien de parámetros externos o bien de parámetros que indiquen el estado de la plataforma. Estos cambios en el punto de trabajo de la arquitectura serán posibles gracias a la reconfiguración dinámica y parcial de aceleradores hardware en tiempo real. • Explotar las posibilidades de procesamiento concurrente, incluso en una arquitectura basada en bus, por medio de la optimización de las transacciones en ráfaga de datos hacia los aceleradores. •Aprovechar las ventajas ofrecidas por la aceleración lograda por módulos puramente hardware para conseguir una mejor eficiencia energética. • Ser capaces de cambiar los niveles de redundancia de hardware de forma dinámica según las necesidades del sistema en tiempo real y sin cambios para el código de aplicación. • Proponer una capa de abstracción entre el código de aplicación y el uso dinámico de los recursos de la FPGA. El diseño en FPGAs permite la utilización de módulos hardware específicamente creados para una aplicación concreta. De esta forma es posible obtener rendimientos mucho mayores que en el caso de las arquitecturas de propósito general. Además, algunas FPGAs permiten la reconfiguración dinámica y parcial de ciertas partes de su lógica en tiempo de ejecución, lo cual dota al diseño de una gran flexibilidad. Los fabricantes de FPGAs ofrecen arquitecturas predefinidas con la posibilidad de añadir bloques prediseñados y poder formar sistemas en chip de una forma más o menos directa. Sin embargo, la forma en la que estos módulos hardware están organizados dentro de la arquitectura interna ya sea estática o dinámicamente, o la forma en la que la información se intercambia entre ellos, influye enormemente en la capacidad de cómputo y eficiencia energética del sistema. De la misma forma, la capacidad de cargar módulos hardware bajo demanda, permite añadir bloques redundantes que permitan aumentar el nivel de tolerancia a fallos de los sistemas. Sin embargo, la complejidad ligada al diseño de bloques hardware dedicados no debe ser subestimada. Es necesario tener en cuenta que el diseño de un bloque hardware no es sólo su propio diseño, sino también el diseño de sus interfaces, y en algunos casos de los drivers software para su manejo. Además, al añadir más bloques, el espacio de diseño se hace más complejo, y su programación más difícil. Aunque la mayoría de los fabricantes ofrecen interfaces predefinidas, IPs (por sus siglas en inglés, Intelectual Property) comerciales y plantillas para ayudar al diseño de los sistemas, para ser capaces de explotar las posibilidades reales del sistema, es necesario construir arquitecturas sobre las ya establecidas para facilitar el uso del paralelismo, la redundancia, y proporcionar un entorno que soporte la gestión dinámica de los recursos. Para proporcionar este tipo de soporte, ARTICo3 trabaja con un espacio de soluciones formado por tres ejes fundamentales: computación, consumo energético y confiabilidad. De esta forma, cada punto de trabajo se obtiene como una solución de compromiso entre estos tres parámetros. Mediante el uso de la reconfiguración dinámica y parcial y una mejora en la transmisión de los datos entre la memoria principal y los aceleradores, es posible dedicar un número variable de recursos en el tiempo para cada tarea, lo que hace que los recursos internos de la FPGA sean virtualmente ilimitados. Este variación en el tiempo del número de recursos por tarea se puede usar bien para incrementar el nivel de paralelismo, y por ende de aceleración, o bien para aumentar la redundancia, y por lo tanto el nivel de tolerancia a fallos. Al mismo tiempo, usar un numero óptimo de recursos para una tarea mejora el consumo energético ya que bien es posible disminuir la potencia instantánea consumida, o bien el tiempo de procesamiento. Con el objetivo de mantener los niveles de complejidad dentro de unos límites lógicos, es importante que los cambios realizados en el hardware sean totalmente transparentes para el código de aplicación. A este respecto, se incluyen distintos niveles de transparencia: • Transparencia a la escalabilidad: los recursos usados por una misma tarea pueden ser modificados sin que el código de aplicación sufra ningún cambio. • Transparencia al rendimiento: el sistema aumentara su rendimiento cuando la carga de trabajo aumente, sin cambios en el código de aplicación. • Transparencia a la replicación: es posible usar múltiples instancias de un mismo módulo bien para añadir redundancia o bien para incrementar la capacidad de procesamiento. Todo ello sin que el código de aplicación cambie. • Transparencia a la posición: la posición física de los módulos hardware es arbitraria para su direccionamiento desde el código de aplicación. • Transparencia a los fallos: si existe un fallo en un módulo hardware, gracias a la redundancia, el código de aplicación tomará directamente el resultado correcto. • Transparencia a la concurrencia: el hecho de que una tarea sea realizada por más o menos bloques es transparente para el código que la invoca. Por lo tanto, esta tesis doctoral contribuye en dos líneas diferentes. En primer lugar, con el diseño de la plataforma HiReCookie y en segundo lugar con el diseño de la arquitectura ARTICo3. Las principales contribuciones de esta tesis se resumen a continuación. • Arquitectura de la HiReCookie incluyendo: o Compatibilidad con la plataforma Cookies para incrementar las capacidades de esta. o División de la arquitectura en distintas islas de alimentación. o Implementación de los diversos modos de bajo consumo y políticas de despertado del nodo. o Creación de un archivo de configuración de la FPGA comprimido para reducir el tiempo y el consumo de la configuración inicial. • Diseño de la arquitectura reconfigurable para FPGAs basadas en RAM ARTICo3: o Modelo de computación y modos de ejecución inspirados en el modelo de CUDA pero basados en hardware reconfigurable con un número variable de bloques de hilos por cada unidad de ejecución. o Estructura para optimizar las transacciones de datos en ráfaga proporcionando datos en cascada o en paralelo a los distinto módulos incluyendo un proceso de votado por mayoría y operaciones de reducción. o Capa de abstracción entre el procesador principal que incluye el código de aplicación y los recursos asignados para las diferentes tareas. o Arquitectura de los módulos hardware reconfigurables para mantener la escalabilidad añadiendo una la interfaz para las nuevas funcionalidades con un simple acceso a una memoria RAM interna. o Caracterización online de las tareas para proporcionar información a un módulo de gestión de recursos para mejorar la operación en términos de energía y procesamiento cuando además se opera entre distintos nieles de tolerancia a fallos. El documento está dividido en dos partes principales formando un total de cinco capítulos. En primer lugar, después de motivar la necesidad de nuevas plataformas para cubrir las nuevas aplicaciones, se detalla el diseño de la plataforma HiReCookie, sus partes, las posibilidades para bajar el consumo energético y se muestran casos de uso de la plataforma así como pruebas de validación del diseño. La segunda parte del documento describe la arquitectura reconfigurable, su implementación en varias FPGAs, y pruebas de validación en términos de capacidad de procesamiento y consumo energético, incluyendo cómo estos aspectos se ven afectados por el nivel de tolerancia a fallos elegido. Los capítulos a lo largo del documento son los siguientes: El capítulo 1 analiza los principales objetivos, motivación y aspectos teóricos necesarios para seguir el resto del documento. El capítulo 2 está centrado en el diseño de la plataforma HiReCookie y sus posibilidades para disminuir el consumo de energía. El capítulo 3 describe la arquitectura reconfigurable ARTICo3. El capítulo 4 se centra en las pruebas de validación de la arquitectura usando la plataforma HiReCookie para la mayoría de los tests. Un ejemplo de aplicación es mostrado para analizar el funcionamiento de la arquitectura. El capítulo 5 concluye esta tesis doctoral comentando las conclusiones obtenidas, las contribuciones originales del trabajo y resultados y líneas futuras. ABSTRACT This PhD Thesis is framed within the field of dynamically reconfigurable embedded systems, advanced sensor networks and distributed computing. The document is centred on the study of processing solutions for high-performance autonomous distributed systems (HPADS) as well as their evolution towards High performance Computing (HPC) systems. The approach of the study is focused on both platform and processor levels to optimise critical aspects such as computing performance, energy efficiency and fault tolerance. HPADS are considered feedback systems, normally networked and/or distributed, with real-time adaptive and predictive functionality. These systems, as part of more complex systems known as Cyber-Physical Systems (CPSs), can be applied in a wide range of fields such as military, health care, manufacturing, aerospace, etc. For the design of HPADS, high levels of dependability, the definition of suitable models of computation, and the use of methodologies and tools to support scalability and complexity management, are required. The first part of the document studies the different possibilities at platform design level in the state of the art, together with description, development and validation tests of the platform proposed in this work to cope with the previously mentioned requirements. The main objectives targeted by this platform design are the following: • Study the feasibility of using SRAM-based FPGAs as the main processor of the platform in terms of energy consumption and performance for high demanding applications. • Analyse and propose energy management techniques to reduce energy consumption in every stage of the working profile of the platform. • Provide a solution with dynamic partial and wireless remote HW reconfiguration (DPR) to be able to change certain parts of the FPGA design at run time and on demand without interrupting the rest of the system. • Demonstrate the applicability of the platform in different test-bench applications. In order to select the best approach for the platform design in terms of processing alternatives, a study of the evolution of the state-of-the-art platforms is required to analyse how different architectures cope with new more demanding applications and scenarios: security, mixed-critical systems for aerospace, multimedia applications, or military environments, among others. In all these scenarios, important changes in the required processing bandwidth or the complexity of the algorithms used are provoking the migration of the platforms from single microprocessor architectures to multiprocessing and heterogeneous solutions with more instant power consumption but higher energy efficiency. Within these solutions, FPGAs and Systems on Chip including FPGA fabric and dedicated hard processors, offer a good trade of among flexibility, processing performance, energy consumption and price, when they are used in demanding applications where working conditions are very likely to vary over time and high complex algorithms are required. The platform architecture proposed in this PhD Thesis is called HiReCookie. It includes an SRAM-based FPGA as the main and only processing unit. The FPGA selected, the Xilinx Spartan-6 LX150, was at the beginning of this work the best choice in terms of amount of resources and power. Although, the power levels are the lowest of these kind of devices, they can be still very high for distributed systems that normally work powered by batteries. For that reason, it is necessary to include different energy saving possibilities to increase the usability of the platform. In order to reduce energy consumption, the platform architecture is divided into different power islands so that only those parts of the systems that are strictly needed are powered on, while the rest of the islands can be completely switched off. This allows a combination of different low power modes to decrease energy. In addition, one of the most important handicaps of SRAM-based FPGAs is that they are not alive at power up. Therefore, recovering the system from a switch-off state requires to reload the FPGA configuration from a non-volatile memory device. For that reason, this PhD Thesis also proposes a methodology to compress the FPGA configuration file in order to reduce time and energy during the initial configuration process. Although some of the requirements for the design of HPADS are already covered by the design of the HiReCookie platform, it is necessary to continue improving energy efficiency, computing performance and fault tolerance. This is only possible by exploiting all the opportunities provided by the processing architectures configured inside the FPGA. Therefore, the second part of the thesis details the design of the so called ARTICo3 FPGA architecture to enhance the already intrinsic capabilities of the FPGA. ARTICo3 is a DPR-capable bus-based virtual architecture for multiple HW acceleration in SRAM-based FPGAs. The architecture provides support for dynamic resource management in real time. In this way, by using DPR, it will be possible to change the levels of computing performance, energy consumption and fault tolerance on demand by increasing or decreasing the amount of resources used by the different tasks. Apart from the detailed design of the architecture and its implementation in different FPGA devices, different validation tests and comparisons are also shown. The main objectives targeted by this FPGA architecture are listed as follows: • Provide a method based on a multithread approach such as those offered by CUDA (Compute Unified Device Architecture) or OpenCL kernel executions, where kernels are executed in a variable number of HW accelerators without requiring application code changes. • Provide an architecture to dynamically adapt working points according to either self-measured or external parameters in terms of energy consumption, fault tolerance and computing performance. Taking advantage of DPR capabilities, the architecture must provide support for a dynamic use of resources in real time. • Exploit concurrent processing capabilities in a standard bus-based system by optimizing data transactions to and from HW accelerators. • Measure the advantage of HW acceleration as a technique to boost performance to improve processing times and save energy by reducing active times for distributed embedded systems. • Dynamically change the levels of HW redundancy to adapt fault tolerance in real time. • Provide HW abstraction from SW application design. FPGAs give the possibility of designing specific HW blocks for every required task to optimise performance while some of them include the possibility of including DPR. Apart from the possibilities provided by manufacturers, the way these HW modules are organised, addressed and multiplexed in area and time can improve computing performance and energy consumption. At the same time, fault tolerance and security techniques can also be dynamically included using DPR. However, the inherent complexity of designing new HW modules for every application is not negligible. It does not only consist of the HW description, but also the design of drivers and interfaces with the rest of the system, while the design space is widened and more complex to define and program. Even though the tools provided by the majority of manufacturers already include predefined bus interfaces, commercial IPs, and templates to ease application prototyping, it is necessary to improve these capabilities. By adding new architectures on top of them, it is possible to take advantage of parallelization and HW redundancy while providing a framework to ease the use of dynamic resource management. ARTICo3 works within a solution space where working points change at run time in a 3D space defined by three different axes: Computation, Consumption, and Fault Tolerance. Therefore, every working point is found as a trade-off solution among these three axes. By means of DPR, different accelerators can be multiplexed so that the amount of available resources for any application is virtually unlimited. Taking advantage of DPR capabilities and a novel way of transmitting data to the reconfigurable HW accelerators, it is possible to dedicate a dynamically-changing number of resources for a given task in order to either boost computing speed or adding HW redundancy and a voting process to increase fault-tolerance levels. At the same time, using an optimised amount of resources for a given task reduces energy consumption by reducing instant power or computing time. In order to keep level complexity under certain limits, it is important that HW changes are transparent for the application code. Therefore, different levels of transparency are targeted by the system: • Scalability transparency: a task must be able to expand its resources without changing the system structure or application algorithms. • Performance transparency: the system must reconfigure itself as load changes. • Replication transparency: multiple instances of the same task are loaded to increase reliability and performance. • Location transparency: resources are accessed with no knowledge of their location by the application code. • Failure transparency: task must be completed despite a failure in some components. • Concurrency transparency: different tasks will work in a concurrent way transparent to the application code. Therefore, as it can be seen, the Thesis is contributing in two different ways. First with the design of the HiReCookie platform and, second with the design of the ARTICo3 architecture. The main contributions of this PhD Thesis are then listed below: • Architecture of the HiReCookie platform including: o Compatibility of the processing layer for high performance applications with the Cookies Wireless Sensor Network platform for fast prototyping and implementation. o A division of the architecture in power islands. o All the different low-power modes. o The creation of the partial-initial bitstream together with the wake-up policies of the node. • The design of the reconfigurable architecture for SRAM FPGAs: ARTICo3: o A model of computation and execution modes inspired in CUDA but based on reconfigurable HW with a dynamic number of thread blocks per kernel. o A structure to optimise burst data transactions providing coalesced or parallel data to HW accelerators, parallel voting process and reduction operation. o The abstraction provided to the host processor with respect to the operation of the kernels in terms of the number of replicas, modes of operation, location in the reconfigurable area and addressing. o The architecture of the modules representing the thread blocks to make the system scalable by adding functional units only adding an access to a BRAM port. o The online characterization of the kernels to provide information to a scheduler or resource manager in terms of energy consumption and processing time when changing among different fault-tolerance levels, as well as if a kernel is expected to work in the memory-bounded or computing-bounded areas. The document of the Thesis is divided into two main parts with a total of five chapters. First, after motivating the need for new platforms to cover new more demanding applications, the design of the HiReCookie platform, its parts and several partial tests are detailed. The design of the platform alone does not cover all the needs of these applications. Therefore, the second part describes the architecture inside the FPGA, called ARTICo3, proposed in this PhD Thesis. The architecture and its implementation are tested in terms of energy consumption and computing performance showing different possibilities to improve fault tolerance and how this impact in energy and time of processing. Chapter 1 shows the main goals of this PhD Thesis and the technology background required to follow the rest of the document. Chapter 2 shows all the details about the design of the FPGA-based platform HiReCookie. Chapter 3 describes the ARTICo3 architecture. Chapter 4 is focused on the validation tests of the ARTICo3 architecture. An application for proof of concept is explained where typical kernels related to image processing and encryption algorithms are used. Further experimental analyses are performed using these kernels. Chapter 5 concludes the document analysing conclusions, comments about the contributions of the work, and some possible future lines for the work.

Productive performance of brown-egg laying pullets from hatching to 5 weeks of age as affected by fiber inclusion, feed form, and energy concentration of the diet1

The effects of fiber inclusion, feed form, and energy concentration of the diet on the growth performance of pullets from hatching to 5 wk age were studied in 2 experiments. In Experiment 1, there was a control diet based on cereals and soybean meal, and 6 extra diets that included 2 or 4% of cereal straw, sugar beet pulp (SBP), or sunflower hulls (SFHs) at the expense (wt/wt) of the whole control diet. From hatching to 5 wk age fiber inclusion increased (P < 0.05) ADG and ADFI, and improved (P < 0.05) energy efficiency (EnE; kcal AMEn/g ADG), but body weight (BW) uniformity was not affected. Pullets fed SFH tended to have higher ADG than pullets fed SBP (P = 0.072) with pullets fed straw being intermediate. The feed conversion ratio (FCR) was better (P < 0.05) with 2% than with 4% fiber inclusion. In Experiment 2, 10 diets were arranged as a 2×5 factorial with 2 feed forms (mash vs. crumbles) and 5 levels of AMEn (2,850, 2,900, 2,950, 3,000, and 3,050 kcal/kg). Pullets fed crumbles were heavier and had better FCR than pullets fed mash (P < 0.001). An increase in the energy content of the crumble diets reduced ADFI and improved FCR linearly, but no effects were detected with the mash diets (P < 0.01 and P < 0.05 for the interactions). Feeding crumbles tended to improve BW uniformity at 5 wk age (P = 0.077) but no effects were detected with increases in energy concentration of the diet. In summary, the inclusion of moderate amounts of fiber in the diet improves pullet performance from hatching to 5 wk age. The response of pullets to increases in energy content of the diet depends on feed form with a decrease in feed intake when fed crumbles but no changes when fed mash. Feeding crumbles might be preferred to feeding mash in pullets from hatching to 5 wk age.

Quantitative high performance liquid chromatography/tandem mass spectrometric analysis of the four classes of F2-isoprostanes in human urine

Isoprostanes (iPs) are free radical catalyzed prostaglandin isomers. Analysis of individual isomers of PGF2α—F2-iPs—in urine has reflected lipid peroxidation in humans. However, up to 64 F2-iPs may be formed, and it is unknown whether coordinate generation, disposition, and excretion of F2-iPs occurs in humans. To address this issue, we developed methods to measure individual members of the four structural classes of F2-iPs, using liquid chromatography/tandem mass spectrometry (LC/MS/MS), in which sample preparation is minimized. Authentic standards of F2-iPs of classes III, IV, V, and VI were used to identify class-specific ions for multiple reaction monitoring. Using iPF2α-VI as a model compound, we demonstrated the reproducibility of the assay in human urine. Urinary levels of all F2-iPs measured were elevated in patients with familial hypercholesterolemia. However, only three of eight F2-iPs were elevated in patients with congestive heart failure, compared with controls. Paired analyses by GC/MS and LC/MS/MS of iPF2α-VI in hypercholesterolemia and of 8,12-iso-iPF2α-VI in congestive heart failure were highly correlated. This approach will permit high throughput analysis of multiple iPs in human disease.

Measurement of 8-hydroxy-2′-deoxyguanosine in DNA by high-performance liquid chromatography-mass spectrometry: comparison with measurement by gas chromatography-mass spectrometry

Measurement of 8-hydroxy-2′-deoxyguanosine (8-OH-dGuo) in DNA by high-performance liquid chromatography/mass spectrometry (LC/MS) was studied. A methodology was developed for separation by LC of 8-OH-dGuo from intact and modified nucleosides in DNA hydrolyzed by a combination of four enzymes: DNase I, phosphodiesterases I and II and alkaline phosphatase. The atmospheric pressure ionization-electrospray process was used for mass spectral measurements. A stable isotope-labeled analog of 8-OH-dGuo was used as an internal standard for quantification by isotope-dilution MS (IDMS). Results showed that LC/IDMS with selected ion-monitoring (SIM) is well suited for identification and quantification of 8-OH-dGuo in DNA at background levels and in damaged DNA. The sensitivity level of LC/IDMS-SIM was found to be comparable to that reported previously using LC-tandem MS (LC/MS/MS). It was found that approximately five lesions per 106 DNA bases can be detected using amounts of DNA as low as 2 µg. The results also suggest that this lesion may be quantified in DNA at levels of one lesion per 106 DNA bases, or even lower, when more DNA is used. Up to 50 µg of DNA per injection were used without adversely affecting the measurements. Gas chromatography/isotope-dilution MS with selected-ion monitoring (GC/IDMS-SIM) was also used to measure this compound in DNA following its removal from DNA by acidic hydrolysis or by hydrolysis with Escherichia coli Fpg protein. The background levels obtained by LC/IDMS-SIM and GC/IDMS-SIM were almost identical. Calf thymus DNA and DNA isolated from cultured HeLa cells were used for this purpose. This indicates that these two techniques can provide similar results in terms of the measurement of 8-OH-dGuo in DNA. In addition, DNA in buffered aqueous solution was damaged by ionizing radiation at different radiation doses and analyzed by LC/IDMS-SIM and GC/IDMS-SIM. Again, similar results were obtained by the two techniques. The sensitivity of GC/MS-SIM for 7,8-dihydro-8-oxoguanine was also examined and found to be much greater than that of LC/MS-SIM and the reported sensitivity of LC/MS/MS for 8-OH-dGuo. Taken together, the results unequivocally show that LC/IDMS-SIM is well suited for sensitive and accurate measurement of 8-OH-dGuo in DNA and that both LC/IDMS-SIM and GC/IDMS-SIM can provide similar results.

An evaluation of the performance of cDNA microarrays for detecting changes in global mRNA expression

The cDNA microarray is one technological approach that has the potential to accurately measure changes in global mRNA expression levels. We report an assessment of an optimized cDNA microarray platform to generate accurate, precise and reliable data consistent with the objective of using microarrays as an acquisition platform to populate gene expression databases. The study design consisted of two independent evaluations with 70 arrays from two different manufactured lots and used three human tissue sources as samples: placenta, brain and heart. Overall signal response was linear over three orders of magnitude and the sensitivity for any element was estimated to be 2 pg mRNA. The calculated coefficient of variation for differential expression for all non-differentiated elements was 12–14% across the entire signal range and did not vary with array batch or tissue source. The minimum detectable fold change for differential expression was 1.4. Accuracy, in terms of bias (observed minus expected differential expression ratio), was less than 1 part in 10 000 for all non-differentiated elements. The results presented in this report demonstrate the reproducible performance of the cDNA microarray technology platform and the methods provide a useful framework for evaluating other technologies that monitor changes in global mRNA expression.

Hydroperoxide lyase depletion in transgenic potato plants leads to an increase in aphid performance

Hydroperoxide lyases (HPLs) catalyze the cleavage of fatty acid hydroperoxides to aldehydes and oxoacids. These volatile aldehydes play a major role in forming the aroma of many plant fruits and flowers. In addition, they have antimicrobial activity in vitro and thus are thought to be involved in the plant defense response against pest and pathogen attack. An HPL activity present in potato leaves has been characterized and shown to cleave specifically 13-hydroperoxides of both linoleic and linolenic acids to yield hexanal and 3-hexenal, respectively, and 12-oxo-dodecenoic acid. A cDNA encoding this HPL has been isolated and used to monitor gene expression in healthy and mechanically damaged potato plants. HPL gene expression is subject to developmental control, being high in young leaves and attenuated in older ones, and it is induced weakly by wounding. HPL enzymatic activity, nevertheless, remains constant in leaves of different ages and also after wounding, suggesting that posttranscriptional mechanisms may regulate its activity levels. Antisense-mediated HPL depletion in transgenic potato plants has identified this enzyme as a major route of 13-fatty acid hydroperoxide degradation in the leaves. Although these transgenic plants have highly reduced levels of both hexanal and 3-hexenal, they show no phenotypic differences compared with wild-type ones, particularly in regard to the expression of wound-induced genes. However, aphids feeding on the HPL-depleted plants display approximately a two-fold increase in fecundity above those feeding on nontransformed plants, consistent with the hypothesis that HPL-derived products have a negative impact on aphid performance. Thus, HPL-catalyzed production of C6 aldehydes may be a key step of a built-in resistance mechanism of plants against some sucking insect pests.