Growth and magnetic properties of ferromagnetic Co nanorods filled inside carbon nanotubes towards nanoscale spintronics

We synthesize Co nanorod filled inside multi-walled CNTs (MWCNTs) by microwave plasma enhanced chemical vapor deposition (MPECVD) and utilize off-axis electron holography to observe the remanent states of the filled metal nanorod inside MWCNTs at room. The MWCNTs grew up to 100-110 nm in diameter and 1.5-1.7 μm in length. The typical bright-field transmission electron microscope (TEM) images revealed both Co/Pd multisegment nanorod and Co nanorod filled inside MWCNTs on the same substrate. We have also performed energy-dispersive X-ray spectrometer (EDS) measurements to characterize the composition of metal filled inside MWCNTs. Based on high-resolution TEM measurements, we observed the face-centered-cubic (fcc) Co filled inside MWCNT. The component of magnetic induction was then measured to be 1.2±0.1 T, which is lower than the expected saturation magnetization of fcc Co of 1.7 T. The partial oxidation of the ferromagnetic metal during the process and the magnetization direction may play an important role in the determination of the quality of the remanent states. © 2008 IEEE.

Fabrication of diamond based schottky barrier diodes with oxide ramp termination

The paper's goal is the first demonstration of the fabrication of high power Schottky diodes on synthetic diamond using oxide ramp termination. In order to allow full activated impurities at room temperature and a high hole mobility a low boron doping of the drift layer is employed. Several aspects of the manufacturing technology are presented. A termination with a small ramp angle can be obtained using only RIE technique due to diamond wafer nonuniformity (roughness). Experimental forward and reverse characteristics measured on diamond diodes are also included. © 2007 IEEE.

Direct growth of horizontally aligned carbon nanotubes between electrodes and its application to field-effect transistors

This paper presents direct growth of horizontally aligned carbon nanotubes (CNTs) between two predefined various inter-spacing up to tens of microns of electrodes (pads) and its use as CNT field-effect transistors (CNT-FETs). The catalytic metals were prepared, consisting of iron (Fe), aluminum (Al) and platinum (Pt) triple layers, on the thermal silicon oxide substrate (Pt/Al/Fe/SiO2). Scanning electron microscopy measurements of CNT-FETs from the as-grown samples showed that over 80% of the nanotubes are grown across the catalytic electrodes. Moreover, the number of CNTs across the catalytic electrodes is roughly controllable by adjusting the growth condition. The Al, as the upper layer on Fe electrode, not only plays a role as a barrier to prevent vertical growth but also serves as a porous medium that helps in forming smaller nano-sized Fe particles which would be necessary for lateral growth of CNTs. Back-gate field effect transistors were demonstrated with the laterally aligned CNTs. The on/off ratios in all the measured devices are lower than 100 due to the drain leakage current. ©2010 IEEE.

Switching speed enhancement of the LDMOSFETs using partial-SOI technology

To overcome reduced breakdown voltage and self-heating effects inherent in silicon-on-insulator (SOI) power integrated circuits while still maintaining good isolation between low power CMOS circuits and the high power cells, partial SOI (PSOI) technology has been proposed. PSOI devices make use of both buried oxide and substrate depletion to support the breakdown voltage. 2D analyses and modeling of parasitic capacitances in PSOI structures show that PSOI-lightly doped MOSFETs can increase the switching speed by as much as four times compared to conventional SOI structures, making them very attractive for high switching applications.

Theoretical and numerical investigation of SiC JFET and MOSFET at 6.5 kV

This paper presents a preliminary theoretical and numerical investigation of 4H-SiC JFET and MOSFET at 6.5 kV. To improve the on-state/breakdown performance of the JFET, buried layers in conjunction with a highly doped buffer layer have been used. Trench technology has been employed for the MOSFET. The devices were simulated and optimized using MEDICI[I] simulator. From the comparison between the two devices, it turns out that the JFET offers a better on-state/breakdown trade-off, while the trench MOSFET has the advantage of MOS-control.

Amorphous carbon for use in thin film transistors

Tetrahedrally bonded amorphous carbon (ta-C) is a new type of semiconducting thin film material. It can be produced at room temperature using the Filtered Cathodic Vacuum Arc technique. The as-grown undoped ta-C is p-type in nature but it can be n-doped by the addition of nitrogen during deposition. This paper will describe thin film transistor design and fabrication using ta-C as the active channel layer.