Functional timing analysis of VLSI circuits containing complex gates

The recent advances in CMOS technology have allowed for the fabrication of transistors with submicronic dimensions, making possible the integration of tens of millions devices in a single chip that can be used to build very complex electronic systems. Such increase in complexity of designs has originated a need for more efficient verification tools that could incorporate more appropriate physical and computational models. Timing verification targets at determining whether the timing constraints imposed to the design may be satisfied or not. It can be performed by using circuit simulation or by timing analysis. Although simulation tends to furnish the most accurate estimates, it presents the drawback of being stimuli dependent. Hence, in order to ensure that the critical situation is taken into account, one must exercise all possible input patterns. Obviously, this is not possible to accomplish due to the high complexity of current designs. To circumvent this problem, designers must rely on timing analysis. Timing analysis is an input-independent verification approach that models each combinational block of a circuit as a direct acyclic graph, which is used to estimate the critical delay. First timing analysis tools used only the circuit topology information to estimate circuit delay, thus being referred to as topological timing analyzers. However, such method may result in too pessimistic delay estimates, since the longest paths in the graph may not be able to propagate a transition, that is, may be false. Functional timing analysis, in turn, considers not only circuit topology, but also the temporal and functional relations between circuit elements. Functional timing analysis tools may differ by three aspects: the set of sensitization conditions necessary to declare a path as sensitizable (i.e., the so-called path sensitization criterion), the number of paths simultaneously handled and the method used to determine whether sensitization conditions are satisfiable or not. Currently, the two most efficient approaches test the sensitizability of entire sets of paths at a time: one is based on automatic test pattern generation (ATPG) techniques and the other translates the timing analysis problem into a satisfiability (SAT) problem. Although timing analysis has been exhaustively studied in the last fifteen years, some specific topics have not received the required attention yet. One such topic is the applicability of functional timing analysis to circuits containing complex gates. This is the basic concern of this thesis. In addition, and as a necessary step to settle the scenario, a detailed and systematic study on functional timing analysis is also presented.

Mixed-signal analog-digital circuits design on the pre-diffused digital array using trapezoidal association of transistors

The mixed-signal and analog design on a pre-diffused array is a challenging task, given that the digital array is a linear matrix arrangement of minimum-length transistors. To surmount this drawback a specific discipline for designing analog circuits over such array is required. An important novel technique proposed is the use of TAT (Trapezoidal Associations of Transistors) composite transistors on the semi-custom Sea-Of-Transistors (SOT) array. The analysis and advantages of TAT arrangement are extensively analyzed and demonstrated, with simulation and measurement comparisons to equivalent single transistors. Basic analog cells were also designed as well in full-custom and TAT versions in 1.0mm and 0.5mm digital CMOS technologies. Most of the circuits were prototyped in full-custom and TAT-based on pre-diffused SOT arrays. An innovative demonstration of the TAT technique is shown with the design and implementation of a mixed-signal analog system, i. e., a fully differential 2nd order Sigma-Delta Analog-to-Digital (A/D) modulator, fabricated in both full-custom and SOT array methodologies in 0.5mm CMOS technology from MOSIS foundry. Three test-chips were designed and fabricated in 0.5mm. Two of them are IC chips containing the full-custom and SOT array versions of a 2nd-Order Sigma-Delta A/D modulator. The third IC contains a transistors-structure (TAT and single) and analog cells placed side-by-side, block components (Comparator and Folded-cascode OTA) of the Sigma-Delta modulator.

Automatic layout generation of static CMOS circuits targeting delay and power

The evolution of integrated circuits technologies demands the development of new CAD tools. The traditional development of digital circuits at physical level is based in library of cells. These libraries of cells offer certain predictability of the electrical behavior of the design due to the previous characterization of the cells. Besides, different versions of each cell are required in such a way that delay and power consumption characteristics are taken into account, increasing the number of cells in a library. The automatic full custom layout generation is an alternative each time more important to cell based generation approaches. This strategy implements transistors and connections according patterns defined by algorithms. So, it is possible to implement any logic function avoiding the limitations of the library of cells. Tools of analysis and estimate must offer the predictability in automatic full custom layouts. These tools must be able to work with layout estimates and to generate information related to delay, power consumption and area occupation. This work includes the research of new methods of physical synthesis and the implementation of an automatic layout generation in which the cells are generated at the moment of the layout synthesis. The research investigates different strategies of elements disposition (transistors, contacts and connections) in a layout and their effects in the area occupation and circuit delay. The presented layout strategy applies delay optimization by the integration with a gate sizing technique. This is performed in such a way the folding method allows individual discrete sizing to transistors. The main characteristics of the proposed strategy are: power supply lines between rows, over the layout routing (channel routing is not used), circuit routing performed before layout generation and layout generation targeting delay reduction by the application of the sizing technique. The possibility to implement any logic function, without restrictions imposed by a library of cells, allows the circuit synthesis with optimization in the number of the transistors. This reduction in the number of transistors decreases the delay and power consumption, mainly the static power consumption in submicrometer circuits. Comparisons between the proposed strategy and other well-known methods are presented in such a way the proposed method is validated.

Low cost BIST techniques for linear and non-linear analog circuits

With the ever increasing demands for high complexity consumer electronic products, market pressures demand faster product development and lower cost. SoCbased design can provide the required design flexibility and speed by allowing the use of IP cores. However, testing costs in the SoC environment can reach a substantial percent of the total production cost. Analog testing costs may dominate the total test cost, as testing of analog circuits usually require functional verification of the circuit and special testing procedures. For RF analog circuits commonly used in wireless applications, testing is further complicated because of the high frequencies involved. In summary, reducing analog test cost is of major importance in the electronic industry today. BIST techniques for analog circuits, though potentially able to solve the analog test cost problem, have some limitations. Some techniques are circuit dependent, requiring reconfiguration of the circuit being tested, and are generally not usable in RF circuits. In the SoC environment, as processing and memory resources are available, they could be used in the test. However, the overhead for adding additional AD and DA converters may be too costly for most systems, and analog routing of signals may not be feasible and may introduce signal distortion. In this work a simple and low cost digitizer is used instead of an ADC in order to enable analog testing strategies to be implemented in a SoC environment. Thanks to the low analog area overhead of the converter, multiple analog test points can be observed and specific analog test strategies can be enabled. As the digitizer is always connected to the analog test point, it is not necessary to include muxes and switches that would degrade the signal path. For RF analog circuits, this is specially useful, as the circuit impedance is fixed and the influence of the digitizer can be accounted for in the design phase. Thanks to the simplicity of the converter, it is able to reach higher frequencies, and enables the implementation of low cost RF test strategies. The digitizer has been applied successfully in the testing of both low frequency and RF analog circuits. Also, as testing is based on frequency-domain characteristics, nonlinear characteristics like intermodulation products can also be evaluated. Specifically, practical results were obtained for prototyped base band filters and a 100MHz mixer. The application of the converter for noise figure evaluation was also addressed, and experimental results for low frequency amplifiers using conventional opamps were obtained. The proposed method is able to enhance the testability of current mixed-signal designs, being suitable for the SoC environment used in many industrial products nowadays.

Numerical integration of coupled stochastic oscillators driven by Random Forces

Trabalho apresentado no International Conference on Scientific Computation And Differential Equations 2015

Development of a dynamic headspace solid-phase microextraction procedure coupled to GC–qMSD for evaluation the chemical profile in alcoholic beverages

In the present study, a simple and sensitive methodology based on dynamic headspace solid-phase microextraction (HS-SPME) followed by thermal desorption gas chromatography with quadrupole mass detection (GC–qMSD), was developed and optimized for the determination of volatile (VOCs) and semi-volatile (SVOCs) compounds from different alcoholic beverages: wine, beer and whisky. Key experimental factors influencing the equilibrium of the VOCs and SVOCs between the sample and the SPME fibre, as the type of fibre coating, extraction time and temperature, sample stirring and ionic strength, were optimized. The performance of five commercially available SPME fibres was evaluated and compared, namely polydimethylsiloxane (PDMS, 100 μm); polyacrylate (PA, 85 μm); polydimethylsiloxane/divinylbenzene (PDMS/DVB, 65 μm); carboxen™/polydimethylsiloxane (CAR/PDMS, 75 μm) and the divinylbenzene/carboxen on polydimethylsiloxane (DVB/CAR/PDMS, 50/30 μm) (StableFlex). An objective comparison among different alcoholic beverages has been established in terms of qualitative and semi-quantitative differences on volatile and semi-volatile compounds. These compounds belong to several chemical families, including higher alcohols, ethyl esters, fatty acids, higher alcohol acetates, isoamyl esters, carbonyl compounds, furanic compounds, terpenoids, C13-norisoprenoids and volatile phenols. The optimized extraction conditions and GC–qMSD, lead to the successful identification of 44 compounds in white wines, 64 in beers and 104 in whiskys. Some of these compounds were found in all of the examined beverage samples. The main components of the HS-SPME found in white wines were ethyl octanoate (46.9%), ethyl decanoate (30.3%), ethyl 9-decenoate (10.7%), ethyl hexanoate (3.1%), and isoamyl octanoate (2.7%). As for beers, the major compounds were isoamyl alcohol (11.5%), ethyl octanoate (9.1%), isoamyl acetate (8.2%), 2-ethyl-1-hexanol (5.9%), and octanoic acid (5.5%). Ethyl decanoate (58.0%), ethyl octanoate (15.1%), ethyl dodecanoate (13.9%) followed by 3-methyl-1-butanol (1.8%) and isoamyl acetate (1.4%) were found to be the major VOCs in whisky samples.

Metamaterial inspired improved antennas and circuits

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior

Estudo do acoplamento entre superfícies seletivas de frequência assimétricas em estruturas de multicamadas

This work presents the development of new microwaves structures, filters and high gain antenna, through the cascading of frequency selective surfaces, which uses fractals Dürer and Minkowski patches as elements, addition of an element obtained from the combination of the other two simple the cross dipole and the square spiral. Frequency selective surfaces (FSS) includes a large area of Telecommunications and have been widely used due to its low cost, low weight and ability to integrate with others microwaves circuits. They re especially important in several applications, such as airplane, antennas systems, radomes, rockets, missiles, etc. FSS applications in high frequency ranges have been investigated, as well as applications of cascading structures or multi-layer, and active FSS. In this work, we present results for simulated and measured transmission characteristics of cascaded structures (multilayer), aiming to investigate the behavior of the operation in terms of bandwidth, one of the major problems presented by frequency selective surfaces. Comparisons are made with simulated results, obtained using commercial software such as Ansoft DesignerTM v3 and measured results in the laboratory. Finally, some suggestions are presented for future works on this subject

Análise do espalhamento espectral em superfícies de estruturas complexas para comunicações móveis

In this work, the transmission line method is explored on the study of the propagation phenomenon in nonhomogeneous walls with finite thickness. It is evaluated the efficiency and applicability of the method, considering materials like gypsum, wood and brick, found in the composition of the structures of walls in question. The results obtained in this work are compared to those available in the literature, for several particular cases. A good agreement is observed, showing that the performed analysis is accurate and efficient in modeling, for instance, the wave propagation through building walls and integrated circuit layers in mobile communication and radar system applications. Later, simulations of resistive sheets devices such as Salisbury screens and Jaumann absorbers and of transmission lines made of metal-insulator-semiconductor (MIS) are made. Thereafter, it is described a study on frequency surface selective structures (FSS). It is proposed the development of devices and microwave integrated circuits (MIC) of such structures, for the accomplishment of experiments. Finally, future works are suggested, for instance, on the development of reflectarrays, frequency selective surfaces with dissimilar elements, and coupled frequency selective surfaces with elements located on different layers

Desenvolvimento de um Sistema de Automação e Supervisão de Máquinas Dispensadoras Através da Internet

This paper aims to design and develop a control and monitoring system of vending machines, based on a Central Processing Unit with peripheral Internet communication. Coupled with the condom vending machines, a data acquisition module will be connected to the original circuits in order to collect and send, via internet, the information to the healthy government agencies, in the form of charts and reports. In the face of this, such agencies may analyze these data and compare them with the rates of reduction, in medium or long term, of the STD/AIDS in their respective regions, after the implementation of these vending machines, together with the conventional preventing programs. Reading the methodology, this paper is about an explaining and bibliography research, with the aspect of a qualitative-quantitative methodology, presenting a deductive method of approach and an indirect documentation technique research. About the results of the tests and simulations, we concluded that the implementation of this system will have the same success in any other type of dispenser machine

Absence of Klein's paradox for massive bosons coupled by nonminimal vector interactions

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Determination of fluoroacetate and fluoride in blood serum by capillary zone electrophoresis using capacitively coupled contactless conductivity detection

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Analysis of the Coupled Stretching-Bending Problem of Stiffened Plates by a BEM Formulation Based on Reissner's Hypothesis

In this work, the plate bending formulation of the boundary element method - BEM, based on the Reissner's hypothesis, is extended to the analysis of plates reinforced by beams taking into account the membrane effects. The formulation is derived by assuming a zoned body where each sub-region defines a beam or a slab and all of them are represented by a chosen reference surface. Equilibrium and compatibility conditions are automatically imposed by the integral equations, which treat this composed structure as a single body. In order to reduce the number of degrees of freedom, the problem values defined on the interfaces are written in terms of their values on the beam axis. Initially are derived separated equations for the bending and stretching problems, but in the final system of equations the two problems are coupled and can not be treated separately. Finally are presented some numerical examples whose analytical results are known to show the accuracy of the proposed model.

A BEM formulation for analysing the coupled stretching-bending problem of plates reinforced by rectangular beams with columns defined in the domain

In this work, a boundary element formulation to analyse plates reinforced by rectangular beams, with columns defined in the domain is proposed. The model is based on Kirchhoff hypothesis and the beams are not required to be displayed over the plate surface, therefore eccentricity effects are taken into account. The presented boundary element method formulation is derived by applying the reciprocity theorem to zoned plates, where beams are treated as thin sub-regions with larger rigidities. The integral representations derived for this complex structural element consider the bending and stretching effects of both structural elements working together. The standard equilibrium and compatibility conditions along interface are naturally imposed, being the bending tractions eliminated along interfaces. The in-plane tractions and the bending and in-plane displacements are approximated along the beam width, reducing the number of degrees of freedom. The columns are introduced into the formulation by considering domain points where tractions can be prescribed. Some examples are then shown to illustrate the accuracy of the formulation, comparing the obtained results with other numerical solutions.