975 resultados para CMOS synchronous circuits


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We experimentally demonstrate a novel synchronous 10.66Gbit/s DPSK OEO regenerator which uses a feed-forward carrier extraction scheme with an injection-locked laser to synchronize the regenerated signal wavelength to the incoming signal wavelength. After injection-locking, a low-cost DFB laser used at the regenerator exhibited the same linewidth characteristics as the narrow line-width transmitter laser. The phase regeneration properties of the regenerator were evaluated by emulating random Gaussian phase noise applied to the DPSK signal before the regenerator using a phase modulator driven by an arbitrary waveform generator. The overall performance was evaluated in terms of electrical eye-diagrams, BER measurements, and constellation diagrams.

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The selective aerobic oxidation of crotyl alcohol to crotonaldehyde was investigated by time-resolved synchronous DRIFTS/MS/XAS over silica and alumina supported Pd nanoparticles. Alcohol and oxygen reactant feeds were cycled through the catalyst bed while dynamic measurements of the palladium oxidation state, molecular adsorbates and evolved product distribution were made simultaneously on a sub-second timescale. Highly dispersed palladium nanoparticles remained in a partially oxidised state

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In-situ, synchronous MS/XANES reveals the Pd catalyzed selective aerobic oxidation of crotyl alcohol is regulated by the balance between the oxidation state and reducibility. Dynamic XANES measurements provide a new, rapid method to determine redox kinetics of nanoparticles and identify important parameters to optimize catalyst design. © 2012 American Chemical Society.

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Numerical optimisation of a 40 Gbit/s dispersion-managed soliton transmission system with in-line synchronous intensity modulation is performed. Using a time-saving numerical approach, superiority of the modified synchronous modulation over conventional synchronous modulation is demonstrated and an optimal operational regime is found.

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Numerical optimization is performed of the 40-Gb/s dispersion-managed (DM) soliton transmission system with in-line synchronous intensity modulation. Stability of DM soliton transmission results from a combined action of dispersion, nonlinearity, in-line filtering, and modulation through effective periodic bandwidth management of carrier pulses. Therefore, analysis of the multiparametric problem is typically required. A two-stage time-saving numerical optimization procedure is applied. At the first step, the regions of the stable carrier propagation are determined using theoretical models available for DM solitons, and system parameters are optimized. At the second stage, full numerical simulations are undertaken in order to verify the tolerance of optimal transmission regimes. An approach developed demonstrates feasibility of error-free transmission over 20 000 km in a transmission line composed of standard fiber and dispersion compensation fiber at 40 Gb/s.

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This paper presents an up to date review of digital watermarking (WM) from a VLSI designer point of view. The reader is introduced to basic principles and terms in the field of image watermarking. It goes through a brief survey on WM theory, laying out common classification criterions and discussing important design considerations and trade-offs. Elementary WM properties such as robustness, computational complexity and their influence on image quality are discussed. Common attacks and testing benchmarks are also briefly mentioned. It is shown that WM design must take the intended application into account. The difference between software and hardware implementations is explained through the introduction of a general scheme of a WM system and two examples from previous works. A versatile methodology to aid in a reliable and modular design process is suggested. Relating to mixed-signal VLSI design and testing, the proposed methodology allows an efficient development of a CMOS image sensor with WM capabilities.

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This paper presents implementation of a low-power tracking CMOS image sensor based on biological models of attention. The presented imager allows tracking of up to N salient targets in the field of view. Employing "smart" image sensor architecture, where all image processing is implemented on the sensor focal plane, the proposed imager allows reduction of the amount of data transmitted from the sensor array to external processing units and thus provides real time operation. The imager operation and architecture are based on the models taken from biological systems, where data sensed by many millions of receptors should be transmitted and processed in real time. The imager architecture is optimized to achieve low-power dissipation both in acquisition and tracking modes of operation. The tracking concept is presented, the system architecture is shown and the circuits description is discussed.

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Transient fully reconfigurable photonic circuits can be introduced at the optical fiber surface with subangstrom precision. A building block of these circuits - a 0.7Å-precise nano-bottle resonator - is experimentally created by local heating, translated, and annihilated.

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Electrically excited synchronous machines with brushes and slip rings are popular but hardly used in inflammable and explosive environments. This paper proposes a new brushless electrically excited synchronous motor with a hybrid rotor. It eliminates the use of brushes and slip rings so as to improve the reliability and cost-effectiveness of the traction drive. The proposed motor is characterized with two sets of stator windings with two different pole numbers to provide excitation and drive torque independently. This paper introduces the structure and operating principle of the machine, followed by the analysis of the air-gap magnetic field using the finite-element method. The influence of the excitation winding's pole number on the coupling capability is studied and the operating characteristics of the machine are simulated. These are further examined by the experimental tests on a 16 kW prototype motor. The machine is proved to have good static and dynamic performance, which meets the stringent requirements for traction applications.

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Permanent magnet synchronous motors (PMSMs) provide a competitive technology for EV traction drives owing to their high power density and high efficiency. In this paper, three types of interior PMSMs with different PM arrangements are modeled by the finite element method (FEM). For a given amount of permanent magnet materials, the V shape interior PMSM is found better than the U-shape and the conventional rotor topologies for EV traction drives. Then the V shape interior PMSM is further analyzed with the effects of stator slot opening and the permanent magnet pole chamfering on cogging torque and output torque performance. A vector-controlled flux-weakening method is developed and simulated in matlab to expand the motor speed range for EV drive system. The results show good dynamic and steady-state performance with a capability of expanding speed up to 4 times of the rated. A prototype of the V shape interior PMSM is also manufactured and tested to validate the numerical models built by the finite element method.

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The Brazilian Environmental Data Collecting System (SBCDA) collects and broadcasts meteorological and environmental data, to be handled by dozens of institutions and organizations. The system space segment, composed by the data collecting satellites, plays an important role for the system operation. To ensure the continuity and quality of these services, efforts are being made to the development of new satellite architectures. Aiming a reduction of size and power consumption, the design of an integrated circuit containing a receiver front-end is proposed, to be embedded in the next SBCDA satellite generations. The circuit will also operate under the requirements of the international data collecting standard ARGOS. This work focuses on the design of an UHF low noise amplifier and mixers in a CMOS standard technology. The specifi- cations are firstly described and the circuit topologies presented. Then the circuit conception is discussed and the design variables derived. Finally, the layout is designed and the final results are commented. The chip will be fabricated in a 130 nm technology from ST Microelectronics.

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The authors thank Professor Iber^e Luiz Caldas for the suggestions and encouragement. The authors F.F.G.d.S., R.M.R., J.C.S., and H.A.A. acknowledge the Brazilian agency CNPq and state agencies FAPEMIG, FAPESP, and FAPESC, and M.S.B. also acknowledges the EPSRC Grant Ref. No. EP/I032606/1.