Polymer gate dielectrics with self-assembled monolayers for high-mobility organic thin-film transistors based on copper phthalocyanine

Organic thin-film transistors based on polycrystalline copper phthalocyanine (CuPc) were fabricated by using poly(vinyl alcohol) as gate dielectric. After treatment of the gate dielectric using an octadecyltrichlorosilane self-assembled monolayer, a mobility of up to 0.11 cm2/V∈s was achieved, which is comparable to that of single-crystal CuPc devices (0.1-1 cm2/V∈s). The surface morphology was analyzed and the possible reasons for the enhanced mobility are discussed. © 2009 Springer-Verlag.

Progresses in organic field effect transistors and molecular electronics

In the past years, organic materials have been extensively investigated as an electronic material for organic field effect transistors (OFETs). In this paper, we briefly summarize the current status of organic field effect transistors including materials design, device physics, molecular electronics and the application of carbon nanotubes in molecular electronics. Future prospects and investigations required to improve the OFET performance are also involved.

Characterization of vertical Mo/diamond Schottky barrier diode from non-ideal I-V and C-V measurements based on MIS model

In this study, we investigated non-ideal characteristics of a diamond Schottky barrier diode with Molybdenum (Mo) Schottky metal fabricated by Microwave Plasma Chemical Vapour Deposition (MPCVD) technique. Extraction from forward bias I-V and reverse bias C- 2-V measurements yields ideality factor of 1.3, Schottky barrier height of 1.872 eV, and on-resistance of 32.63 mö·cm2. The deviation of extracted Schottky barrier height from an ideal value of 2.24 eV (considering Mo workfunction of 4.53 eV) indicates Fermi level pinning at the interface. We attributed such non-ideal behavior to the existence of thin interfacial layer and interface states between metal and diamond which forms Metal-Interfacial layer-Semiconductor (MIS) structure. Oxygen surface treatment during fabrication process might have induced them. From forward bias C-V characteristics, the minimum thickness of the interfacial layer is approximately 0.248 nm. Energy distribution profile of the interface state density is then evaluated from the forward bias I-V characteristics based on the MIS model. The interface state density is found to be uniformly distributed with values around 1013 eV - 1·cm- 2. © 2013 Elsevier B.V.

Non-ohmic contact resistance and field-effect mobility in nanocrystalline silicon thin film transistors

Contact resistance has a significant impact on the electrical characteristics of thin film transistors. It limits their maximum on-current and affects their subsequent behavior with bias. This distorts the extracted device parameters, in particular, the field-effect mobility. This letter presents a method capable of accounting for both the non-ohmic (nonlinear) and ohmic (linear) contact resistance effects solely based upon terminal I-V measurements. Applying our analysis to a nanocrystalline silicon thin film transistor, we demonstrate that contact resistance effects can lead to a twofold underestimation of the field-effect mobility. © 2008 American Institute of Physics.

Localized tail state distribution in amorphous oxide transistors deduced from low temperature measurements

In this paper, we extract density of localized tail states from measurements of low temperature conductance in amorphous oxide transistors. At low temperatures, trap-limited conduction prevails, allowing extraction of the trapped carrier distribution with energy. Using a test device with a-InGaZnO channel layer, the extracted tail state energy and density at the conduction band minima are 20 meV and 2 × 10 19 cm -3 eV -1, respectively, which are consistent with values reported in the literature. Also, the field-effect mobility as a function of temperature from 77 K to 300 K is retrieved for different gate voltages, yielding the activation energy and the percolation threshold. © 2012 American Institute of Physics.

Analytical field-effect method for extraction of subgap states in thin-film transistors

We present an analytical field-effect method to extract the density of subgap states (subgap DOS) in amorphous semiconductor thin-film transistors (TFTs), using a closed-form relationship between surface potential and gate voltage. By accounting the interface states in the subthreshold characteristics, the subgap DOS is retrieved, leading to a reasonably accurate description of field-effect mobility and its gate voltage dependence. The method proposed here is very useful not only in extracting device performance but also in physically based compact TFT modeling for circuit simulation. © 2012 IEEE.

Structural and optical characterization of vertical GaAs/GaP core-shell nanowires grown on Si substrates

GaAs nanowires were grown on Si (111) substrates. By coating a thin GaAs buffer layer on Si surface and using a two-temperature growth, the morphology and crystal structure of GaAs nanowires were dramatically improved. The strained GaAs/GaP core-shell nanowires, based on the improved GaAs nanowires with a shell thickness of 25 nm, showed a significant shift in emission energy of 260 meV from the unstrained GaAs nanowires. © 2010 IEEE.

A comparative study of transistors based on wurtzite and zincblende InAs nanowires

We report a comparative study of the electronic properties of nominally identical nanowire field-effect transistor (NW-FET) devices produced using 50 nm diameter InAs nanowires that differ only in phase: ZB on the one hand, and WZ on the other. We find much higher current densities in the ZB NW-FETs, and on/off ratios of up to 100. © 2010 IEEE.

Growth of GaAs/InAs vertical nanowires on GaAs (111)B by metalorganic chemical vapor deposition

The growth mechanism and properties of GaAs/InAs nanowires prepared by metalorganic chemical vapor deposition are investigated. Vertical InAs nanowires on GaAs (111)B substrates are successfully grown despite the large lattice mismatch (-7.2%). The crystallographic perfection of InAs nanowires is confirmed by hexagonal or triangular cross section. An interesting L-shaping of GaAs/InAs heterostructure nanowire which could be useful for novel device application is observed. © 2005 IEEE.

Vertical CNT-Si photodiode array.

A photodiode consisting of nanopillars of thin-film silicon p-i-n on an array of vertically aligned carbon nanotubes (CNTs) with a noncontinuous cathode electrode is demonstrated. The structure exploits the intrinsic enhancement of the CNTs' electric field, which leads to reduction in the photodiode's operating voltage and response time and enhancement of optical coupling due to better light trapping, as compared with the conventional planar photodiode. These improvements translate to higher resolution and higher frame rate flat-panel imaging systems for a broad range of applications, including computed tomography and particle detection.

A discretized proportional base driver for Silicon Carbide Bipolar Junction Transistors

Silicon Carbide Bipolar Junction Transistors require a continuous base current in the on-state. This base current is usually made constant and is corresponding to the maximum collector current and maximum junction temperature that is foreseen in a certain application. In this paper, a discretized proportional base driver is proposed which will reduce, for the right application, the steady-state power consumption of the base driver. The operation of the proposed base driver has been verified experimentally, driving a 1200V/40A SiC BJT in a DC-DC boost converter. In order to determine the potential reduction of the power consumption of the base driver, a case with a dc-dc converter in an ideal electric vehicle driving the new European drive cycle has been investigated. It is found that the steady-state power consumption of the base driver can be reduced by approximately 63 %. The total reduction of the driver consumption is 2816 J during the drive cycle, which is slightly more than the total on-state losses for the SiC BJTs used in the converter. © 2013 IEEE.

Ultrafast and widely tuneable vertical-external-cavity surface-emitting laser, mode-locked by a graphene-integrated distributed Bragg reflector

We report a versatile and cost-effective way of controlling the unsaturated loss, modulation depth and saturation fluence of graphene-based saturable absorbers (GSAs), by changing the thickness of a spacer between SLG and a high-reflection mirror. This allows us to modulate the electric field intensity enhancement at the GSA from 0 up to 400%, due to the interference of incident and reflected light at the mirror. The unsaturated loss of the SLG-mirror-assembly can be reduced to$\sim$0. We use this to mode-lock a VECSEL from 935 to 981nm. This approach can be applied to integrate SLG into various optical components, such as output coupler mirrors, dispersive mirrors, dielectric coatings on gain materials. Conversely, it can also be used to increase absorption (up to 10%) in various graphene based photonics and optoelectronics devices, such as photodetectors.