Mejoras tecnológicas en el reciclado de residuos de construcción y demolición (RCD)

La tesis doctoral “Mejoras Tecnológicas en el Reciclado de Residuos de Construcción y Demolición (RCD)” investiga la utilización de los separadores hidráulicos para mejorar la calidad de los áridos reciclados, y se demuestra que es un equipo más eficiente que las técnicas actuales basadas en la simple separación por densidad. En la tesisn se ha realizado inicialmente una revisión de la situación del sector, para a continuación centrarse en los sistemas de separación utilizados en las plantas de valorización españolas. Una vez analizados éstos y en particular los de tipo hidráulico, de los que se resume un estudio comparativo, se ha procedido a ensayar a escala de Laboratorio el comportamiento de un separador hidráulico de aceleración diferencial con diversos materiales procedentes de tres plantas de reciclaje. Adicionalmente fueron probadas otras técnicas, como es la separación magnética para mejorar la calidad de los productos reciclados. En vista de los buenos resultados de la investigación, se procede a escalar los ensayos con equipo piloto y distintas composiciones de naturaleza cerámica y hormigón. El equipo utilizado fue un jig de 3´x 1´ en el que se ensayaron las tres muestras con resultados diferentes. La limpieza de los materiales impropios y el yeso fue positiva en las tres muestras, y únicamente la separación entre sí de los componentes pétreos, resultó dependiente de su proporción en la mezcla, obteniéndose los mejores resultados en las muestras con menor cantidad de materiales cerámicos. Finalmente, se procede a analizar en un laboratorio reconocido las propiedades de los áridos reciclados obtenidos en la separación hidráulica por jig, y constatar las mejoras conseguidas para su utilización como materiales de construcción en usos ligados y no ligados. Todo lo anterior permite afirmar que los equipos de separación hidráulica con aceleración diferencial (jig) presentan una innovación tecnológica en el reciclado de los residuos de construcción y demolición (RCD). ABSTRACT The doctoral thesis “Technological Improvements in Recycling of Construction and Demolition Waste (C&DW)” researches the hydraulic separators utilization in order to improve the recycled aggregates quality, demonstrating that the equipment is more efficient than the current techniques based on the simple density separation. This doctoral thesis has been initially done reviewing the situation of the sector and focusing afterwards on the separation systems used at the Spanish recovery facilities. Once analyzed these and, particularly, the hydraulic type ones, from which a comparative study has been summarized, the behavior of a differential acceleration hydraulic separator with various materials coming from three recycling plants has been tested at laboratory scale. Additionally other techniques have been tested, such as the magnetic separation to improve the quality of recycled products. In view of the good investigation results, the testing process scaled up by using pilot equipment and different ceramics and concrete compositions. The equipment utilized was a jig 3” x 1”, in which the three samples were tested with different results. The unsuitable materials and gypsum cleanliness was positive on the three samples and only the separation among the stony components turned out to be dependent of its proportion in the mixing, obtaining the best results in the samples with less quantity of ceramic materials. Finally, the properties of the recycled aggregates obtained by jig hydraulic separation are analyzed at a recognized laboratory and the improvements gained for their utilization as construction materials, in bounded and unbounded uses, are stated. The facts cited are a basis for affirming that the hydraulic separator equipments with differential acceleration (jig) offer a technological innovation in the Recycling of Construction and Demolition Waste (C&DW).

Spatial variability patterns of some Vertisol properties at a field scale using standardized data

Spatial variability of Vertisol properties is relevant for identifying those zones with physical degradation. In this sense, one has to face the problem of identifying the origin and distribution of spatial variability patterns. The objectives of the present work were (i) to quantify the spatial structure of different physical properties collected from a Vertisol, (ii) to search for potential correlations between different spatial patterns and (iii) to identify relevant components through multivariate spatial analysis. The study was conducted on a Vertisol (Typic Hapludert) dedicated to sugarcane (Saccharum officinarum L.) production during the last sixty years. We used six soil properties collected from a squared grid (225 points) (penetrometer resistance (PR), total porosity, fragmentation dimension (Df), vertical electrical conductivity (ECv), horizontal electrical conductivity (ECh) and soil water content (WC)). All the original data sets were z-transformed before geostatistical analysis. Three different types of semivariogram models were necessary for fitting individual experimental semivariograms. This suggests the different natures of spatial variability patterns. Soil water content rendered the largest nugget effect (C0 = 0.933) while soil total porosity showed the largest range of spatial correlation (A = 43.92 m). The bivariate geostatistical analysis also rendered significant cross-semivariance between different paired soil properties. However, four different semivariogram models were required in that case. This indicates an underlying co-regionalization between different soil properties, which is of interest for delineating management zones within sugarcane fields. Cross-semivariograms showed larger correlation ranges than individual, univariate, semivariograms (A ≥ 29 m). All the findings were supported by multivariate spatial analysis, which showed the influence of soil tillage operations, harvesting machinery and irrigation water distribution on the status of the investigated area.

Mechanical design optimization for multi-finger haptic devices applied to virtual grasping manipulation

This paper describes the design of a modular multi-finger haptic device for virtual object manipulation. Mechanical structures are based on one module per finger and can be scaled up to three fingers. Mechanical configurations for two and three fingers are based on the use of one and two redundant axes, respectively. As demonstrated, redundant axes significantly increase workspace and prevent link collisions, which is their main asset with respect to other multi-finger haptic devices. The location of redundant axes and link dimensions have been optimized in order to guarantee a proper workspace, manipulability, force capability, and inertia for the device. The mechanical haptic device design and a thimble adaptable to different finger sizes have also been developed for virtual object manipulation.

Low-dimensional modeling of streaks in a wedge flow boundary layer

This paper is concerned with the low dimensional structure of optimal streaks in a wedge flow boundary layer, which have been recently shown to consist of a unique (up to a constant factor) three-dimensional streamwise evolving mode, known as the most unstable streaky mode. Optimal streaks exhibit a still unexplored/unexploited approximate self-similarity (not associated with the boundary layer self-similarity), namely the streamwise velocity re-scaled with their maximum remains almost independent of both the spanwise wavenumber and the streamwise coordinate; the remaining two velocity components instead do not satisfy this property. The approximate self-similar behavior is analyzed here and exploited to further simplify the description of optimal streaks. In particular, it is shown that streaks can be approximately described in terms of the streamwise evolution of the scalar amplitudes of just three one-dimensional modes, providing the wall normal profiles of the streamwise velocity and two combinations of the cross flow velocity components; the scalar amplitudes obey a singular system of three ordinary differential equations (involving only two degrees of freedom), which approximates well the streamwise evolution of the general streaks.

Orbital debris mitigation through deorbiting with passive electrodynamic drag

The increase of orbital debris and the consequent proliferation of smaller objects through fragmentation are driving the need for mitigation strategies. The issue is how to deorbit the satellite with an efficient system that does not impair drastically the propellant budget of the satellite and, consequently, reduces its operating life. We have been investigating, in the framework of a European-Community-funded project, a passive system that makes use of an electrodynamics tether to deorbit a satellite through Lorentz forces. The deorbiting system will be carried by the satellite itself at launch and deployed from the satellite at the end of its life. From that moment onward the system operates passively without requiring any intervention from the satellite itself. The paper summarizes the results of the analysis carried out to show the deorbiting performance of the system starting from different orbital altitudes and inclinations for a reference satellite mass. Results can be easily scaled to other satellite masses. The results have been obtained by using a high-fidelity computer model that uses the latest environmental routines for magnetic field, ionospheric density, atmospheric density and a gravity field model. The tether dynamics is modelled by considering all the main aspects of a real system as the tether flexibility and its temperature-dependent electrical conductivity. Temperature variations are computed by including all the major external and internal input fluxes and the thermal flux emitted from the tether. The results shows that a relatively compact and light system can carry out the complete deorbit of a relatively large satellite in a time ranging from a month to less than a year starting from high LEO with the best performance occurring at low orbital inclinations.

Viabilidad técnica para la explotación y separación isotópica de Li y prospectiva en el mercado de baterías de ION-7Li y de 6Li como material base de diseño en reactores de fusión nuclear

En claro alineamiento con estrategias de sostenibilidad en el uso de recursos naturales en un escenario constante de aumento de la demanda energética mundial, el desarrollo de la tecnología energética en la Historia de la Especie Humana muestra un vector de evolución permanente desde su origen en el sentido del desarrollo y uso de nuevas fuentes energéticas con la explotación de recursos naturales de manera más eficiente: soluciones energéticas con aumento de la densidad energética (exoenergía de proceso por unidad de masa de recurso natural). Así el cambio de escala en la demanda de explotación del Litio como recurso natural se viene presentando en la última década ligada al desarrollo del mercado de las baterías "ion-Litio" y los requisitos de combustible (Deuterio y Litio) en el camino de la fusión nuclear como opción energética próxima. El análisis anticipado de las demandas sinérgicas a escala de ambos mercados aparece de enorme interés prospectivo en sus aspectos técnicos: (1) tecnologías de base para la extracción mineral y de agua marina y (2) su enriquecimiento isotópico (de interés sinérgico; 7Li para baterías eficientes ion-litio; 6Li como regenerador de tritio en ciclo de combustible en fusión nuclear) a la vez que en sus aspectos económicos. Este Proyecto realiza: (1) un ejercicio de análisis prospectivo de la demanda y de mercado para el enriquecimiento 6Li/7Li para las próximas décadas, (2) se califican los desarrollos tecnológicos específicos que van a poder permitir la producción a escala conforme a la demanda; (3) se selecciona y califica una técnica [de centrifugación / termo-difusión/ destilación combinada] como opción tecnológicamente viable para la producción a escala de formas litiadas; (4) se propone un diseño conceptual de planta de producción y finalmente (5) propone un estudio de viabilidad para la demostración de proceso y construcción de dicha planta de demostración de la nueva capacidad tecnológica. ABSTRACT Clearly aligned with sustainability strategies under growing world energy demand in the use of natural resources the development of energy technology in the history of the human species shows a vector of ongoing evolution from its origin in the sense of the development and use of new energy sources with the exploitation of natural resources in a more efficient manner. The change of scale in the demand for exploitation of Lithium as a natural resource appears during the last decade as bound to the deployment of "lithium-ion" batteries market and to the Nuclear Fusion fuels (deuterium and lithium) supply scaled demands. The prospective analysis of demands to scale in both markets appears in scene with huge prospective interest in its technical aspects: (1) base technologies for mineral and water marine extraction (2) its isotopic enrichment (synergistic interests; 7Li efficient battery Li-ion; 6Li as fusion nuclear fuel breeder (tritium) as well as in its economic aspects. This Project: (1) propose a prospective analysis exercise of the synergistic supply demand for coming decades for the enrichment of 6Li and 7Li, (2) qualifies specific technological developments ongoing to respond to supply demand; (3) select and qualifies an appropriate technique [combined centrifugation/thermo-diffusion/distillation] as technologically viable option for lithiated forms scaled-production; (4) proposes a conceptual design of production plant based on the technique and finally (5) proposes a feasibility study for the process demonstration and construction of this new technological capability Demonstration Plant.

Shaking table tests of a RC frame structure equipped with hysteretic dampers

This paper provides partial results of an on-going research aimed at investigating the seismic response of reinforced concrete (RC) frames equipped with hysteretic-type energy dissipating devices (EDD). From a prototype RC frame structure designed only for gravity loads, a test model scaled in geometry to 2/5 was defined and built in the Laboratory of Structures of the University of Granada. Four EDDs were installed in the test model to provide the same seismic resistance than a conventional RC bare frame designed for sustain gravity and seismic loads following current codes. The test model with EDDs was subjected to several seismic simulations with the shaking table of Laboratory of structures of the University of Granada. The test results provide empirical evidences on the efficiency of the EDDs to prevent damage on the main frame and concentrating the inelastic deformations on the EDDs.

Scaling of the coercivity with the geometrical parameters in epitaxial Fe antidot arrays

We studied a series of square lattice antidot arrays, with diameter and lattice parameter from hundreds of nanometers to some microns, fabricated using two lithography techniques in epitaxial Fe(001) films. The coercivity increase of each array with respect to its base film can be scaled to a simple geometric parameter, irrespective of the lithography technique employed. Magnetic transmission x-ray microscopy studies, in arrays fabricated on polycrystalline Fe films deposited on silicon nitride membranes, evidenced the propagation of reversed domains from the edges of the arrays, in agreement with the coercivity analysis of the epitaxial arrays and with micromagnetic models.

Low-Dimensional Modelling for optimal streaks in the blasius boundary layer

This paper is concerned with the low dimensional structure of optimal streaks in the Blasius boundary layer. Optimal streaks are well known to exhibit an approximate self-similarity, namely the streamwise velocity re-scaled with their maximum remains almost independent of both the spanwise wavenumber and the streamwise coordinate. However, the reason of this self-similar behavior is still unexplained as well as unexploited. After revisiting the structure of the streaks near the leading edge singularity, two additional approximately self-similar relations involving the velocity components and their wall normal derivatives are identified. Based on these properties, we derive a low dimensional model with two degrees of freedom. The comparison with the results obtained from the linearized boundary layer equations shows that this model is consistent and provide good approximations.

Run-Time Scalable Hardware for Reconfigurable Systems

La optimización de parámetros tales como el consumo de potencia, la cantidad de recursos lógicos empleados o la ocupación de memoria ha sido siempre una de las preocupaciones principales a la hora de diseñar sistemas embebidos. Esto es debido a que se trata de sistemas dotados de una cantidad de recursos limitados, y que han sido tradicionalmente empleados para un propósito específico, que permanece invariable a lo largo de toda la vida útil del sistema. Sin embargo, el uso de sistemas embebidos se ha extendido a áreas de aplicación fuera de su ámbito tradicional, caracterizadas por una mayor demanda computacional. Así, por ejemplo, algunos de estos sistemas deben llevar a cabo un intenso procesado de señales multimedia o la transmisión de datos mediante sistemas de comunicaciones de alta capacidad. Por otra parte, las condiciones de operación del sistema pueden variar en tiempo real. Esto sucede, por ejemplo, si su funcionamiento depende de datos medidos por el propio sistema o recibidos a través de la red, de las demandas del usuario en cada momento, o de condiciones internas del propio dispositivo, tales como la duración de la batería. Como consecuencia de la existencia de requisitos de operación dinámicos es necesario ir hacia una gestión dinámica de los recursos del sistema. Si bien el software es inherentemente flexible, no ofrece una potencia computacional tan alta como el hardware. Por lo tanto, el hardware reconfigurable aparece como una solución adecuada para tratar con mayor flexibilidad los requisitos variables dinámicamente en sistemas con alta demanda computacional. La flexibilidad y adaptabilidad del hardware requieren de dispositivos reconfigurables que permitan la modificación de su funcionalidad bajo demanda. En esta tesis se han seleccionado las FPGAs (Field Programmable Gate Arrays) como los dispositivos más apropiados, hoy en día, para implementar sistemas basados en hardware reconfigurable De entre todas las posibilidades existentes para explotar la capacidad de reconfiguración de las FPGAs comerciales, se ha seleccionado la reconfiguración dinámica y parcial. Esta técnica consiste en substituir una parte de la lógica del dispositivo, mientras el resto continúa en funcionamiento. La capacidad de reconfiguración dinámica y parcial de las FPGAs es empleada en esta tesis para tratar con los requisitos de flexibilidad y de capacidad computacional que demandan los dispositivos embebidos. La propuesta principal de esta tesis doctoral es el uso de arquitecturas de procesamiento escalables espacialmente, que son capaces de adaptar su funcionalidad y rendimiento en tiempo real, estableciendo un compromiso entre dichos parámetros y la cantidad de lógica que ocupan en el dispositivo. A esto nos referimos con arquitecturas con huellas escalables. En particular, se propone el uso de arquitecturas altamente paralelas, modulares, regulares y con una alta localidad en sus comunicaciones, para este propósito. El tamaño de dichas arquitecturas puede ser modificado mediante la adición o eliminación de algunos de los módulos que las componen, tanto en una dimensión como en dos. Esta estrategia permite implementar soluciones escalables, sin tener que contar con una versión de las mismas para cada uno de los tamaños posibles de la arquitectura. De esta manera se reduce significativamente el tiempo necesario para modificar su tamaño, así como la cantidad de memoria necesaria para almacenar todos los archivos de configuración. En lugar de proponer arquitecturas para aplicaciones específicas, se ha optado por patrones de procesamiento genéricos, que pueden ser ajustados para solucionar distintos problemas en el estado del arte. A este respecto, se proponen patrones basados en esquemas sistólicos, así como de tipo wavefront. Con el objeto de poder ofrecer una solución integral, se han tratado otros aspectos relacionados con el diseño y el funcionamiento de las arquitecturas, tales como el control del proceso de reconfiguración de la FPGA, la integración de las arquitecturas en el resto del sistema, así como las técnicas necesarias para su implementación. Por lo que respecta a la implementación, se han tratado distintos aspectos de bajo nivel dependientes del dispositivo. Algunas de las propuestas realizadas a este respecto en la presente tesis doctoral son un router que es capaz de garantizar el correcto rutado de los módulos reconfigurables dentro del área destinada para ellos, así como una estrategia para la comunicación entre módulos que no introduce ningún retardo ni necesita emplear recursos configurables del dispositivo. El flujo de diseño propuesto se ha automatizado mediante una herramienta denominada DREAMS. La herramienta se encarga de la modificación de las netlists correspondientes a cada uno de los módulos reconfigurables del sistema, y que han sido generadas previamente mediante herramientas comerciales. Por lo tanto, el flujo propuesto se entiende como una etapa de post-procesamiento, que adapta esas netlists a los requisitos de la reconfiguración dinámica y parcial. Dicha modificación la lleva a cabo la herramienta de una forma completamente automática, por lo que la productividad del proceso de diseño aumenta de forma evidente. Para facilitar dicho proceso, se ha dotado a la herramienta de una interfaz gráfica. El flujo de diseño propuesto, y la herramienta que lo soporta, tienen características específicas para abordar el diseño de las arquitecturas dinámicamente escalables propuestas en esta tesis. Entre ellas está el soporte para el realojamiento de módulos reconfigurables en posiciones del dispositivo distintas a donde el módulo es originalmente implementado, así como la generación de estructuras de comunicación compatibles con la simetría de la arquitectura. El router has sido empleado también en esta tesis para obtener un rutado simétrico entre nets equivalentes. Dicha posibilidad ha sido explotada para aumentar la protección de circuitos con altos requisitos de seguridad, frente a ataques de canal lateral, mediante la implantación de lógica complementaria con rutado idéntico. Para controlar el proceso de reconfiguración de la FPGA, se propone en esta tesis un motor de reconfiguración especialmente adaptado a los requisitos de las arquitecturas dinámicamente escalables. Además de controlar el puerto de reconfiguración, el motor de reconfiguración ha sido dotado de la capacidad de realojar módulos reconfigurables en posiciones arbitrarias del dispositivo, en tiempo real. De esta forma, basta con generar un único bitstream por cada módulo reconfigurable del sistema, independientemente de la posición donde va a ser finalmente reconfigurado. La estrategia seguida para implementar el proceso de realojamiento de módulos es diferente de las propuestas existentes en el estado del arte, pues consiste en la composición de los archivos de configuración en tiempo real. De esta forma se consigue aumentar la velocidad del proceso, mientras que se reduce la longitud de los archivos de configuración parciales a almacenar en el sistema. El motor de reconfiguración soporta módulos reconfigurables con una altura menor que la altura de una región de reloj del dispositivo. Internamente, el motor se encarga de la combinación de los frames que describen el nuevo módulo, con la configuración existente en el dispositivo previamente. El escalado de las arquitecturas de procesamiento propuestas en esta tesis también se puede beneficiar de este mecanismo. Se ha incorporado también un acceso directo a una memoria externa donde se pueden almacenar bitstreams parciales. Para acelerar el proceso de reconfiguración se ha hecho funcionar el ICAP por encima de la máxima frecuencia de reloj aconsejada por el fabricante. Así, en el caso de Virtex-5, aunque la máxima frecuencia del reloj deberían ser 100 MHz, se ha conseguido hacer funcionar el puerto de reconfiguración a frecuencias de operación de hasta 250 MHz, incluyendo el proceso de realojamiento en tiempo real. Se ha previsto la posibilidad de portar el motor de reconfiguración a futuras familias de FPGAs. Por otro lado, el motor de reconfiguración se puede emplear para inyectar fallos en el propio dispositivo hardware, y así ser capaces de evaluar la tolerancia ante los mismos que ofrecen las arquitecturas reconfigurables. Los fallos son emulados mediante la generación de archivos de configuración a los que intencionadamente se les ha introducido un error, de forma que se modifica su funcionalidad. Con el objetivo de comprobar la validez y los beneficios de las arquitecturas propuestas en esta tesis, se han seguido dos líneas principales de aplicación. En primer lugar, se propone su uso como parte de una plataforma adaptativa basada en hardware evolutivo, con capacidad de escalabilidad, adaptabilidad y recuperación ante fallos. En segundo lugar, se ha desarrollado un deblocking filter escalable, adaptado a la codificación de vídeo escalable, como ejemplo de aplicación de las arquitecturas de tipo wavefront propuestas. El hardware evolutivo consiste en el uso de algoritmos evolutivos para diseñar hardware de forma autónoma, explotando la flexibilidad que ofrecen los dispositivos reconfigurables. En este caso, los elementos de procesamiento que componen la arquitectura son seleccionados de una biblioteca de elementos presintetizados, de acuerdo con las decisiones tomadas por el algoritmo evolutivo, en lugar de definir la configuración de las mismas en tiempo de diseño. De esta manera, la configuración del core puede cambiar cuando lo hacen las condiciones del entorno, en tiempo real, por lo que se consigue un control autónomo del proceso de reconfiguración dinámico. Así, el sistema es capaz de optimizar, de forma autónoma, su propia configuración. El hardware evolutivo tiene una capacidad inherente de auto-reparación. Se ha probado que las arquitecturas evolutivas propuestas en esta tesis son tolerantes ante fallos, tanto transitorios, como permanentes y acumulativos. La plataforma evolutiva se ha empleado para implementar filtros de eliminación de ruido. La escalabilidad también ha sido aprovechada en esta aplicación. Las arquitecturas evolutivas escalables permiten la adaptación autónoma de los cores de procesamiento ante fluctuaciones en la cantidad de recursos disponibles en el sistema. Por lo tanto, constituyen un ejemplo de escalabilidad dinámica para conseguir un determinado nivel de calidad, que puede variar en tiempo real. Se han propuesto dos variantes de sistemas escalables evolutivos. El primero consiste en un único core de procesamiento evolutivo, mientras que el segundo está formado por un número variable de arrays de procesamiento. La codificación de vídeo escalable, a diferencia de los codecs no escalables, permite la decodificación de secuencias de vídeo con diferentes niveles de calidad, de resolución temporal o de resolución espacial, descartando la información no deseada. Existen distintos algoritmos que soportan esta característica. En particular, se va a emplear el estándar Scalable Video Coding (SVC), que ha sido propuesto como una extensión de H.264/AVC, ya que este último es ampliamente utilizado tanto en la industria, como a nivel de investigación. Para poder explotar toda la flexibilidad que ofrece el estándar, hay que permitir la adaptación de las características del decodificador en tiempo real. El uso de las arquitecturas dinámicamente escalables es propuesto en esta tesis con este objetivo. El deblocking filter es un algoritmo que tiene como objetivo la mejora de la percepción visual de la imagen reconstruida, mediante el suavizado de los "artefactos" de bloque generados en el lazo del codificador. Se trata de una de las tareas más intensivas en procesamiento de datos de H.264/AVC y de SVC, y además, su carga computacional es altamente dependiente del nivel de escalabilidad seleccionado en el decodificador. Por lo tanto, el deblocking filter ha sido seleccionado como prueba de concepto de la aplicación de las arquitecturas dinámicamente escalables para la compresión de video. La arquitectura propuesta permite añadir o eliminar unidades de computación, siguiendo un esquema de tipo wavefront. La arquitectura ha sido propuesta conjuntamente con un esquema de procesamiento en paralelo del deblocking filter a nivel de macrobloque, de tal forma que cuando se varía del tamaño de la arquitectura, el orden de filtrado de los macrobloques varia de la misma manera. El patrón propuesto se basa en la división del procesamiento de cada macrobloque en dos etapas independientes, que se corresponden con el filtrado horizontal y vertical de los bloques dentro del macrobloque. Las principales contribuciones originales de esta tesis son las siguientes: - El uso de arquitecturas altamente regulares, modulares, paralelas y con una intensa localidad en sus comunicaciones, para implementar cores de procesamiento dinámicamente reconfigurables. - El uso de arquitecturas bidimensionales, en forma de malla, para construir arquitecturas dinámicamente escalables, con una huella escalable. De esta forma, las arquitecturas permiten establecer un compromiso entre el área que ocupan en el dispositivo, y las prestaciones que ofrecen en cada momento. Se proponen plantillas de procesamiento genéricas, de tipo sistólico o wavefront, que pueden ser adaptadas a distintos problemas de procesamiento. - Un flujo de diseño y una herramienta que lo soporta, para el diseño de sistemas reconfigurables dinámicamente, centradas en el diseño de las arquitecturas altamente paralelas, modulares y regulares propuestas en esta tesis. - Un esquema de comunicaciones entre módulos reconfigurables que no introduce ningún retardo ni requiere el uso de recursos lógicos propios. - Un router flexible, capaz de resolver los conflictos de rutado asociados con el diseño de sistemas reconfigurables dinámicamente. - Un algoritmo de optimización para sistemas formados por múltiples cores escalables que optimice, mediante un algoritmo genético, los parámetros de dicho sistema. Se basa en un modelo conocido como el problema de la mochila. - Un motor de reconfiguración adaptado a los requisitos de las arquitecturas altamente regulares y modulares. Combina una alta velocidad de reconfiguración, con la capacidad de realojar módulos en tiempo real, incluyendo el soporte para la reconfiguración de regiones que ocupan menos que una región de reloj, así como la réplica de un módulo reconfigurable en múltiples posiciones del dispositivo. - Un mecanismo de inyección de fallos que, empleando el motor de reconfiguración del sistema, permite evaluar los efectos de fallos permanentes y transitorios en arquitecturas reconfigurables. - La demostración de las posibilidades de las arquitecturas propuestas en esta tesis para la implementación de sistemas de hardware evolutivos, con una alta capacidad de procesamiento de datos. - La implementación de sistemas de hardware evolutivo escalables, que son capaces de tratar con la fluctuación de la cantidad de recursos disponibles en el sistema, de una forma autónoma. - Una estrategia de procesamiento en paralelo para el deblocking filter compatible con los estándares H.264/AVC y SVC que reduce el número de ciclos de macrobloque necesarios para procesar un frame de video. - Una arquitectura dinámicamente escalable que permite la implementación de un nuevo deblocking filter, totalmente compatible con los estándares H.264/AVC y SVC, que explota el paralelismo a nivel de macrobloque. El presente documento se organiza en siete capítulos. En el primero se ofrece una introducción al marco tecnológico de esta tesis, especialmente centrado en la reconfiguración dinámica y parcial de FPGAs. También se motiva la necesidad de las arquitecturas dinámicamente escalables propuestas en esta tesis. En el capítulo 2 se describen las arquitecturas dinámicamente escalables. Dicha descripción incluye la mayor parte de las aportaciones a nivel arquitectural realizadas en esta tesis. Por su parte, el flujo de diseño adaptado a dichas arquitecturas se propone en el capítulo 3. El motor de reconfiguración se propone en el 4, mientras que el uso de dichas arquitecturas para implementar sistemas de hardware evolutivo se aborda en el 5. El deblocking filter escalable se describe en el 6, mientras que las conclusiones finales de esta tesis, así como la descripción del trabajo futuro, son abordadas en el capítulo 7. ABSTRACT The optimization of system parameters, such as power dissipation, the amount of hardware resources and the memory footprint, has been always a main concern when dealing with the design of resource-constrained embedded systems. This situation is even more demanding nowadays. Embedded systems cannot anymore be considered only as specific-purpose computers, designed for a particular functionality that remains unchanged during their lifetime. Differently, embedded systems are now required to deal with more demanding and complex functions, such as multimedia data processing and high-throughput connectivity. In addition, system operation may depend on external data, the user requirements or internal variables of the system, such as the battery life-time. All these conditions may vary at run-time, leading to adaptive scenarios. As a consequence of both the growing computational complexity and the existence of dynamic requirements, dynamic resource management techniques for embedded systems are needed. Software is inherently flexible, but it cannot meet the computing power offered by hardware solutions. Therefore, reconfigurable hardware emerges as a suitable technology to deal with the run-time variable requirements of complex embedded systems. Adaptive hardware requires the use of reconfigurable devices, where its functionality can be modified on demand. In this thesis, Field Programmable Gate Arrays (FPGAs) have been selected as the most appropriate commercial technology existing nowadays to implement adaptive hardware systems. There are different ways of exploiting reconfigurability in reconfigurable devices. Among them is dynamic and partial reconfiguration. This is a technique which consists in substituting part of the FPGA logic on demand, while the rest of the device continues working. The strategy followed in this thesis is to exploit the dynamic and partial reconfiguration of commercial FPGAs to deal with the flexibility and complexity demands of state-of-the-art embedded systems. The proposal of this thesis to deal with run-time variable system conditions is the use of spatially scalable processing hardware IP cores, which are able to adapt their functionality or performance at run-time, trading them off with the amount of logic resources they occupy in the device. This is referred to as a scalable footprint in the context of this thesis. The distinguishing characteristic of the proposed cores is that they rely on highly parallel, modular and regular architectures, arranged in one or two dimensions. These architectures can be scaled by means of the addition or removal of the composing blocks. This strategy avoids implementing a full version of the core for each possible size, with the corresponding benefits in terms of scaling and adaptation time, as well as bitstream storage memory requirements. Instead of providing specific-purpose architectures, generic architectural templates, which can be tuned to solve different problems, are proposed in this thesis. Architectures following both systolic and wavefront templates have been selected. Together with the proposed scalable architectural templates, other issues needed to ensure the proper design and operation of the scalable cores, such as the device reconfiguration control, the run-time management of the architecture and the implementation techniques have been also addressed in this thesis. With regard to the implementation of dynamically reconfigurable architectures, device dependent low-level details are addressed. Some of the aspects covered in this thesis are the area constrained routing for reconfigurable modules, or an inter-module communication strategy which does not introduce either extra delay or logic overhead. The system implementation, from the hardware description to the device configuration bitstream, has been fully automated by modifying the netlists corresponding to each of the system modules, which are previously generated using the vendor tools. This modification is therefore envisaged as a post-processing step. Based on these implementation proposals, a design tool called DREAMS (Dynamically Reconfigurable Embedded and Modular Systems) has been created, including a graphic user interface. The tool has specific features to cope with modular and regular architectures, including the support for module relocation and the inter-module communications scheme based on the symmetry of the architecture. The core of the tool is a custom router, which has been also exploited in this thesis to obtain symmetric routed nets, with the aim of enhancing the protection of critical reconfigurable circuits against side channel attacks. This is achieved by duplicating the logic with an exactly equal routing. In order to control the reconfiguration process of the FPGA, a Reconfiguration Engine suited to the specific requirements set by the proposed architectures was also proposed. Therefore, in addition to controlling the reconfiguration port, the Reconfiguration Engine has been enhanced with the online relocation ability, which allows employing a unique configuration bitstream for all the positions where the module may be placed in the device. Differently to the existing relocating solutions, which are based on bitstream parsers, the proposed approach is based on the online composition of bitstreams. This strategy allows increasing the speed of the process, while the length of partial bitstreams is also reduced. The height of the reconfigurable modules can be lower than the height of a clock region. The Reconfiguration Engine manages the merging process of the new and the existing configuration frames within each clock region. The process of scaling up and down the hardware cores also benefits from this technique. A direct link to an external memory where partial bitstreams can be stored has been also implemented. In order to accelerate the reconfiguration process, the ICAP has been overclocked over the speed reported by the manufacturer. In the case of Virtex-5, even though the maximum frequency of the ICAP is reported to be 100 MHz, valid operations at 250 MHz have been achieved, including the online relocation process. Portability of the reconfiguration solution to today's and probably, future FPGAs, has been also considered. The reconfiguration engine can be also used to inject faults in real hardware devices, and this way being able to evaluate the fault tolerance offered by the reconfigurable architectures. Faults are emulated by introducing partial bitstreams intentionally modified to provide erroneous functionality. To prove the validity and the benefits offered by the proposed architectures, two demonstration application lines have been envisaged. First, scalable architectures have been employed to develop an evolvable hardware platform with adaptability, fault tolerance and scalability properties. Second, they have been used to implement a scalable deblocking filter suited to scalable video coding. Evolvable Hardware is the use of evolutionary algorithms to design hardware in an autonomous way, exploiting the flexibility offered by reconfigurable devices. In this case, processing elements composing the architecture are selected from a presynthesized library of processing elements, according to the decisions taken by the algorithm, instead of being decided at design time. This way, the configuration of the array may change as run-time environmental conditions do, achieving autonomous control of the dynamic reconfiguration process. Thus, the self-optimization property is added to the native self-configurability of the dynamically scalable architectures. In addition, evolvable hardware adaptability inherently offers self-healing features. The proposal has proved to be self-tolerant, since it is able to self-recover from both transient and cumulative permanent faults. The proposed evolvable architecture has been used to implement noise removal image filters. Scalability has been also exploited in this application. Scalable evolvable hardware architectures allow the autonomous adaptation of the processing cores to a fluctuating amount of resources available in the system. Thus, it constitutes an example of the dynamic quality scalability tackled in this thesis. Two variants have been proposed. The first one consists in a single dynamically scalable evolvable core, and the second one contains a variable number of processing cores. Scalable video is a flexible approach for video compression, which offers scalability at different levels. Differently to non-scalable codecs, a scalable video bitstream can be decoded with different levels of quality, spatial or temporal resolutions, by discarding the undesired information. The interest in this technology has been fostered by the development of the Scalable Video Coding (SVC) standard, as an extension of H.264/AVC. In order to exploit all the flexibility offered by the standard, it is necessary to adapt the characteristics of the decoder to the requirements of each client during run-time. The use of dynamically scalable architectures is proposed in this thesis with this aim. The deblocking filter algorithm is the responsible of improving the visual perception of a reconstructed image, by smoothing blocking artifacts generated in the encoding loop. This is one of the most computationally intensive tasks of the standard, and furthermore, it is highly dependent on the selected scalability level in the decoder. Therefore, the deblocking filter has been selected as a proof of concept of the implementation of dynamically scalable architectures for video compression. The proposed architecture allows the run-time addition or removal of computational units working in parallel to change its level of parallelism, following a wavefront computational pattern. Scalable architecture is offered together with a scalable parallelization strategy at the macroblock level, such that when the size of the architecture changes, the macroblock filtering order is modified accordingly. The proposed pattern is based on the division of the macroblock processing into two independent stages, corresponding to the horizontal and vertical filtering of the blocks within the macroblock. The main contributions of this thesis are: - The use of highly parallel, modular, regular and local architectures to implement dynamically reconfigurable processing IP cores, for data intensive applications with flexibility requirements. - The use of two-dimensional mesh-type arrays as architectural templates to build dynamically reconfigurable IP cores, with a scalable footprint. The proposal consists in generic architectural templates, which can be tuned to solve different computational problems. •A design flow and a tool targeting the design of DPR systems, focused on highly parallel, modular and local architectures. - An inter-module communication strategy, which does not introduce delay or area overhead, named Virtual Borders. - A custom and flexible router to solve the routing conflicts as well as the inter-module communication problems, appearing during the design of DPR systems. - An algorithm addressing the optimization of systems composed of multiple scalable cores, which size can be decided individually, to optimize the system parameters. It is based on a model known as the multi-dimensional multi-choice Knapsack problem. - A reconfiguration engine tailored to the requirements of highly regular and modular architectures. It combines a high reconfiguration throughput with run-time module relocation capabilities, including the support for sub-clock reconfigurable regions and the replication in multiple positions. - A fault injection mechanism which takes advantage of the system reconfiguration engine, as well as the modularity of the proposed reconfigurable architectures, to evaluate the effects of transient and permanent faults in these architectures. - The demonstration of the possibilities of the architectures proposed in this thesis to implement evolvable hardware systems, while keeping a high processing throughput. - The implementation of scalable evolvable hardware systems, which are able to adapt to the fluctuation of the amount of resources available in the system, in an autonomous way. - A parallelization strategy for the H.264/AVC and SVC deblocking filter, which reduces the number of macroblock cycles needed to process the whole frame. - A dynamically scalable architecture that permits the implementation of a novel deblocking filter module, fully compliant with the H.264/AVC and SVC standards, which exploits the macroblock level parallelism of the algorithm. This document is organized in seven chapters. In the first one, an introduction to the technology framework of this thesis, specially focused on dynamic and partial reconfiguration, is provided. The need for the dynamically scalable processing architectures proposed in this work is also motivated in this chapter. In chapter 2, dynamically scalable architectures are described. Description includes most of the architectural contributions of this work. The design flow tailored to the scalable architectures, together with the DREAMs tool provided to implement them, are described in chapter 3. The reconfiguration engine is described in chapter 4. The use of the proposed scalable archtieectures to implement evolvable hardware systems is described in chapter 5, while the scalable deblocking filter is described in chapter 6. Final conclusions of this thesis, and the description of future work, are addressed in chapter 7.

Desarrollo y aplicaciones de radares de alta resolución en bandas milimétricas

Las bandas de las denominadas ondas milimétricas y submilimétricas están situadas en la región del espectro entre las microondas y el infrarrojo. La banda de milimétricas se sitúa entre 30 y 300 GHz, considerada normalmente como la banda EHF (Extremely High Frequency). El margen de frecuencias entre 300 y 3000 GHz es conocido como la banda de ondas submilimétricas o de terahercios (THz). Sin embargo, no toda la comunidad científica está de acuerdo acerca de las frecuencias que limitan la banda de THz. De hecho, 100 GHz y 10 THz son considerados comúnmente como los límites inferior y superior de dicha banda, respectivamente. Hasta hace relativamente pocos años, la banda de THz sólo había sido explotada para aplicaciones en los campos de la espectroscopía y la radioastronomía. Los avances tecnológicos en la electrónica de microondas y la óptica lastraron el desarrollo de la banda de THz. Sin embargo, investigaciones recientes han demostrado las ventajas asociadas a operar en estas longitudes de onda, lo que ha aumentado el interés y los esfuerzos dedicados a la tecnología de THz. A pesar de que han surgido un gran número de aplicaciones, una de las más prometedoras está en el campo de la vigilancia y la seguridad. Esta tesis está dedicada al desarrollo de radares de onda continua y frecuencia modulada (CW-LFM) de alta resolución en la banda de milimétricas, más concretamente, en las ventanas de atenuación situadas en 100 y 300 GHz. Trabajar en estas bandas de frecuencia presenta beneficios tales como la capacidad de las ondas de atravesar ciertos materiales como la ropa o el papel, opacos en el rango visible, y la posibilidad de usar grandes anchos de banda, obteniéndose así elevadas resoluciones en distancia. Los anchos de banda de 9 y 27 GHz seleccionados para los sistemas de 100 y 300 GHz, respectivamente, proporcionan resoluciones en distancia alrededor y por debajo del cm. Por otro lado, las aplicaciones objetivo se centran en la adquisición de imágenes a corto alcance. En el caso del prototipo a 300 GHz, su diseño se ha orientado a aplicaciones de detección a distancia en escenarios de vigilancia y seguridad. La naturaleza no ionizante de esta radiación supone una ventaja frente a las alternativas tradicionalmente usadas tales como los sistemas de rayos X. La presente tesis se centra en el proceso de diseño, implementación y caracterización de ambos sistemas así como de la validación de su funcionamiento. Se ha elegido una solución basada en componentes electrónicos, y no ópticos, debido a su alta fiabilidad, volumen reducido y amplia disponibilidad de componentes comerciales. Durante el proceso de diseño e implementación, se han tenido en cuenta varias directrices tales como la minimización del coste y la versatilidad de los sistemas desarrollados para hacer posible su aplicación para múltiples propósitos. Ambos sistemas se han utilizado en diferentes pruebas experimentales, obteniendo resultados satisfactorios. Aunque son sólo ejemplos dentro del amplio rango de posibles aplicaciones, la adquisición de imágenes ISAR de modelos de blancos a escala para detección automática así como la obtención de datos micro-Range/micro- Doppler para el análisis de patrones humanos han validado el funcionamiento del sistema a 100 GHz. Por otro lado, varios ejemplos de imágenes 3D obtenidas a 300 GHz han demostrado las capacidades del sistema para su uso en tareas de seguridad y detección a distancia. ABSTRACT The millimeter- and submillimeter-wave bands are the regions of the spectrum between the microwaves and the infrared (IR). The millimeter-wave band covers the range of the spectrum from 30 to 300 GHz, which is usually considered as the extremely high frequency (EHF) band. The range of frequencies between 300 and 3000 GHz is known as the submillimeter-wave or terahertz (THz) band. Nevertheless, the boundaries of the THz band are not accepted by the whole research community. In fact, 100 GHz and 10 THz are often considered by some authors as the lower and upper limit of this band, respectively. Until recently, the THz band had not been exploited for practical applications, with the exception of minor uses in the fields of spectroscopy and radio astronomy. The advancements on microwave electronics and optical technology left the well-known THz gap undeveloped. However, recent research has unveiled the advantages of working at these frequencies, which has motivated the increase in research effort devoted to THz technology. Even though the range of upcoming applications is wide, the most promising ones are in the field of security and surveillance. Particularly, this Ph.D. thesis deals with the development of high resolution continuouswave linear-frequency modulated (CW-LFM) radars in the millimeter-wave band, namely, in the attenuation windows located at 100 and 300 GHz. Working at these wavelengths presents several benefits such as the ability of radiation to penetrate certain materials, visibly opaque, and the great availability of bandwidth at these frequencies, which leads to high range resolution. The selected bandwidths of 9 and 27 GHz for these systems at 100 and 300 GHz, respectively, result in cm and sub-cm range resolution. On the other hand, the intended applications are in the field of short-range imaging. In particular, the design of the 300-GHz prototype is oriented to standoff detection for security and surveillance scenarios. The non-ionizing nature of this radiation allows safety concerns to be alleviated, in clear contrast to other traditional alternatives such as X-rays systems. This thesis is focused on the design, implementation and characterization process of both systems as well as the experimental assessment of their performances. An electronic approach has been selected instead of an optical solution so as to take advantage of its high reliability, reduced volume and the availability of commercial components. Through the whole design and implementation process, several guidelines such as low cost and hardware versatility have been also kept in mind. Taking advantage of that versatility, different applications can be carried out with the same hardware concept. Both radar systems have been used in several experimental trials with satisfactory results. Despite being mere examples within the wide range of fields of application, ISAR imaging of scaled model targets for automatic target recognition and micro-Range/micro-Doppler analysis of human patterns have validated the system performance at 100 GHz. In addition, 3D imaging examples at 300 GHz demonstrate the radar system’s capabilities for standoff detection and security tasks.

Use of a scrapped ship as a floating breakwater for shore protection

The purpose of this research is to assess the effectiveness of a ship used as a detached floating breakwater for coastal protection and forming salients of sand or tombolos. Floating breakwaters have been extensively used as port or coastal protection structures and display advantages in terms of construction and ecology, amongst others. However, the greatest problem these structures present is the limited range of wave heights and periods for which they are really effective. Furthermore, ships may be considered as floating structures which, used as breakwaters, would keep the advantages of floating breakwaters and would increase their range of applicability. The possibility of using ships at the conclusion of their useful life for this purpose would also involve greater economic and environmental advantages. Tests were carried out to assess the ship’s effectiveness as a detached floating breakwater using a scaled down physical model to determine the vessel’s transmission coefficient (Kt) as to regular waves with significant periods of 5 sec to 12 sec and significant wave heights of 1.5 m to 4 m at depths from 20 m to 35 m. The ship proves effective for waves up to 4 m significant height and significant periods up to 9 sec. Hanson and Kraus and Pilarzyk’s analytical models, which take transmission coefficients into account, were used to analyse the shore’s response to the breakwater protection. The results obtained show that salients form for waves with periods between 6 sec and 9 sec. It is also concluded that the depths tested are far different from the more usual shallow water involved in constructing detached breakwaters and the shore’s response is therefore scarce.

Diffusion of photovoltaic in Germany: policy vs. consumers

In some countries photovoltaic (PV) technology has already achieved a stage of development at which it can compete with conventional electricity sources. Germany provides a good illustration of this where PV market has reached a mature stage. As a manifest of this, the German government has recently reduced subsidies for households and industry by decreasing the feed in tariff for PV. This development raises fundamental questions: could the PV industry survive? Will consumers be motivated to continue to adopt PV when feed-in tariff diminish? The point of departure for the relevant literature on diffusion of PV has been on the effect of subsidies but little attention has paid to consumer motives when the policy support is scaled down. This paper introduces an in-depth analysis on understanding the consumer motives for adopting photovoltaic applications. Anchored in an extensive exploratory case study on PV consumers and PV system providers, this study aims to provide an encompassing explanation of diffusion of PV by revealing the link between consumer motives and the impact of policy.

A 2D computational parametric analysis of the sheltering effect of fences on a railway vehicle standing on a bridge and experiencing crosswinds

In a crosswind scenario, the risk of high-speed trains overturning increases when they run on viaducts since the aerodynamic loads are higher than on the ground. In order to increase safety, vehicles are sheltered by fences that are installed on the viaduct to reduce the loads experienced by the train. Windbreaks can be designed to have different heights, and with or without eaves on the top. In this paper, a parametric study with a total of 12 fence designs was carried out using a two-dimensional model of a train standing on a viaduct. To asses the relative effectiveness of sheltering devices, tests were done in a wind tunnel with a scaled model at a Reynolds number of 1 × 105, and the train’s aerodynamic coefficients were measured. Experimental results were compared with those predicted by Unsteady Reynolds-averaged Navier-Stokes (URANS) simulations of flow, showing that a computational model is able to satisfactorily predict the trend of the aerodynamic coefficients. In a second set of tests, the Reynolds number was increased to 12 × 106 (at a free flow air velocity of 30 m/s) in order to simulate strong wind conditions. The aerodynamic coefficients showed a similar trend for both Reynolds numbers; however, their numerical value changed enough to indicate that simulations at the lower Reynolds number do not provide all required information. Furthermore, the variation of coefficients in the simulations allowed an explanation of how fences modified the flow around the vehicle to be proposed. This made it clear why increasing fence height reduced all the coefficients but adding an eave had an effect mainly on the lift force coefficient. Finally, by analysing the time signals it was possible to clarify the influence of the Reynolds number on the peak-to-peak amplitude, the time period and the Strouhal number.

Quantitative evaluation of patient-specific conforming hexahedral meshes of abdominal aortic aneurysms and intraluminal thrombus generated from MRI

A novel method for generating patient-specific high quality conforming hexahedral meshes is presented. The meshes are directly obtained from the segmentation of patient magnetic resonance (MR) images of abdominal aortic aneu-rysms (AAA). The MRI permits distinguishing between struc-tures of interest in soft tissue. Being so, the contours of the lumen, the aortic wall and the intraluminal thrombus (ILT) are available and thus the meshes represent the actual anato-my of the patient?s aneurysm, including the layered morpholo-gies of these structures. Most AAAs are located in the lower part of the aorta and the upper section of the iliac arteries, where the inherent tortuosity of the anatomy and the presence of the ILT makes the generation of high-quality elements at the bifurcation is a challenging task. In this work we propose a novel approach for building quadrilateral meshes for each surface of the sectioned geometry, and generating conforming hexahedral meshes by combining the quadrilateral meshes. Conforming hexahedral meshes are created for the wall and the ILT. The resulting elements are evaluated on four patients? datasets using the Scaled Jacobian metric. Hexahedral meshes of 25,000 elements with 94.8% of elements well-suited for FE analysis are generated.