Temperature dependent current-voltage characteristics of zinc oxide nanowire/polypyrrole nanocomposite

Temperature dependent current-voltage (I-V) measurements of electrochemically prepared zinc oxide nanowire/polypyrrole (ZnONW/PPy) nanocomposite yielded non-linear I-V characteristics at temperatures between 300 and 4.5 K. The low-field conductance (G) of the ZnONW/PPy film exhibits pronounced temperature dependence with room temperature conductance (G(300K)) similar to 10(-3) S and a conductance ratio (G(300)K/G(4.5K)) of similar to 10(4), indicating dominance of significant temperature dependent charge transport processes. The conduction mechanism of the film is satisfactorily understood by extended fluctuation induced tunneling (FIT) model as the non-linear I-V characteristics fit fairly well to the extended FIT model. Further, the temperature dependence of G(o) obtained from fitting followed Sheng's model also. (C) 2014 AIP Publishing LLC.

Room Temperature-Processed TiO2 MIM Capacitors for DRAM Applications

We report the room temperature fabrication of Ta/TiO2/Ta metal-insulator-metal (MIM) capacitors (mainly, for DRAM applications). The fabricated devices show high capacitance density (similar to 15 fF/mu m(2)), and low leakage current density of 6.4 X 10(-8) A/cm(2) (27 degrees C) and 3.3 x 10(-6) A/cm(2) (125 degrees C) at -1 V. We analyze the electrical and material characteristics of the fabricated capacitors, and compare the device performance of these capacitors with other TiO2 and TiO2-based MIM capacitors reported in recent literature.

A unique strategy towards high dielectric constant and low loss with multiwall carbon nanotubes anchored onto graphene oxide sheets

Multiwall carbon nanotubes (MWNTs) were anchored onto graphene oxide sheets (GOs) via diazonium and C-C coupling reactions and characterized by spectroscopic and electron microscopic techniques. The thus synthesized MWNT-GO hybrid was then melt mixed with 50/50 polyamide6-maleic anhydride-modified acrylonitrile-butadiene-styrene (PA6-mABS) blend to design materials with high dielectric constant (30) and low dielectric loss. The phase morphology was studied by SEM and it was observed that the MWNT-GO hybrid was selectively localized in the PA6 phase of the blend. The 30 scales with the concentration of MWNT-GO in the blends, which interestingly showed a very low dielectric loss (< 0.2) making them potential candidate for capacitors. In addition, the dynamic storage modulus scales with the fraction of MWNT-GO in the blends, demonstrating their reinforcing capability as well.

Seventeen-Level Inverter Formed by Cascading Flying Capacitor and Floating Capacitor H-Bridges

A multilevel inverter for generating 17 voltage levels using a three-level flying capacitor inverter and cascaded H-bridge modules with floating capacitors has been proposed. Various aspects of the proposed inverter like capacitor voltage balancing have been presented in the present paper. Experimental results are presented to study the performance of the proposed converter. The stability of the capacitor balancing algorithm has been verified both during transients and steady-state operation. All the capacitors in this circuit can be balanced instantaneously by using one of the pole voltage combinations. Another advantage of this topology is its ability to generate all the voltages from a single dc-link power supply which enables back-to-back operation of converter. Also, the proposed inverter can be operated at all load power factors and modulation indices. Additional advantage is, if one of the H-bridges fail, the inverter can still be operated at full load with reduced number of levels. This configuration has very low dv/dt and common-mode voltage variation.

Experimental Investigation on Switching Characteristics of High-Current Insulated Gate Bipolar Transistors at Low Currents

Insulated gate bipolar transistors (IGBTs) are used in high-power voltage-source converters rated up to hundreds of kilowatts or even a few megawatts. Knowledge of device switching characteristics is required for reliable design and operation of the converters. Switching characteristics are studied widely at high current levels, and corresponding data are available in datasheets. But the devices in a converter also switch low currents close to the zero crossings of the line currents. Further, the switching behaviour under these conditions could significantly influence the output waveform quality including zero crossover distortion. Hence, the switching characteristics of high-current IGBTs (300-A and 75-A IGBT modules) at low load current magnitudes are investigated experimentally in this paper. The collector current, gate-emitter voltage and collector-emitter voltage are measured at various low values of current (less than 10% of the device rated current). A specially designed in-house constructed coaxial current transformer (CCT) is used for device current measurement without increasing the loop inductance in the power circuit. Experimental results show that the device voltage rise time increases significantly during turn-off transitions at low currents.

Low-Order Harmonic Suppression for Open-End Winding IM With Dodecagonal Space Vector Using a Single DC-Link Supply

This paper proposes a technique to suppress low-order harmonics for an open-end winding induction motor drive for a full modulation range. One side of the machine is connected to a main inverter with a dc power supply, whereas the other inverter is connected to a capacitor from the other side. Harmonic suppression (with complete elimination of fifth- and seventh-order harmonics) is achieved by realizing dodecagonal space vectors using a combined pulsewidth modulation (PWM) control for the two inverters. The floating capacitor voltage is inherently controlled during the PWM operation. The proposed PWM technique is shown to be valid for the entire modulation range, including overmodulation and six-step mode of operation of the main inverter. Experimental results have been presented to validate the proposed technique.

A low-power, low-cost soil-moisture sensor using dual-probe heat-pulse technique

This paper presents the development and testing of an integrated low-power and low-cost dual-probe heat-pulse (DPHP) soil-moisture sensor in view of the electrical power consumed and affordability in developing countries. A DPHP sensor has two probes: a heater and a temperature sensor probe spaced 3 mm apart from the heater probe. Supply voltage of 3.3V is given to the heater-coil having resistance of 33 Omega power consumption of 330 mW, which is among the lowest in this category of sensors. The heater probe is 40 mm long with 2 mm diameter and hence is stiff enough to be inserted into the soil. The parametric finite element simulation study was performed to ensure that the maximum temperature rise is between 1 degrees C and 5 degrees C for wet and dry soils, respectively. The discrepancy between the simulation and experiment is less than 3.2%. The sensor was validated with white clay and tested with red soil samples to detect volumetric water-content ranging from 0% to 30%. The sensor element is integrated with low-power electronics for amplifying the output from thermocouple sensor and TelosB mote for wireless communication. A 3.7V lithium ion battery with capacity of 1150 mAh is used to power the system. The battery is charged by a 6V and 300 mA solar cell array. Readings were taken in 30 min intervals. The life-time of DPHP sensor node is around 3.6 days. The sensor, encased in 30 mm x 20 mm x 10 mm sized box, and integrated with electronics was tested independently in two separate laboratories for validating as well as investigating the dependence of the measurement of soil-moisture on the density of the soil. The difference in the readings while repeating the experiments was found out to be less than 0.01%. Furthermore, the effect of ambient temperature on the measurement of soil-moisture is studied experimentally and computationally. (C) 2015 Elsevier B.V. All rights reserved.

Transport properties of solution processed Cu2SnS3/AZnO heterostructure for low cost photovoltaics

Cu2SnS3 thin films were deposited by a facile sot-gel technique followed by annealing. The annealed films were structurally characterized by grazing incidence X-ray diffraction (GIXRD) and transmission electron microscopy (TEM). The crystal structure was found to be tetragonal with crystallite sizes of 2.4-3 nm. Texture coefficient calculations from the GIXRD revealed the preferential orientation of the film along the (112) plane. The morphological investigations of the films were carried out using field emission scanning electron microscopy (FESEM) and the composition using electron dispersive spectroscopy (EDS). The temperature dependent current, voltage characteristics of the Cu2SnS3/AZnO heterostructure were studied. The log I-log V plot exhibited three regions of different slopes showing linear ohmic behavior and non-linear behavior following the power law. The temperature dependent current voltage characteristics revealed the variation in ideality factor and barrier height with temperature. The Richardson constant was calculated and its deviation from the theoretical value revealed the inhomogeneity of the barrier heights. Transport characteristics were modeled using the thermionic emission model. The Gaussian distribution of barrier heights was applied and from the modified Richardson plot the value of the Richardson constant was found to be 47.18 A cm(-2) K-2. (c) 2015 Elsevier B.V. All rights reserved.

DLTS analysis of amphoteric interface defects in high-TiO2 MOS structures prepared by sol-gel spin-coating

High-kappa TiO2 thin films have been fabricated from a facile, combined sol-gel spin - coating technique on p and n type silicon substrate. XRD and Raman studies headed the existence of anatase phase of TiO2 with a small grain size of 18 nm. The refractive index `n' quantified from ellipsometry is 2.41. AFM studies suggest a high quality, pore free films with a fairly small surface roughness of 6 angstrom. The presence of Ti in its tetravalent state is confirmed by XPS analysis. The defect parameters observed at the interface of Si/TiO2 were studied by capacitance - voltage (C - V) and deep level transient spectroscopy (DLTS). The flat - band voltage (V-FB) and the density of slow interface states estimated are -0.9, -0.44 V and 5.24x10(10), 1.03x10(11) cm(-2); for the NMOS and PMOS capacitors, respectively. The activation energies, interface state densities and capture cross -sections measured by DLTS are E-V + 0.30, E-C - 0.21 eV; 8.73x10(11), 6.41x10(11) eV(-1) cm(-2) and 5.8x10(-23), 8.11x10(-23) cm(2) for the NMOS and PMOS structures, respectively. A low value of interface state density in both P-and N-MOS structures makes it a suitable alternate dielectric layer for CMOS applications. And also very low value of capture cross section for both the carriers due to the amphoteric nature of defect indicates that the traps are not aggressive recombination centers and possibly can not contribute to the device operation to a large extent. (C) 2015 Author(s).

Measuring the magnetic-field-dependent chemical potential of a low-density three-dimensional electron gas in n-GaAs and extracting its magnetic susceptibility

We report the magnetic-field-dependent shift of the electron chemical potential in bulk, n-type GaAs at room temperature. A transient voltage of similar to 100 mu V was measured across a Au-Al2O3-GaAs metal-oxide-semiconductor capacitor in a pulsed magnetic field of similar to 6 T. Several spurious voltages larger than the signal that had plagued earlier researchers performing similar experiments were carefully eliminated. The itinerant magnetic susceptibility of GaAs is extracted from the experimentally measured data for four different doping densities, including one as low as 5 x 10(15) cm(-3). Though the susceptibility in GaAs is dominated by Landau-Peierls diamagnetism, the experimental technique demonstrated can be a powerful tool for extracting the total free carrier magnetization of any electron system. The method is also virtually independent of the carrier concentration and is expected to work better in the nondegenerate limit. Such experiments had been successfully performed in two-dimensional electron gases at cryogenic temperatures. However, an unambiguous report on having observed this effect in any three-dimensional electron gas has been lacking. We highlight the 50 year old literature of various trials and discuss the key details of our experiment that were essential for its success. The technique can be used to unambiguously yield only the itinerant part of the magnetic susceptibility of complex materials such as magnetic semiconductors and hexaborides, and thus shed light on the origin of ferromagnetism in such systems.

Ionothermal Synthesis of High-Voltage Alluaudite Na2+2xFe2-x(SO4)(3) Sodium Insertion Compound: Structural, Electronic, and Magnetic Insights

Exploring future cathode materials for sodium-ion batteries, alluaudite class of Na2Fe2II(SO4)(3) has been recently unveiled as a 3.8 V positive insertion candidate (Barpanda et al. Nat. Commun. 2014, 5, 4358). It forms an Fe-based polyanionic compound delivering the highest Fe-redox potential along with excellent rate kinetics and reversibility. However, like all known SO4-based insertion materials, its synthesis is cumbersome that warrants careful processing avoiding any aqueous exposure. Here, an alternate low temperature ionothermal synthesis has been described to produce the alluaudite Na2+2xFe2-xII(SO4)(3). It marks the first demonstration of solvothermal synthesis of alluaudite Na2+2xM2-xII(SO4)(3) (M = 3d metals) family of cathodes. Unlike classical solid-state route, this solvothermal route favors sustainable synthesis of homogeneous nanostructured alluaudite products at only 300 degrees C, the lowest temperature value until date. The current work reports the synthetic aspects of pristine and modified ionothermal synthesis of Na2+2xFe2-xII(SO4)(3) having tunable size (300 nm similar to 5 mu m) and morphology. It shows antiferromagnetic ordering below 12 K. A reversible capacity in excess of 80 mAh/g was obtained with good rate kinetics and cycling stability over 50 cycles. Using a synergistic approach combining experimental and ab initio DFT analysis, the structural, magnetic, electronic, and electrochemical properties and the structural limitation to extract full capacity have been described.

Na2M2(SO4)(3) (M = Fe, Mn, Co and Ni): towards high-voltage sodium battery applications

Sodium-ion-based batteries have evolved as excellent alternatives to their lithium-ion-based counterparts due to the abundance, uniform geographical distribution and low price of Na resources. In the pursuit of sodium chemistry, recently the alluaudite framework Na2M2(SO4)(3) has been unveiled as a high-voltage sodium insertion system. In this context, the framework of density functional theory has been applied to systematically investigate the crystal structure evolution, density of states and charge transfer with sodium ions insertion, and the corresponding average redox potential, for Na2M2(SO4)(3) (M = Fe, Mn, Co and Ni). It is shown that full removal of sodium atoms from the Fe-based device is not a favorable process due to the 8% volume shrinkage. The imaginary frequencies obtained in the phonon dispersion also reflect this instability and the possible phase transition. This high volume change has not been observed in the cases of the Co- and Ni-based compounds. This is because the redox reaction assumes a different mechanism for each of the compounds investigated. For the polyanion with Fe, the removal of sodium ions induces a charge reorganization at the Fe centers. For the Mn case, the redox process induces a charge reorganization of the Mn centers with a small participation of the oxygen atoms. The Co and Ni compounds present a distinct trend with the redox reaction occurring with a strong participation of the oxygen sublattice, resulting in a very small volume change upon desodiation. Moreover, the average deintercalation potential for each of the compounds has been computed. The implications of our findings have been discussed both from the scientific perspective and in terms of technological aspects.

Low temperature solution processed high-kappa ZrO2 gate dielectrics for nanoelectonics

The high-kappa gate dielectrics, specifically amorphous films offer salient features such as exceptional mechanical flexibility, smooth surfaces and better uniformity associated with low leakage current density. In this work, similar to 35 nm thick amorphous ZrO2 films were deposited on silicon substrate at low temperature (300 degrees C, 1 h) from facile spin-coating method and characterized by various analytical techniques. The X-ray diffraction and X-ray photoelectron spectroscopy reveal the formation of amorphous phase ZrO2, while ellipsometry analysis together with the Atomic Force Microscope suggest the formation of dense film with surface roughness of 1.5 angstrom, respectively. The fabricated films were integrated in metal-oxide-semiconductor (MOS) structures to check the electrical capabilities. The oxide capacitance (C-ox), flat band capacitance (C-FB), flat band voltage (V-FB), dielectric constant (kappa) and oxide trapped charges (Q(ot)) extracted from high frequency (1 MHz) C-V curve are 186 pF, 104 pF, 0.37V, 15 and 2 x 10(-11) C, respectively. The small flat band voltage 0.37V, narrow hysteresis and very little frequency dispersion between 10 kHz-1 MHz suggest an excellent a-ZrO2/Si interface with very less trapped charges in the oxide. The films exhibit a low leakage current density 4.7 x 10(-9)A/cm(2) at 1V. In addition, the charge transport mechanism across the MOSC is analyzed and found to have a strong bias dependence. The space charge limited conduction mechanism is dominant in the high electric field region (1.3-5 V) due to the presence of traps, while the trap-supported tunneling is prevailed in the intermediate region (0.35-1.3 V). Low temperature solution processed ZrO2 thin films obtained are of high quality and find their importance as a potential dielectric layer on Si and polymer based flexible electronics. (C) 2016 Published by Elsevier B.V.

Partial soi power LDMOS with a variable low-kappa; Dielectric buried layer and a buried P layer

A power LDMOS on partial silicon on insulator (PSOI) with a variable low-κ dielectric (VLKD) buried layer and a buried p (BP) layer is proposed (VLKD BPSOI). At a low κ value, the electric field strength in the buried dielectric (EI) is enhanced, and a Si window makes the substrate share the vertical voltage drop, leading to a high vertical breakdown voltage (BV). Moreover, three interface field peaks are introduced by the BP, the Si window, and the VLKD, which modulate the fields in the SOI layer, the VLKD layer, and the substrate; consequently, a high BV is obtained. Furthermore, the BP reduces the specific on-resistance (Ron), and the Si window alleviates the self-heating effect (SHE). The BV for VLKD BPSOI is enhanced by 34.5%, and Ron is decreased by 26.6%, compared with those for the conventional PSOI, and VLKD BPSOI also maintains a low SHE. © 2006 IEEE.

High tuning range AlSi RF MEMS capacitors fabricated with sacrificial amorphous silicon surface micromachining

This paper reports the fabrication and electrical characterization of high tuning range AlSi RF MEMS capacitors. We present experimental results obtained by a surface micromachining process that uses dry etching of sacrificial amorphous silicon to release Al-1%Si membranes and has a low thermal budget (<450 °C) being compatible with CMOS post-processing. The proposed silicon sacrificial layer dry etching (SSLDE) process is able to provide very high Si etch rates (3-15 μm/min, depending on process parameters) with high Si: SiO2 selectivity (>10,000:1). Single- and double-air-gap MEMS capacitors, as well as some dedicated test structures needed to calibrate the electro-mechanical parameters and explore the reliability of the proposed technology, have been fabricated with the new process. S-parameter measurements from 100 MHz up to 2 GHz have shown a capacitance tuning range higher than 100% with the double-air-gap architecture. The tuning range can be enlarged with a proper DC electrical bias of the capacitor electrodes. Finally, the reported results make the proposed MEMS tuneable capacitor a good candidate for above-IC integration in communications applications. © 2004 Elsevier B.V. All rights reserved.