Atlas-free Brain Tissue Segmentation Using a Single T1-weighted MRI Acquisition

Many studies investigating the aging brain or disease-induced brain alterations rely on accurate and reproducible brain tissue segmentation. Being a preliminary processing step prior to the segmentation, reliableskull-stripping the removal ofnon-brain tissue is also crucial for all later image assessment. Typically, segmentation algorithms rely on an atlas i.e. pre-segmented template data. Brain morphology, however, differs considerably depending on age, sex and race. In addition, diseased brains may deviate significantly from the atlas information typically gained from healthy volunteers. The imposed prior atlas information can thus lead to degradation of segmentation results. The recently introduced MP2RAGE sequence provides a bias-free T1 contrast with heavily reduced T2*- and PD-weighting compared to the standard MP-RAGE [1]. To this end, it acquires two image volumes at different inversion times in one acquisition, combining them to a uniform, i.e. homogenous image. In this work, we exploit the advantageous contrast properties of the MP2RAGE and combine it with a Dixon (i.e. fat-water separation) approach. The information gained by the additional fat image of the head considerably improves the skull-stripping outcome [2]. In conjunction with the pure T1 contrast of the MP2RAGE uniform image, we achieve robust skull-stripping and brain tissue segmentation without the use of an atlas

Dynamic Response Optimization of Vehicles through Efficient Multibody Formulations and Automatic Differentiation Techniques

El diseño y desarrollo de sistemas de suspensión para vehículos se basa cada día más en el diseño por ordenador y en herramientas de análisis por ordenador, las cuales permiten anticipar problemas y resolverlos por adelantado. El comportamiento y las características dinámicas se calculan con precisión, bajo coste, y recursos y tiempos de cálculo reducidos. Sin embargo, existe una componente iterativa en el proceso, que requiere la definición manual de diseños a través de técnicas “prueba y error”. Esta Tesis da un paso hacia el desarrollo de un entorno de simulación eficiente capaz de simular, analizar y evaluar diseños de suspensiones vehiculares, y de mejorarlos hacia la solución optima mediante la modificación de los parámetros de diseño. La modelización mediante sistemas multicuerpo se utiliza aquí para desarrollar un modelo de autocar con 18 grados de libertad, de manera detallada y eficiente. La geometría y demás características de la suspensión se ajustan a las del vehículo real, así como los demás parámetros del modelo. Para simular la dinámica vehicular, se utiliza una formulación multicuerpo moderna y eficiente basada en las ecuaciones de Maggi, a la que se ha incorporado un visor 3D. Así, se consigue simular maniobras vehiculares en tiempos inferiores al tiempo real. Una vez que la dinámica está disponible, los análisis de sensibilidad son cruciales para una optimización robusta y eficiente. Para ello, se presenta una técnica matemática que permite derivar las variables dinámicas dentro de la formulación, de forma algorítmica, general, con la precisión de la maquina, y razonablemente eficiente: la diferenciación automática. Este método propaga las derivadas con respecto a las variables de diseño a través del código informático y con poca intervención del usuario. En contraste con otros enfoques en la bibliografía, generalmente particulares y limitados, se realiza una comparación de librerías, se desarrolla una formulación híbrida directa-automática para el cálculo de sensibilidades, y se presentan varios ejemplos reales. Finalmente, se lleva a cabo la optimización de la respuesta dinámica del vehículo citado. Se analizan cuatro tipos distintos de optimización: identificación de parámetros, optimización de la maniobrabilidad, optimización del confort y optimización multi-objetivo, todos ellos aplicados al diseño del autocar. Además de resultados analíticos y gráficos, se incluyen algunas consideraciones acerca de la eficiencia. En resumen, se mejora el comportamiento dinámico de vehículos por medio de modelos multicuerpo y de técnicas de diferenciación automática y optimización avanzadas, posibilitando un ajuste automático, preciso y eficiente de los parámetros de diseño. ABSTRACT Each day, the design and development of vehicle suspension systems relies more on computer-aided design and computer-aided engineering tools, which allow anticipating the problems and solving them ahead of time. Dynamic behavior and characteristics are thus simulated accurately and inexpensively with moderate computational times and resources. There is, however, an iterative component in the process, which involves the manual definition of designs in a trialand-error manner. This Thesis takes a step towards the development of an efficient simulation framework capable of simulating, analyzing and evaluating vehicle suspension designs, and automatically improving them by varying the design parameters towards the optimal solution. The multibody systems approach is hereby used to model a three-dimensional 18-degrees-of-freedom coach in a comprehensive yet efficient way. The suspension geometry and characteristics resemble the ones from the real vehicle, as do the rest of vehicle parameters. In order to simulate vehicle dynamics, an efficient, state-of-the-art multibody formulation based on Maggi’s equations is employed, and a three-dimensional graphics viewer is developed. As a result, vehicle maneuvers can be simulated faster than real-time. Once the dynamics are ready, a sensitivity analysis is crucial for a robust optimization. To that end, a mathematical technique is introduced, which allows differentiating the dynamic variables within the multibody formulation in a general, algorithmic, accurate to machine precision, and reasonably efficient way: automatic differentiation. This method propagates the derivatives with respect to the design parameters throughout the computer code, with little user interaction. In contrast with other attempts in the literature, mostly not generalpurpose, a benchmarking of libraries is carried out, a hybrid direct-automatic differentiation approach for the computation of sensitivities is developed, and several real-life examples are analyzed. Finally, a design optimization process of the aforementioned vehicle is carried out. Four different types of dynamic response optimization are presented: parameter identification, handling optimization, ride comfort optimization and multi-objective optimization; all of which are applied to the design of the coach example. Together with analytical and visual proof of the results, efficiency considerations are made. In summary, the dynamic behavior of vehicles is improved by using the multibody systems approach, along with advanced differentiation and optimization techniques, enabling an automatic, accurate and efficient tuning of design parameters.

Mealiness assessment in fruits using MRI techniques.

Mealiness is a sensory attribute that cannot be defined by a single parameter but through a combination of variables (multidimensional structure). Previous studies propose the definition of mealiness as the lack of crispiness, of hardness and of juiciness. Current aims are focused on establishing non destructive tests for mealiness assessment. MultiSliceMultiEcho Magnetic resonance images (MRI, 64*64pixels) have been taken corresponding to a 3ms of Echo time. Small samples of Top Red apples stored 6 months at controlled atmosphere (expected to be non mealy) and 2°C (expected to be mealy) have been used for MRI imaging. Three out of four apples corresponding to the sample maintained at controlled atmosphere did not develop mealiness while three out of four fruits corresponding to the sample stored at 2°C became mealy after 6 month of storage. The minimum T2 values/image obtained for the mealy apples shows to be significantly lower when compared with non mealy apples pointing that a more dis-aggregated structure leads to a quicker loss of signal Also, there is a significant linear correlation (r=-0.76) between the number of pixels with a T2 value below 35ms within a fruit image and the deformation parameter registered during the Magness-Taylor firmness test. Finally, all the T2 images of the mealy apples show a regional variation of contrast which is not shown for non mealy apples. This variation of contrast is similar to the MRI images of water-cored apples indicating that in these cases there is a differential water movement that may precede the internal browning.

Side-Channel Attack Protection Techniques in FPGA Systems using Enhanced Dual-Rail Solutions

Esta tesis doctoral se centra principalmente en técnicas de ataque y contramedidas relacionadas con ataques de canal lateral (SCA por sus siglas en inglés), que han sido propuestas dentro del campo de investigación académica desde hace 17 años. Las investigaciones relacionadas han experimentado un notable crecimiento en las últimas décadas, mientras que los diseños enfocados en la protección sólida y eficaz contra dichos ataques aún se mantienen como un tema de investigación abierto, en el que se necesitan iniciativas más confiables para la protección de la información persona de empresa y de datos nacionales. El primer uso documentado de codificación secreta se remonta a alrededor de 1700 B.C., cuando los jeroglíficos del antiguo Egipto eran descritos en las inscripciones. La seguridad de la información siempre ha supuesto un factor clave en la transmisión de datos relacionados con inteligencia diplomática o militar. Debido a la evolución rápida de las técnicas modernas de comunicación, soluciones de cifrado se incorporaron por primera vez para garantizar la seguridad, integridad y confidencialidad de los contextos de transmisión a través de cables sin seguridad o medios inalámbricos. Debido a las restricciones de potencia de cálculo antes de la era del ordenador, la técnica de cifrado simple era un método más que suficiente para ocultar la información. Sin embargo, algunas vulnerabilidades algorítmicas pueden ser explotadas para restaurar la regla de codificación sin mucho esfuerzo. Esto ha motivado nuevas investigaciones en el área de la criptografía, con el fin de proteger el sistema de información ante sofisticados algoritmos. Con la invención de los ordenadores se ha acelerado en gran medida la implementación de criptografía segura, que ofrece resistencia eficiente encaminada a obtener mayores capacidades de computación altamente reforzadas. Igualmente, sofisticados cripto-análisis han impulsado las tecnologías de computación. Hoy en día, el mundo de la información ha estado involucrado con el campo de la criptografía, enfocada a proteger cualquier campo a través de diversas soluciones de cifrado. Estos enfoques se han fortalecido debido a la unificación optimizada de teorías matemáticas modernas y prácticas eficaces de hardware, siendo posible su implementación en varias plataformas (microprocesador, ASIC, FPGA, etc.). Las necesidades y requisitos de seguridad en la industria son las principales métricas de conducción en el diseño electrónico, con el objetivo de promover la fabricación de productos de gran alcance sin sacrificar la seguridad de los clientes. Sin embargo, una vulnerabilidad en la implementación práctica encontrada por el Prof. Paul Kocher, et al en 1996 implica que un circuito digital es inherentemente vulnerable a un ataque no convencional, lo cual fue nombrado posteriormente como ataque de canal lateral, debido a su fuente de análisis. Sin embargo, algunas críticas sobre los algoritmos criptográficos teóricamente seguros surgieron casi inmediatamente después de este descubrimiento. En este sentido, los circuitos digitales consisten típicamente en un gran número de celdas lógicas fundamentales (como MOS - Metal Oxide Semiconductor), construido sobre un sustrato de silicio durante la fabricación. La lógica de los circuitos se realiza en función de las innumerables conmutaciones de estas células. Este mecanismo provoca inevitablemente cierta emanación física especial que puede ser medida y correlacionada con el comportamiento interno del circuito. SCA se puede utilizar para revelar datos confidenciales (por ejemplo, la criptografía de claves), analizar la arquitectura lógica, el tiempo e incluso inyectar fallos malintencionados a los circuitos que se implementan en sistemas embebidos, como FPGAs, ASICs, o tarjetas inteligentes. Mediante el uso de la comparación de correlación entre la cantidad de fuga estimada y las fugas medidas de forma real, información confidencial puede ser reconstruida en mucho menos tiempo y computación. Para ser precisos, SCA básicamente cubre una amplia gama de tipos de ataques, como los análisis de consumo de energía y radiación ElectroMagnética (EM). Ambos se basan en análisis estadístico y, por lo tanto, requieren numerosas muestras. Los algoritmos de cifrado no están intrínsecamente preparados para ser resistentes ante SCA. Es por ello que se hace necesario durante la implementación de circuitos integrar medidas que permitan camuflar las fugas a través de "canales laterales". Las medidas contra SCA están evolucionando junto con el desarrollo de nuevas técnicas de ataque, así como la continua mejora de los dispositivos electrónicos. Las características físicas requieren contramedidas sobre la capa física, que generalmente se pueden clasificar en soluciones intrínsecas y extrínsecas. Contramedidas extrínsecas se ejecutan para confundir la fuente de ataque mediante la integración de ruido o mala alineación de la actividad interna. Comparativamente, las contramedidas intrínsecas están integradas en el propio algoritmo, para modificar la aplicación con el fin de minimizar las fugas medibles, o incluso hacer que dichas fugas no puedan ser medibles. Ocultación y Enmascaramiento son dos técnicas típicas incluidas en esta categoría. Concretamente, el enmascaramiento se aplica a nivel algorítmico, para alterar los datos intermedios sensibles con una máscara de manera reversible. A diferencia del enmascaramiento lineal, las operaciones no lineales que ampliamente existen en criptografías modernas son difíciles de enmascarar. Dicho método de ocultación, que ha sido verificado como una solución efectiva, comprende principalmente la codificación en doble carril, que está ideado especialmente para aplanar o eliminar la fuga dependiente de dato en potencia o en EM. En esta tesis doctoral, además de la descripción de las metodologías de ataque, se han dedicado grandes esfuerzos sobre la estructura del prototipo de la lógica propuesta, con el fin de realizar investigaciones enfocadas a la seguridad sobre contramedidas de arquitectura a nivel lógico. Una característica de SCA reside en el formato de las fuentes de fugas. Un típico ataque de canal lateral se refiere al análisis basado en la potencia, donde la capacidad fundamental del transistor MOS y otras capacidades parásitas son las fuentes esenciales de fugas. Por lo tanto, una lógica robusta resistente a SCA debe eliminar o mitigar las fugas de estas micro-unidades, como las puertas lógicas básicas, los puertos I/O y las rutas. Las herramientas EDA proporcionadas por los vendedores manipulan la lógica desde un nivel más alto, en lugar de realizarlo desde el nivel de puerta, donde las fugas de canal lateral se manifiestan. Por lo tanto, las implementaciones clásicas apenas satisfacen estas necesidades e inevitablemente atrofian el prototipo. Por todo ello, la implementación de un esquema de diseño personalizado y flexible ha de ser tomado en cuenta. En esta tesis se presenta el diseño y la implementación de una lógica innovadora para contrarrestar SCA, en la que se abordan 3 aspectos fundamentales: I. Se basa en ocultar la estrategia sobre el circuito en doble carril a nivel de puerta para obtener dinámicamente el equilibrio de las fugas en las capas inferiores; II. Esta lógica explota las características de la arquitectura de las FPGAs, para reducir al mínimo el gasto de recursos en la implementación; III. Se apoya en un conjunto de herramientas asistentes personalizadas, incorporadas al flujo genérico de diseño sobre FPGAs, con el fin de manipular los circuitos de forma automática. El kit de herramientas de diseño automático es compatible con la lógica de doble carril propuesta, para facilitar la aplicación práctica sobre la familia de FPGA del fabricante Xilinx. En este sentido, la metodología y las herramientas son flexibles para ser extendido a una amplia gama de aplicaciones en las que se desean obtener restricciones mucho más rígidas y sofisticadas a nivel de puerta o rutado. En esta tesis se realiza un gran esfuerzo para facilitar el proceso de implementación y reparación de lógica de doble carril genérica. La viabilidad de las soluciones propuestas es validada mediante la selección de algoritmos criptográficos ampliamente utilizados, y su evaluación exhaustiva en comparación con soluciones anteriores. Todas las propuestas están respaldadas eficazmente a través de ataques experimentales con el fin de validar las ventajas de seguridad del sistema. El presente trabajo de investigación tiene la intención de cerrar la brecha entre las barreras de implementación y la aplicación efectiva de lógica de doble carril. En esencia, a lo largo de esta tesis se describirá un conjunto de herramientas de implementación para FPGAs que se han desarrollado para trabajar junto con el flujo de diseño genérico de las mismas, con el fin de lograr crear de forma innovadora la lógica de doble carril. Un nuevo enfoque en el ámbito de la seguridad en el cifrado se propone para obtener personalización, automatización y flexibilidad en el prototipo de circuito de bajo nivel con granularidad fina. Las principales contribuciones del presente trabajo de investigación se resumen brevemente a continuación: Lógica de Precharge Absorbed-DPL logic: El uso de la conversión de netlist para reservar LUTs libres para ejecutar la señal de precharge y Ex en una lógica DPL. Posicionamiento entrelazado Row-crossed con pares idénticos de rutado en redes de doble carril, lo que ayuda a aumentar la resistencia frente a la medición EM selectiva y mitigar los impactos de las variaciones de proceso. Ejecución personalizada y herramientas de conversión automática para la generación de redes idénticas para la lógica de doble carril propuesta. (a) Para detectar y reparar conflictos en las conexiones; (b) Detectar y reparar las rutas asimétricas. (c) Para ser utilizado en otras lógicas donde se requiere un control estricto de las interconexiones en aplicaciones basadas en Xilinx. Plataforma CPA de pruebas personalizadas para el análisis de EM y potencia, incluyendo la construcción de dicha plataforma, el método de medición y análisis de los ataques. Análisis de tiempos para cuantificar los niveles de seguridad. División de Seguridad en la conversión parcial de un sistema de cifrado complejo para reducir los costes de la protección. Prueba de concepto de un sistema de calefacción auto-adaptativo para mitigar los impactos eléctricos debido a la variación del proceso de silicio de manera dinámica. La presente tesis doctoral se encuentra organizada tal y como se detalla a continuación: En el capítulo 1 se abordan los fundamentos de los ataques de canal lateral, que abarca desde conceptos básicos de teoría de modelos de análisis, además de la implementación de la plataforma y la ejecución de los ataques. En el capítulo 2 se incluyen las estrategias de resistencia SCA contra los ataques de potencia diferencial y de EM. Además de ello, en este capítulo se propone una lógica en doble carril compacta y segura como contribución de gran relevancia, así como también se presentará la transformación lógica basada en un diseño a nivel de puerta. Por otra parte, en el Capítulo 3 se abordan los desafíos relacionados con la implementación de lógica en doble carril genérica. Así mismo, se describirá un flujo de diseño personalizado para resolver los problemas de aplicación junto con una herramienta de desarrollo automático de aplicaciones propuesta, para mitigar las barreras de diseño y facilitar los procesos. En el capítulo 4 se describe de forma detallada la elaboración e implementación de las herramientas propuestas. Por otra parte, la verificación y validaciones de seguridad de la lógica propuesta, así como un sofisticado experimento de verificación de la seguridad del rutado, se describen en el capítulo 5. Por último, un resumen de las conclusiones de la tesis y las perspectivas como líneas futuras se incluyen en el capítulo 6. Con el fin de profundizar en el contenido de la tesis doctoral, cada capítulo se describe de forma más detallada a continuación: En el capítulo 1 se introduce plataforma de implementación hardware además las teorías básicas de ataque de canal lateral, y contiene principalmente: (a) La arquitectura genérica y las características de la FPGA a utilizar, en particular la Xilinx Virtex-5; (b) El algoritmo de cifrado seleccionado (un módulo comercial Advanced Encryption Standard (AES)); (c) Los elementos esenciales de los métodos de canal lateral, que permiten revelar las fugas de disipación correlacionadas con los comportamientos internos; y el método para recuperar esta relación entre las fluctuaciones físicas en los rastros de canal lateral y los datos internos procesados; (d) Las configuraciones de las plataformas de pruebas de potencia / EM abarcadas dentro de la presente tesis. El contenido de esta tesis se amplia y profundiza a partir del capítulo 2, en el cual se abordan varios aspectos claves. En primer lugar, el principio de protección de la compensación dinámica de la lógica genérica de precarga de doble carril (Dual-rail Precharge Logic-DPL) se explica mediante la descripción de los elementos compensados a nivel de puerta. En segundo lugar, la lógica PA-DPL es propuesta como aportación original, detallando el protocolo de la lógica y un caso de aplicación. En tercer lugar, dos flujos de diseño personalizados se muestran para realizar la conversión de doble carril. Junto con ello, se aclaran las definiciones técnicas relacionadas con la manipulación por encima de la netlist a nivel de LUT. Finalmente, una breve discusión sobre el proceso global se aborda en la parte final del capítulo. El Capítulo 3 estudia los principales retos durante la implementación de DPLs en FPGAs. El nivel de seguridad de las soluciones de resistencia a SCA encontradas en el estado del arte se ha degenerado debido a las barreras de implantación a través de herramientas EDA convencionales. En el escenario de la arquitectura FPGA estudiada, se discuten los problemas de los formatos de doble carril, impactos parásitos, sesgo tecnológico y la viabilidad de implementación. De acuerdo con estas elaboraciones, se plantean dos problemas: Cómo implementar la lógica propuesta sin penalizar los niveles de seguridad, y cómo manipular un gran número de celdas y automatizar el proceso. El PA-DPL propuesto en el capítulo 2 se valida con una serie de iniciativas, desde características estructurales como doble carril entrelazado o redes de rutado clonadas, hasta los métodos de aplicación tales como las herramientas de personalización y automatización de EDA. Por otra parte, un sistema de calefacción auto-adaptativo es representado y aplicado a una lógica de doble núcleo, con el fin de ajustar alternativamente la temperatura local para equilibrar los impactos negativos de la variación del proceso durante la operación en tiempo real. El capítulo 4 se centra en los detalles de la implementación del kit de herramientas. Desarrollado sobre una API third-party, el kit de herramientas personalizado es capaz de manipular los elementos de la lógica de circuito post P&R ncd (una versión binaria ilegible del xdl) convertido al formato XDL Xilinx. El mecanismo y razón de ser del conjunto de instrumentos propuestos son cuidadosamente descritos, que cubre la detección de enrutamiento y los enfoques para la reparación. El conjunto de herramientas desarrollado tiene como objetivo lograr redes de enrutamiento estrictamente idénticos para la lógica de doble carril, tanto para posicionamiento separado como para el entrelazado. Este capítulo particularmente especifica las bases técnicas para apoyar las implementaciones en los dispositivos de Xilinx y su flexibilidad para ser utilizado sobre otras aplicaciones. El capítulo 5 se enfoca en la aplicación de los casos de estudio para la validación de los grados de seguridad de la lógica propuesta. Se discuten los problemas técnicos detallados durante la ejecución y algunas nuevas técnicas de implementación. (a) Se discute el impacto en el proceso de posicionamiento de la lógica utilizando el kit de herramientas propuesto. Diferentes esquemas de implementación, tomando en cuenta la optimización global en seguridad y coste, se verifican con los experimentos con el fin de encontrar los planes de posicionamiento y reparación optimizados; (b) las validaciones de seguridad se realizan con los métodos de correlación y análisis de tiempo; (c) Una táctica asintótica se aplica a un núcleo AES sobre BCDL estructurado para validar de forma sofisticada el impacto de enrutamiento sobre métricas de seguridad; (d) Los resultados preliminares utilizando el sistema de calefacción auto-adaptativa sobre la variación del proceso son mostrados; (e) Se introduce una aplicación práctica de las herramientas para un diseño de cifrado completa. Capítulo 6 incluye el resumen general del trabajo presentado dentro de esta tesis doctoral. Por último, una breve perspectiva del trabajo futuro se expone, lo que puede ampliar el potencial de utilización de las contribuciones de esta tesis a un alcance más allá de los dominios de la criptografía en FPGAs. ABSTRACT This PhD thesis mainly concentrates on countermeasure techniques related to the Side Channel Attack (SCA), which has been put forward to academic exploitations since 17 years ago. The related research has seen a remarkable growth in the past decades, while the design of solid and efficient protection still curiously remain as an open research topic where more reliable initiatives are required for personal information privacy, enterprise and national data protections. The earliest documented usage of secret code can be traced back to around 1700 B.C., when the hieroglyphs in ancient Egypt are scribed in inscriptions. Information security always gained serious attention from diplomatic or military intelligence transmission. Due to the rapid evolvement of modern communication technique, crypto solution was first incorporated by electronic signal to ensure the confidentiality, integrity, availability, authenticity and non-repudiation of the transmitted contexts over unsecure cable or wireless channels. Restricted to the computation power before computer era, simple encryption tricks were practically sufficient to conceal information. However, algorithmic vulnerabilities can be excavated to restore the encoding rules with affordable efforts. This fact motivated the development of modern cryptography, aiming at guarding information system by complex and advanced algorithms. The appearance of computers has greatly pushed forward the invention of robust cryptographies, which efficiently offers resistance relying on highly strengthened computing capabilities. Likewise, advanced cryptanalysis has greatly driven the computing technologies in turn. Nowadays, the information world has been involved into a crypto world, protecting any fields by pervasive crypto solutions. These approaches are strong because of the optimized mergence between modern mathematical theories and effective hardware practices, being capable of implement crypto theories into various platforms (microprocessor, ASIC, FPGA, etc). Security needs from industries are actually the major driving metrics in electronic design, aiming at promoting the construction of systems with high performance without sacrificing security. Yet a vulnerability in practical implementation found by Prof. Paul Kocher, et al in 1996 implies that modern digital circuits are inherently vulnerable to an unconventional attack approach, which was named as side-channel attack since then from its analysis source. Critical suspicions to theoretically sound modern crypto algorithms surfaced almost immediately after this discovery. To be specifically, digital circuits typically consist of a great number of essential logic elements (as MOS - Metal Oxide Semiconductor), built upon a silicon substrate during the fabrication. Circuit logic is realized relying on the countless switch actions of these cells. This mechanism inevitably results in featured physical emanation that can be properly measured and correlated with internal circuit behaviors. SCAs can be used to reveal the confidential data (e.g. crypto-key), analyze the logic architecture, timing and even inject malicious faults to the circuits that are implemented in hardware system, like FPGA, ASIC, smart Card. Using various comparison solutions between the predicted leakage quantity and the measured leakage, secrets can be reconstructed at much less expense of time and computation. To be precisely, SCA basically encloses a wide range of attack types, typically as the analyses of power consumption or electromagnetic (EM) radiation. Both of them rely on statistical analyses, and hence require a number of samples. The crypto algorithms are not intrinsically fortified with SCA-resistance. Because of the severity, much attention has to be taken into the implementation so as to assemble countermeasures to camouflage the leakages via "side channels". Countermeasures against SCA are evolving along with the development of attack techniques. The physical characteristics requires countermeasures over physical layer, which can be generally classified into intrinsic and extrinsic vectors. Extrinsic countermeasures are executed to confuse the attacker by integrating noise, misalignment to the intra activities. Comparatively, intrinsic countermeasures are built into the algorithm itself, to modify the implementation for minimizing the measurable leakage, or making them not sensitive any more. Hiding and Masking are two typical techniques in this category. Concretely, masking applies to the algorithmic level, to alter the sensitive intermediate values with a mask in reversible ways. Unlike the linear masking, non-linear operations that widely exist in modern cryptographies are difficult to be masked. Approved to be an effective counter solution, hiding method mainly mentions dual-rail logic, which is specially devised for flattening or removing the data-dependent leakage in power or EM signatures. In this thesis, apart from the context describing the attack methodologies, efforts have also been dedicated to logic prototype, to mount extensive security investigations to countermeasures on logic-level. A characteristic of SCA resides on the format of leak sources. Typical side-channel attack concerns the power based analysis, where the fundamental capacitance from MOS transistors and other parasitic capacitances are the essential leak sources. Hence, a robust SCA-resistant logic must eliminate or mitigate the leakages from these micro units, such as basic logic gates, I/O ports and routings. The vendor provided EDA tools manipulate the logic from a higher behavioral-level, rather than the lower gate-level where side-channel leakage is generated. So, the classical implementations barely satisfy these needs and inevitably stunt the prototype. In this case, a customized and flexible design scheme is appealing to be devised. This thesis profiles an innovative logic style to counter SCA, which mainly addresses three major aspects: I. The proposed logic is based on the hiding strategy over gate-level dual-rail style to dynamically overbalance side-channel leakage from lower circuit layer; II. This logic exploits architectural features of modern FPGAs, to minimize the implementation expenses; III. It is supported by a set of assistant custom tools, incorporated by the generic FPGA design flow, to have circuit manipulations in an automatic manner. The automatic design toolkit supports the proposed dual-rail logic, facilitating the practical implementation on Xilinx FPGA families. While the methodologies and the tools are flexible to be expanded to a wide range of applications where rigid and sophisticated gate- or routing- constraints are desired. In this thesis a great effort is done to streamline the implementation workflow of generic dual-rail logic. The feasibility of the proposed solutions is validated by selected and widely used crypto algorithm, for thorough and fair evaluation w.r.t. prior solutions. All the proposals are effectively verified by security experiments. The presented research work attempts to solve the implementation troubles. The essence that will be formalized along this thesis is that a customized execution toolkit for modern FPGA systems is developed to work together with the generic FPGA design flow for creating innovative dual-rail logic. A method in crypto security area is constructed to obtain customization, automation and flexibility in low-level circuit prototype with fine-granularity in intractable routings. Main contributions of the presented work are summarized next: Precharge Absorbed-DPL logic: Using the netlist conversion to reserve free LUT inputs to execute the Precharge and Ex signal in a dual-rail logic style. A row-crossed interleaved placement method with identical routing pairs in dual-rail networks, which helps to increase the resistance against selective EM measurement and mitigate the impacts from process variations. Customized execution and automatic transformation tools for producing identical networks for the proposed dual-rail logic. (a) To detect and repair the conflict nets; (b) To detect and repair the asymmetric nets. (c) To be used in other logics where strict network control is required in Xilinx scenario. Customized correlation analysis testbed for EM and power attacks, including the platform construction, measurement method and attack analysis. A timing analysis based method for quantifying the security grades. A methodology of security partitions of complex crypto systems for reducing the protection cost. A proof-of-concept self-adaptive heating system to mitigate electrical impacts over process variations in dynamic dual-rail compensation manner. The thesis chapters are organized as follows: Chapter 1 discusses the side-channel attack fundamentals, which covers from theoretic basics to analysis models, and further to platform setup and attack execution. Chapter 2 centers to SCA-resistant strategies against generic power and EM attacks. In this chapter, a major contribution, a compact and secure dual-rail logic style, will be originally proposed. The logic transformation based on bottom-layer design will be presented. Chapter 3 is scheduled to elaborate the implementation challenges of generic dual-rail styles. A customized design flow to solve the implementation problems will be described along with a self-developed automatic implementation toolkit, for mitigating the design barriers and facilitating the processes. Chapter 4 will originally elaborate the tool specifics and construction details. The implementation case studies and security validations for the proposed logic style, as well as a sophisticated routing verification experiment, will be described in Chapter 5. Finally, a summary of thesis conclusions and perspectives for future work are included in Chapter 5. To better exhibit the thesis contents, each chapter is further described next: Chapter 1 provides the introduction of hardware implementation testbed and side-channel attack fundamentals, and mainly contains: (a) The FPGA generic architecture and device features, particularly of Virtex-5 FPGA; (b) The selected crypto algorithm - a commercially and extensively used Advanced Encryption Standard (AES) module - is detailed; (c) The essentials of Side-Channel methods are profiled. It reveals the correlated dissipation leakage to the internal behaviors, and the method to recover this relationship between the physical fluctuations in side-channel traces and the intra processed data; (d) The setups of the power/EM testing platforms enclosed inside the thesis work are given. The content of this thesis is expanded and deepened from chapter 2, which is divided into several aspects. First, the protection principle of dynamic compensation of the generic dual-rail precharge logic is explained by describing the compensated gate-level elements. Second, the novel DPL is originally proposed by detailing the logic protocol and an implementation case study. Third, a couple of custom workflows are shown next for realizing the rail conversion. Meanwhile, the technical definitions that are about to be manipulated above LUT-level netlist are clarified. A brief discussion about the batched process is given in the final part. Chapter 3 studies the implementation challenges of DPLs in FPGAs. The security level of state-of-the-art SCA-resistant solutions are decreased due to the implementation barriers using conventional EDA tools. In the studied FPGA scenario, problems are discussed from dual-rail format, parasitic impact, technological bias and implementation feasibility. According to these elaborations, two problems arise: How to implement the proposed logic without crippling the security level; and How to manipulate a large number of cells and automate the transformation. The proposed PA-DPL in chapter 2 is legalized with a series of initiatives, from structures to implementation methods. Furthermore, a self-adaptive heating system is depicted and implemented to a dual-core logic, assumed to alternatively adjust local temperature for balancing the negative impacts from silicon technological biases on real-time. Chapter 4 centers to the toolkit system. Built upon a third-party Application Program Interface (API) library, the customized toolkit is able to manipulate the logic elements from post P&R circuit (an unreadable binary version of the xdl one) converted to Xilinx xdl format. The mechanism and rationale of the proposed toolkit are carefully convoyed, covering the routing detection and repairing approaches. The developed toolkit aims to achieve very strictly identical routing networks for dual-rail logic both for separate and interleaved placement. This chapter particularly specifies the technical essentials to support the implementations in Xilinx devices and the flexibility to be expanded to other applications. Chapter 5 focuses on the implementation of the case studies for validating the security grades of the proposed logic style from the proposed toolkit. Comprehensive implementation techniques are discussed. (a) The placement impacts using the proposed toolkit are discussed. Different execution schemes, considering the global optimization in security and cost, are verified with experiments so as to find the optimized placement and repair schemes; (b) Security validations are realized with correlation, timing methods; (c) A systematic method is applied to a BCDL structured module to validate the routing impact over security metric; (d) The preliminary results using the self-adaptive heating system over process variation is given; (e) A practical implementation of the proposed toolkit to a large design is introduced. Chapter 6 includes the general summary of the complete work presented inside this thesis. Finally, a brief perspective for the future work is drawn which might expand the potential utilization of the thesis contributions to a wider range of implementation domains beyond cryptography on FPGAs.

Quality-optimization algorithm based on stochastic dynamic programming for MPEG DASH video streaming

In contrast to traditional push-based protocols, adaptive streaming techniques like Dynamic Adaptive Streaming over HTTP (DASH) fix attention on the client, who dynamically requests different-quality portions of the content to cope with a limited and variable bandwidth but aiming at maximizing the quality perceived by the user. Since DASH adaptation logic at the client is not covered by the standard, we propose a solution based on Stochastic Dynamic Programming (SDP) techniques to find the optimal request policies that guarantee the users' Quality of Experience (QoE). Our algorithm is evaluated in a simulated streaming session and is compared with other adaptation approaches. The results show that our proposal outperforms them in terms of QoE, requesting higher qualities on average.

Static and dynamic lengths of neutrophil microvilli

Containing most of the L-selectin and P-selectin glycoprotein ligand-1 (PSGL-1) on their tips, microvilli are believed to promote the initial arrest of neutrophils on endothelium. At the rolling stage following arrest, the lifetimes of the involved molecular bonds depend on the pulling force imposed by the shear stress of blood flow. With two different methods, electron microscopy and micropipette manipulation, we have obtained two comparable neutrophil microvillus lengths, both ≈0.3 μm in average. We have found also that, under a pulling force, a microvillus can be extended (microvillus extension) or a long thin membrane cylinder (a tether) can be formed from it (tether formation). If the force is ≤34 pN (± 3 pN), the length of the microvillus will be extended; if the force is >61 pN (± 5 pN), a tether will be formed from the microvillus at a constant velocity, which depends linearly on the force. When the force is between 34 pN and 61 pN (transition zone), the degree of association between membrane and cytoskeleton in individual microvilli will dictate whether microvillus extension or tether formation occurs. When a microvillus is extended, it acts like a spring with a spring constant of ≈43 pN/μm. In contrast to a rigid or nonextendible microvillus, both microvillus extension and tether formation can decrease the pulling force imposed on the adhesive bonds, and thus prolonging the persistence of the bonds at high physiological shear stresses.

A substance P (neurokinin-1) receptor mutant carboxyl-terminally truncated to resemble a naturally occurring receptor isoform displays enhanced responsiveness and resistance to desensitization

Two isoforms of the substance P (SP) receptor, differing in the length of the cytoplasmic carboxyl-terminus by ≈8 kDa, have been detected previously in rat salivary glands and other tissues. The binding and functional properties of these two isoforms have been investigated using full-length (407 amino acids) and carboxyl-terminally truncated (324 amino acids) rat SP receptors transfected stably into Chinese hamster ovary cells. Both the full-length and the truncated receptor bound radiolabeled SP with a similar Kd (≈0.1 nM). The average number of high affinity SP binding sites per cell was 1.0 × 105 and 0.3 × 105 for the full-length and the truncated SP receptor, respectively. In both cell lines, SP induced a rapid but transient increase in cytosolic calcium concentration ([Ca2+]i), which consisted of the release of Ca2+ from intracellular stores and the influx of extracellular Ca2+. Both components are dependent on phospholipase C activation. Although the full-length and the truncated receptor utilize the same calcium pathways, they differ in their EC50 values (0.28 nM for the full-length; 0.07 nM for the truncated). These differences in responsiveness may be related to the observed differences in receptor desensitization. The truncated receptor, in contrast to the full-length receptor, does not undergo rapid and long-lasting desensitization. Cells possessing the short isoform of the SP receptor would thus be expected to exhibit a prolonged responsiveness.

Dynamic regulation of c-Jun N-terminal kinase activity in mouse brain by environmental stimuli

Activation of the recently identified c-Jun N-terminal kinases (JNKs) typically results in programmed cell death (apoptosis) in neurons and other cell types grown in culture. However, the effects of JNK activation in the central nervous system in vivo are unknown. At baseline, JNK activity in mice was on average 17-fold higher in brain than in peripheral organs, whereas JNK protein levels were similar. In brain, JNK was expressed primarily in neurons. Restraining mice or allowing them to explore a novel environment rapidly increased JNK activity 3- to 15-fold in various brain regions, but these manipulations did not increase brain activity of the extracellular signal-regulated kinase. Because noninvasive environmental stimuli that do not induce neurodegeneration elicited prominent increases in JNK activity in the brain, we conclude that acute activation of the JNK cascade in central nervous system neurons does not induce neuronal apoptosis in vivo. In contrast, the high baseline activity of JNK in the brain and the activation of the JNK cascade by environmental stimuli suggest that this kinase may play an important physiological role in neuronal function.

Tubulin Polyglycylation: Differential Posttranslational Modification of Dynamic Cytoplasmic and Stable Axonemal Microtubules in Paramecium

Polyglycylation, a posttranslational modification of tubulin, was discovered in the highly stable axonemal microtubules of Paramecium cilia where it involves the lateral linkage of up to 34 glycine units per tubulin subunit. The observation of this type of posttranslational modification mainly in axonemes raises the question as to its relationship with axonemal organization and with microtubule stability. This led us to investigate the glycylation status of cytoplasmic microtubules that correspond to the dynamic microtubules in Paramecium. Two anti-glycylated tubulin monoclonal antibodies (mAbs), TAP 952 and AXO 49, are shown here to exhibit different affinities toward mono- and polyglycylated synthetic tubulin peptides. Using immunoblotting and mass spectrometry, we show that cytoplasmic tubulin is glycylated. In contrast to the highly glycylated axonemal tubulin, which is recognized by the two mAbs, cytoplasmic tubulin reacts exclusively with TAP 952, and the α- and β- tubulin subunits are modified by only 1–5 and 2–9 glycine units, respectively. Our analyses suggest that most of the cytoplasmic tubulin contains side chain lengths of 1 or 2 glycine units distributed on several glycylation sites. The subcellular partition of distinct polyglycylated tubulin isoforms between cytoplasmic and axonemal compartments implies the existence of regulatory mechanisms for glycylation. By following axonemal tubulin immunoreactivity with anti-glycylated tubulin mAbs upon incubation with a Paramecium cellular extract, the presence of a deglycylation enzyme is revealed in the cytoplasm of this organism. These observations establish that polyglycylation is reversible and indicate that, in vivo, an equilibrium between glycylating and deglycylating enzymes might be responsible for the length of the oligoglycine side chains of tubulin.

An in vitro study of the dynamic features of the major histocompatibility complex class I complex relevant to its role as a versatile peptide-receptive molecule

The major histocompatibility complex class I complex consists of a heavy chain and a light chain (β2-microglobulin, β2m), which assemble with a short endogenously derived peptide in the endoplasmic reticulum. The class I peptide can be directly exchanged, either at the cell surface or, as recently described, in vesicles of the endocytic compartments, thus allowing exogenous peptides to enter the class I presentation pathway. To probe the interactions between the components of the class I molecule, we analyzed the exchange of peptide and β2m by using purified, recombinant H2-Kb/peptide complexes in a cell-free in vitro system. The exchange of competitor peptide was primarily dependent on the off-rate of the original peptide in the class I binding groove. Peptide exchange was not enhanced by the presence of exogenous β2m, as exchange occurred to the same extent in its absence. Thus, the exchange of peptide and β2m are independent events. The exchange rate of β2m also was not affected by the dissociation rates of the original peptides. Furthermore, peptides could substantially exchange into class I molecules over a pH range of 5.5 to 7.5, conditions prevalent in certain endocytic compartments. We conclude that the dynamic properties of the components of class I molecules explain its function as a highly peptide-receptive molecule. The major histocompatibility complex class I can readily receive peptides independent of the presence of exogenous β2m, even at a low pH. Such properties are relevant to class I peptide acquisition, which can occur at the cell surface, as well as in specialized endosomes.

Transgenically Enhanced Sorbitol Synthesis Facilitates Phloem Boron Transport and Increases Tolerance of Tobacco to Boron Deficiency1

The mobility of elements within plants contributes to a plant species' tolerance of nutrient deficiencies in the soil. The genetic manipulation of within-plant nutrient movement may therefore provide a means to enhance plant growth under conditions of variable soil nutrient availability. In these experiments tobacco (Nicotiana tabacum) was engineered to synthesize sorbitol, and the resultant effect on phloem mobility of boron (B) was determined. In contrast to wild-type tobacco, transgenic tobacco plants containing sorbitol exhibit a marked increase in within-plant B mobility and a resultant increase in plant growth and yield when grown with limited or interrupted soil B supply. Growth of transgenic tobacco could be maintained by reutilization of B present in mature tissues or from B supplied as a foliar application to mature leaves. In contrast, B present in mature leaves of control tobacco lines could not be used to provide the B requirements for new plant growth. 10B-labeling experiments verified that B is phloem mobile in transgenic tobacco but is immobile in control lines. These results demonstrate that the transgenic enhancement of within-plant nutrient mobility is a viable approach to improve plant tolerance of nutrient stress.

Enhanced sensitivity of ubiquinone-deficient mutants of Saccharomyces cerevisiae to products of autoxidized polyunsaturated fatty acids.

Coenzyme Q (ubiquinone or Q) plays a well known electron transport function in the respiratory chain, and recent evidence suggests that the reduced form of ubiquinone (QH2) may play a second role as a potent lipid-soluble antioxidant. To probe the function of QH2 as an antioxidant in vivo, we have made use of a Q-deficient strain of Saccharomyces cerevisiae harboring a deletion in the COQ3 gene [Clarke, C. F., Williams, W. & Teruya, J. H. (1991) J. Biol. Chem. 266, 16636-16644]. Q-deficient yeast and the wild-type parental strain were subjected to treatment with polyunsaturated fatty acids, which are prone to autoxidation and breakdown into toxic products. In this study we find that Q-deficient yeast are hypersensitive to the autoxidation products of linolenic acid and other polyunsaturated fatty acids. In contrast, the monounsaturated oleic acid, which is resistant to autoxidative breakdown, has no effect. The hypersensitivity of the coq3delta strains can be prevented by the presence of the COQ3 gene on a single copy plasmid, indicating that the sensitive phenotype results solely from the inability to produce Q. As a result of polyunsaturated fatty acid treatment, there is a marked elevation of lipid hydroperoxides in the coq3 mutant as compared with either wild-type or respiratory-deficient control strains. The hypersensitivity of the Q-deficient mutant can be rescued by the addition of butylated hydroxytoluene, alpha-tocopherol, or trolox, an aqueous soluble vitamin E analog. The results indicate that autoxidation products of polyunsaturated fatty acids mediate the cell killing and that QH2 plays an important role in vivo in protecting eukaryotic cells from these products.

Peptide vaccination can lead to enhanced tumor growth through specific T-cell tolerance induction.

Vaccination with synthetic peptides representing cytotoxic T lymphocyte (CTL) epitopes can lead to a protective CTL-mediated immunity against tumors or viruses. We now report that vaccination with a CTL epitope derived from the human adenovirus type 5 E1A-region (Ad5E1A234-243), which can serve as a target for tumor-eradicating CTL, enhances rather than inhibits the growth of Ad5E1A-expressing tumors. This adverse effect of peptide vaccination was rapidly evoked, required low doses of peptide (10 micrograms), and was achieved by a mode of peptide delivery that induces protective T-cell-mediated immunity in other models. Ad5E1A-specific CTL activity could no longer be isolated from mice after injection of Ad5E1A-peptide, indicating that tolerization of Ad5E1A-specific CTL activity causes the enhanced tumor outgrowth. In contrast to peptide vaccination, immunization with adenovirus, expressing Ad5E1A, induced Ad5E1A-specific immunity and prevented the outgrowth of Ad5E1A-expressing tumors. These results show that immunization with synthetic peptides can lead to the elimination of anti-tumor CTL responses. These findings are important for the design of safe peptide-based vaccines against tumors, allogeneic organ transplants, and T-cell-mediated autoimmune diseases.

Enhanced conformational sampling in Monte Carlo simulations of proteins: application to a constrained peptide.

A Monte Carlo simulation method for globular proteins, called extended-scaled-collective-variable (ESCV) Monte Carlo, is proposed. This method combines two Monte Carlo algorithms known as entropy-sampling and scaled-collective-variable algorithms. Entropy-sampling Monte Carlo is able to sample a large configurational space even in a disordered system that has a large number of potential barriers. In contrast, scaled-collective-variable Monte Carlo provides an efficient sampling for a system whose dynamics is highly cooperative. Because a globular protein is a disordered system whose dynamics is characterized by collective motions, a combination of these two algorithms could provide an optimal Monte Carlo simulation for a globular protein. As a test case, we have carried out an ESCV Monte Carlo simulation for a cell adhesive Arg-Gly-Asp-containing peptide, Lys-Arg-Cys-Arg-Gly-Asp-Cys-Met-Asp, and determined the conformational distribution at 300 K. The peptide contains a disulfide bridge between the two cysteine residues. This bond mimics the strong geometrical constraints that result from a protein's globular nature and give rise to highly cooperative dynamics. Computation results show that the ESCV Monte Carlo was not trapped at any local minimum and that the canonical distribution was correctly determined.

Potent interleukin 3 receptor agonist with selectively enhanced hematopoietic activity relative to recombinant human interleukin 3.

A systematic evaluation of structure-activity information led to the construction of genetically engineered interleukin 3 (IL-3) receptor agonists (synthokines) with enhanced hematopoietic potency. SC-55494, the most extensively characterized member of this series, exhibits 10- to 20-fold greater biological activity than recombinant human IL-3 (rhIL-3) in human hematopoietic cell proliferation and marrow colony-forming-unit assays. In contrast, SC-55494 is only twice as active as rhIL-3 in priming the synthesis of inflammatory mediators such as leukotriene C4 and triggering the release of histamine from peripheral blood leukocytes. The enhanced hematopoietic activity of SC-55494 correlates with a 60-fold increase in IL-3 alpha-subunit binding affinity and a 20-fold greater affinity for binding to alpha/beta receptor complexes on intact cells relative to rhIL-3. SC-55494 demonstrates a 5- to 10-fold enhanced hematopoietic response relative to its ability to activate the priming and release of inflammatory mediators. Therefore, SC-55494 may ameliorate the myeloablation of cancer therapeutic regimens while minimizing dose-limiting inflammatory side effects.