Responsiveness of voltage-gated calcium channels in SH-SY5Y human neuroblastoma cells on quasi-three-dimensional micropatterns formed with poly (l-lactic acid)

Introduction: In this study, quasi-three-dimensional (3D) microwell patterns were fabricated with poly (l-lactic acid) for the development of cell-based assays, targeting voltage-gated calcium channels (VGCCs). Methods and materials: SH-SY5Y human neuroblastoma cells were interfaced with the microwell patterns and found to grow as two dimensional (2D), 3D, and near two dimensional (N2D), categorized on the basis of the cells’ location in the pattern. The capability of the microwell patterns to support 3D cell growth was evaluated in terms of the percentage of the cells in each growth category. Cell spreading was analyzed in terms of projection areas under light microscopy. SH-SY5Y cells’ VGCC responsiveness was evaluated with confocal microscopy and a calcium fluorescent indicator, Calcium GreenTM-1. The expression of L-type calcium channels was evaluated using immunofluorescence staining with DM-BODIPY. Results: It was found that cells within the microwells, either N2D or 3D, showed more rounded shapes and less projection areas than 2D cells on flat poly (l-lactic acid) substrates. Also, cells in microwells showed a significantly lower VGCC responsiveness than cells on flat substrates, in terms of both response magnitudes and percentages of responsive cells, upon depolarization with 50 mM K+. This lower VGCC responsiveness could not be explained by the difference in L-type calcium channel expression. For the two patterns addressed in this study, N2D cells consistently exhibited an intermediate value of either projection areas or VGCC responsiveness between those for 2D and 3D cells, suggesting a correlative relation between cell morphology and VGCC responsiveness. Conclusion: These results suggest that the pattern structure and therefore the cell growth characteristics were critical factors in determining cell VGCC responsiveness and thus provide an approach for engineering cell functionality in cell-based assay systems and tissue engineering scaffolds.

Modelo comportamental do capacitor ferroelétrico como unidade básica de neurônios artificiais e sua implementação em FPGA

This work proposes the use of the behavioral model of the hysteresis loop of the ferroelectrics capacitor as a new alternative to the usually costly techniques in the computation of nonlinear functions in artificial neurons implemented on reconfigurable hardware platform, in this case, a FPGA device. Initially the proposal has been validated by the implementation of the boolean logic through the digital models of two artificial neurons: the Perceptron and a variation of the model Integrate and Fire Spiking Neuron, both using the model also digital of the hysteresis loop of the ferroelectric capacitor as it’s basic nonlinear unit for the calculations of the neurons outputs. Finally, it has been used the analog model of the ferroelectric capacitor with the goal of verifying it’s effectiveness and possibly the reduction of the number of necessary logic elements in the case of implementing the artificial neurons on integrated circuit. The implementations has been carried out by Simulink models and the synthesizing has been done through the DSP Builder software from Altera Corporation.

Estudo da sinterização e oxidação anódica na produção de um capacitor eletrolítico de nióbio

It seeks to find an alternative to the current tantalum electrolytic capacitors in the market due to its high cost. Niobium is a potential replacement for be lighter and cheaper than tantalum. They belong to the same table group periodically and thus exhibit several physical and chemical properties similar. Niobium is used in many technologically important applications, and Brazil has the largest reserves, around 96%. These electrolytic capacitors have high specific capacitance, so they can store high energy in small volumes compared to other types of capacitors. This is the main attraction of this type of capacitor because is growing demand in the production of capacitors with capacitance specifies increasingly high, this because of the miniaturization of various devices such as GPS devices, televisions, computers, phones and many others. The production route of the capacitor was made by powder metallurgy. The initial niobium poder was first characterized by XRD, SEM and laser particle size to then be sieved into particle size 400mesh. The powder was then compacted at pressure of 150MPa and sintered at 1400, 1450 and 1500°C using two sintering time 30 and 60min. Sintering is an important part of the process as it affects properties as porosity and surface cleaning of the samples, which greatly affected the quality of the capacitor. After sintering the samples were underwent a process of anodic oxidation (anodizing), which created a thin film of niobium pentoxide over the whole surface of the sample, this film is the dielectric capacitor. The anodizing process variables influenced a lot in film formation and consequently the capacitor. The samples were characterized by electrical measurements of capacitance, loss factor and ESR (equivalent series resistance). The sintering has affected the porosity and in turn the specific area of the samples. The capacitor area is directly related to the capacitance, that is, the higher the specific area is the capacitance. Higher sintering temperatures decrease the surface area but eliminate as many impurities. The best results were obtained at a temperature of 1400°C with 60 minutes. The most interesting results were compared with the specific capacitance and ESR for all samples.

Estudo da sinterização e oxidação anódica na produção de um capacitor eletrolítico de nióbio

It seeks to find an alternative to the current tantalum electrolytic capacitors in the market due to its high cost. Niobium is a potential replacement for be lighter and cheaper than tantalum. They belong to the same table group periodically and thus exhibit several physical and chemical properties similar. Niobium is used in many technologically important applications, and Brazil has the largest reserves, around 96%. These electrolytic capacitors have high specific capacitance, so they can store high energy in small volumes compared to other types of capacitors. This is the main attraction of this type of capacitor because is growing demand in the production of capacitors with capacitance specifies increasingly high, this because of the miniaturization of various devices such as GPS devices, televisions, computers, phones and many others. The production route of the capacitor was made by powder metallurgy. The initial niobium poder was first characterized by XRD, SEM and laser particle size to then be sieved into particle size 400mesh. The powder was then compacted at pressure of 150MPa and sintered at 1400, 1450 and 1500°C using two sintering time 30 and 60min. Sintering is an important part of the process as it affects properties as porosity and surface cleaning of the samples, which greatly affected the quality of the capacitor. After sintering the samples were underwent a process of anodic oxidation (anodizing), which created a thin film of niobium pentoxide over the whole surface of the sample, this film is the dielectric capacitor. The anodizing process variables influenced a lot in film formation and consequently the capacitor. The samples were characterized by electrical measurements of capacitance, loss factor and ESR (equivalent series resistance). The sintering has affected the porosity and in turn the specific area of the samples. The capacitor area is directly related to the capacitance, that is, the higher the specific area is the capacitance. Higher sintering temperatures decrease the surface area but eliminate as many impurities. The best results were obtained at a temperature of 1400°C with 60 minutes. The most interesting results were compared with the specific capacitance and ESR for all samples.

Single Events in a COTS Soft-Error Free SRAM at Low Bias Voltage Induced by 15-MeV Neutrons

This paper presents an experimental study of the sensitivity to 15-MeV neutrons of Advanced Low Power SRAMs (A-LPSRAM) at low bias voltage little above the threshold value that allows the retention of data. This family of memories is characterized by a 3D structure to minimize the area penalty and to cope with latchups, as well as by the presence of integrated capacitors to hinder the occurrence of single event upsets. In low voltage static tests, classical single event upsets were a minor source of errors, but other unexpected phenomena such as clusters of bitflips and hard errors turned out to be the origin of hundreds of bitflips. Besides, errors were not observed in dynamic tests at nominal voltage. This behavior is clearly different than that of standard bulk CMOS SRAMs, where thousands of errors have been reported.

Danger High Voltage Sign

General note: Title and date provided by Bettye Lane.

Déterminants moléculaires de la sensibilité à la flécainide des canaux potassiques voltage dépendants

Mémoire numérisé par la Direction des bibliothèques de l'Université de Montréal.

Direct power control with common mode voltage elimination for open-winding brushless doubly-fed wind power generators

In this paper, a new open-winding control strategy is proposed for a brushless doubly-fed reluctance generator (BDFRG) applicable for wind turbines. The BDFRG control winding is fed via a dual two-level three-phase converter using a single dc bus. Direct power control based on maximum power point tracking with common mode voltage elimination is designed, which not only the active and reactive power is decoupled, but the reliability and redundancy are all improved greatly by increasing the switching modes of operation, while DC-link voltage and rating of power devices decreased by 50% comparing to the traditional three-level converter systems. Consequently its effectiveness is evaluated by simulation tests based on a 42-kW prototype generator.

Performance comparison of direct power control for brushless doubly-fed wind power generator with different control winding structure

A novel open-winding brushless doubly-fed generator (BDFG) system with two two-level bidirectional converters is proposed. This topology is equivalent to a three-level bidirectional converter connected to the typical BDFG, but solves the unbalanced-voltage-division problem of DC capacitor in the three-level converter, and has lower converter capacity, more flexible control mode, and better fault-tolerant ability. The direct power control (DPC) based on the twelve sections is adopted to implement the power tracking of the open-winding BDFG system, which is compared with the typical BDFG DPC system based on the six and twelve sections to verify the advantages of the proposed scheme.

Experimental comparison of artificial neural network and volterra based nonlinear equalization for CO-OFDM

A novel artificial neural network (ANN)-based nonlinear equalizer (NLE) of low complexity is demonstrated for 40-Gb/s CO-OFDM at 2000 km, revealing ∼1.5 dB enhancement in Q-factor compared to inverse Volterra-series transfer function based NLE.

Kerr-induced nonlinearity reduction in coherent optical OFDM by low complexity support vector machine regression-based equalization

We experimentally demonstrate 7-dB reduction of nonlinearity penalty in 40-Gb/s CO-OFDM at 2000-km using support vector machine regression-based equalization. Simulation in WDM-CO-OFDM shows up to 12-dB enhancement in Q-factor compared to linear equalization.

Effects of alternating current voltage amplitude and oxide capacitance on mid-gap interface state defect density extractions in In0.53Ga 0.47As capacitors

This work looks at the effect on mid-gap interface state defect density estimates for In0.53Ga0.47As semiconductor capacitors when different AC voltage amplitudes are selected for a fixed voltage bias step size (100 mV) during room temperature only electrical characterization. Results are presented for Au/Ni/Al2O3/In0.53Ga0.47As/InP metal–oxide–semiconductor capacitors with (1) n-type and p-type semiconductors, (2) different Al2O3 thicknesses, (3) different In0.53Ga0.47As surface passivation concentrations of ammonium sulphide, and (4) different transfer times to the atomic layer deposition chamber after passivation treatment on the semiconductor surface—thereby demonstrating a cross-section of device characteristics. The authors set out to determine the importance of the AC voltage amplitude selection on the interface state defect density extractions and whether this selection has a combined effect with the oxide capacitance. These capacitors are prototypical of the type of gate oxide material stacks that could form equivalent metal–oxide–semiconductor field-effect transistors beyond the 32 nm technology node. The authors do not attempt to achieve the best scaled equivalent oxide thickness in this work, as our focus is on accurately extracting device properties that will allow the investigation and reduction of interface state defect densities at the high-k/III–V semiconductor interface. The operating voltage for future devices will be reduced, potentially leading to an associated reduction in the AC voltage amplitude, which will force a decrease in the signal-to-noise ratio of electrical responses and could therefore result in less accurate impedance measurements. A concern thus arises regarding the accuracy of the electrical property extractions using such impedance measurements for future devices, particularly in relation to the mid-gap interface state defect density estimated from the conductance method and from the combined high–low frequency capacitance–voltage method. The authors apply a fixed voltage step of 100 mV for all voltage sweep measurements at each AC frequency. Each of these measurements is repeated 15 times for the equidistant AC voltage amplitudes between 10 mV and 150 mV. This provides the desired AC voltage amplitude to step size ratios from 1:10 to 3:2. Our results indicate that, although the selection of the oxide capacitance is important both to the success and accuracy of the extraction method, the mid-gap interface state defect density extractions are not overly sensitive to the AC voltage amplitude employed regardless of what oxide capacitance is used in the extractions, particularly in the range from 50% below the voltage sweep step size to 50% above it. Therefore, the use of larger AC voltage amplitudes in this range to achieve a better signal-to-noise ratio during impedance measurements for future low operating voltage devices will not distort the extracted interface state defect density.

Investigation of electrically active defects at the interface of high-k dielectrics and compound semiconductors

As silicon based devices in integrated circuits reach the fundamental limits of dimensional scaling there is growing research interest in the use of high electron mobility channel materials, such as indium gallium arsenide (InGaAs), in conjunction with high dielectric constant (high-k) gate oxides, for Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) based devices. The motivation for employing high mobility channel materials is to reduce power dissipation in integrated circuits while also providing improved performance. One of the primary challenges to date in the field of III-V semiconductors has been the observation of high levels of defect densities at the high-k/III-V interface, which prevents surface inversion of the semiconductor. The work presented in this PhD thesis details the characterization of MOS devices incorporating high-k dielectrics on III-V semiconductors. The analysis examines the effect of modifying the semiconductor bandgap in MOS structures incorporating InxGa1-xAs (x: 0, 0.15. 0.3, 0.53) layers, the optimization of device passivation procedures designed to reduce interface defect densities, and analysis of such electrically active interface defect states for the high-k/InGaAs system. Devices are characterized primarily through capacitance-voltage (CV) and conductance-voltage (GV) measurements of MOS structures both as a function of frequency and temperature. In particular, the density of electrically active interface states was reduced to the level which allowed the observation of true surface inversion behavior in the In0.53Ga0.47As MOS system. This was achieved by developing an optimized (NH4)2S passivation, minimized air exposure, and atomic layer deposition of an Al2O3 gate oxide. An extraction of activation energies allows discrimination of the mechanisms responsible for the inversion response. Finally a new approach is described to determine the minority carrier generation lifetime and the oxide capacitance in MOS structures. The method is demonstrated for an In0.53Ga0.47As system, but is generally applicable to any MOS structure exhibiting a minority carrier response in inversion.

Déterminants moléculaires de la sensibilité à la flécainide des canaux potassiques voltage dépendants

Mémoire numérisé par la Direction des bibliothèques de l'Université de Montréal.

An ether-functionalised cyclic sulfonium based ionic liquid as an electrolyte for electrochemical double layer capacitors

A novel cyclic sulfonium cation-based ionic liquid (IL) with an ether-group appendage and the bis{(trifluoromethyl)sulfonyl}imide anion was synthesised and developed for electrochemical double layer capacitor (EDLC) testing. The synthesis and chemical-physical characterisation of the ether-group containing IL is reported in parallel with a similarly sized alkyl-functionalised sulfonium IL. Results of the chemical-physical measurements demonstrate how important transport properties, i.e. viscosity and conductivity, can be promoted through the introduction of the ether-functionality without impeding thermal, chemical or electrochemical stability of the IL. Although the apparent transport properties are improved relative to the alkyl-functionalised analogue, the ether-functionalised sulfonium cation-based IL exhibits moderately high viscosity, and poorer conductivity, when compared to traditional EDLC electrolytes based on organic solvents (propylene carbonate and acetonitrile). Electrochemical testing of the ether-functionalised sulfonium IL was conducted using activated carbon composite electrodes to inspect the performance of the IL as a solvent-free electrolyte for EDLC application. Good cycling stability was achieved over the studied range and the performance was comparable to other solvent free,
IL-based EDLC systems. Nevertheless, limitations of the attainable performance are primarily the result of sluggish transport properties and a restricted operative voltage of the IL, thus highlighting key aspects of this field which require further attention.