FPGA BASED DESIGN FOR ACCELERATED FAULT-TESTING OF INTEGRATED CIRCUITS

In the past few decades, integrated circuits have become a major part of everyday life. Every circuit that is created needs to be tested for faults so faulty circuits are not sent to end-users. The creation of these tests is time consuming, costly and difficult to perform on larger circuits. This research presents a novel method for fault detection and test pattern reduction in integrated circuitry under test. By leveraging the FPGA's reconfigurability and parallel processing capabilities, a speed up in fault detection can be achieved over previous computer simulation techniques. This work presents the following contributions to the field of Stuck-At-Fault detection: We present a new method for inserting faults into a circuit net list. Given any circuit netlist, our tool can insert multiplexers into a circuit at correct internal nodes to aid in fault emulation on reconfigurable hardware. We present a parallel method of fault emulation. The benefit of the FPGA is not only its ability to implement any circuit, but its ability to process data in parallel. This research utilizes this to create a more efficient emulation method that implements numerous copies of the same circuit in the FPGA. A new method to organize the most efficient faults. Most methods for determinin the minimum number of inputs to cover the most faults require sophisticated softwareprograms that use heuristics. By utilizing hardware, this research is able to process data faster and use a simpler method for an efficient way of minimizing inputs.

3CAM - A NOVEL TERNARY CONTENT ADDRESSABLE MEMORY USING THREE-VALUED LOGIC

Content Addressable Memory (CAM) is a special type of Complementary Metal-Oxide-Semiconductor (CMOS) storage element that allows for a parallel search operation on a memory stack in addition to the read and write operations yielded by a conventional SRAM storage array. In practice, it is often desirable to be able to store a “don’t care” state for faster searching operation. However, commercially available CAM chips are forced to accomplish this functionality by having to include two binary memory storage elements per CAM cell,which is a waste of precious area and power resources. This research presents a novel CAM circuit that achieves the “don’t care” functionality with a single ternary memory storage element. Using the recent development of multiple-voltage-threshold (MVT) CMOS transistors, the functionality of the proposed circuit is validated and characteristics for performance, power consumption, noise immunity, and silicon area are presented. This workpresents the following contributions to the field of CAM and ternary-valued logic:• We present a novel Simple Ternary Inverter (STI) transistor geometry scheme for achieving ternary-valued functionality in existing SOI-CMOS 0.18µm processes.• We present a novel Ternary Content Addressable Memory based on Three-Valued Logic (3CAM) as a single-storage-element CAM cell with “don’t care” functionality.• We explore the application of macro partitioning schemes to our proposed 3CAM array to observe the benefits and tradeoffs of architecture design in the context of power, delay, and area.

Lower complexity bounds in justification logic

Justification Logic studies epistemic and provability phenomena by introducing justifications/proofs into the language in the form of justification terms. Pure justification logics serve as counterparts of traditional modal epistemic logics, and hybrid logics combine epistemic modalities with justification terms. The computational complexity of pure justification logics is typically lower than that of the corresponding modal logics. Moreover, the so-called reflected fragments, which still contain complete information about the respective justification logics, are known to be in~NP for a wide range of justification logics, pure and hybrid alike. This paper shows that, under reasonable additional restrictions, these reflected fragments are NP-complete, thereby proving a matching lower bound. The proof method is then extended to provide a uniform proof that the corresponding full pure justification logics are $\Pi^p_2$-hard, reproving and generalizing an earlier result by Milnikel.

Dual-loop circuits in postoperative atrial macro re-entrant tachycardias

Background Patients late after open-heart surgery may develop dual-loop reentrant atrial arrhythmias, and mapping and catheter ablation remain challenging despite computer-assisted mapping techniques. Objectives The purpose of the study was to demonstrate the prevalence and characteristics of dual-loop reentrant arrhythmias, and to define the optimal mapping and ablation strategy. Methods Fourty consecutive patients (mean age 52+/-12 years) with intra-atrial reentrant tachycardia (IART) after open-heart surgery (with an incision of the right atrial free wall) were studied. Dual-loop IART was defined as the presence of two simultaneous atrial circuits. Following an abrupt tachycardia change during radiofrequency (RF) ablation, electrical disconnection of the targeted reentry isthmus from the remaining circuit was demonstrated by entrainment mapping. Furthermore, the second circuit loop was localized using electroanatomic mapping and/or entrainment mapping. Results Dual-loop IART was demonstrated in 8 patients (20%, 5 patients with congenital heart disease, 3 with acquired heart disease). Dual-loop IART included an isthmus-dependant atrial flutter combined with a reentry related to the atriotomy scar. The diagnosis of dual-loop IART required the comparison of entrainment mapping before and after tachycardiamodification. Overall, 35 patients had successful RF ablation (88%). Success rates were lower in patients with dual-loop IART than in patient without dual-loop IART. Ablation failures in 3 patients with dual-loop IART were related to the inability to properly transect the second tachycardia isthmus in the right atrial free wall. Conclusions Dual-loop IART is relatively common after heart surgery involving a right atriotomy. Abrupt tachycardia change and specific entrainment mapping maneuvers demonstrate these circuits. Electroanatomic mapping appears to be important to assist catheter ablation of periatriotomy circuits.

Object-Oriented Legacy System Trace-based Logic Testing

When reengineering legacy systems, it is crucial to assess if the legacy behavior has been preserved or how it changed due to the reengineering effort. Ideally if a legacy system is covered by tests, running the tests on the new version can identify potential differences or discrepancies. However, writing tests for an unknown and large system is difficult due to the lack of internal knowledge. It is especially difficult to bring the system to an appropriate state. Our solution is based on the acknowledgment that one of the few trustable piece of information available when approaching a legacy system is the running system itself. Our approach reifies the execution traces and uses logic programming to express tests on them. Thereby it eliminates the need to programatically bring the system in a particular state, and handles the test-writer a high-level abstraction mechanism to query the trace. The resulting system, called TESTLOG, was used on several real-world case studies to validate our claims.