四种电化学分析仪器的研制

本报告介绍我们实验室以原有研究工作为基础，结合国家十五科技攻关课题，适应市场需要，研发的生化需氧量(BOD)快速监测仪、溶氧(DO)在线检测仪、毛细管电泳电化学发光检测仪(CE/ECL)、USB插头式超微型电化学研究系统(uECS)等四种电化学分析仪器。BOD、DO仪采用纳米、自组装等技术制作电化学探头，可实现对水体中的BOD、DO的快速、灵敏的检测，所得结果与使用传统的方法相一致，而所需时间很短，可以实时、在线监测;CE/ECL仪系结合了毛细管电泳的高分离能力和电化学发光的高灵敏度的特点开发出的整体仪器;uECS突破了原有电化学分析仪器的概念，结合了先进的USB2.0技术，整个系统体积小巧(如U盘)，通过计算机的USB接口提供电源并进行高速数据传输，具有一般研究型电化学仪的各项功能，并且具有较强的可扩展性。

海洋要素垂直剖面测量系统的数据存储

长期、定点、连续测量海洋环境参数，尤其是从海洋表面到海底的垂直剖面的监测一直以来大都是由船只完成，耗费大量的人力和财力。“海浪驱动自持式海洋要素垂直剖面测量系统”（简称“海马”）利用海洋无时不在的波浪能，驱动滑行器单方向下潜运动，直达海底或程序设定的预定深度，在控制系统作用下，滑行器依靠自身的浮力匀速上浮， 并在此过程中，完成海洋要素的自动测量和存储。 当今海洋仪器大多采用“闪存”来存储数据，主要有RS－232串口和并型口的CF(Compact Flash)卡两种形式。但是两种接口都有一定的缺陷：CF卡不能和PC机直接通信，必须通过转接口才能将数据传送到PC机上；而RS-232接口虽然可以和PC机直接通信，但是由于其传输速度较慢，不利于大量数据的传输。由于上述两种接口的缺点，“海马”采用U盘来实现数据的存储。 USB接口不仅可以和PC机直接通信，而且具有使用方便，数据传输率高，又支持即插即用等特点，但由于USB接口协议复杂，涉及的方面广，特别是软件种类比较多，而且USB芯片种类繁多，使得USB设备的开发非常困难。 本文设计的USB(Universal Serial Bus)接口电路以单片机AT89C51以及CYPRESS公司生产的USB接口芯片SL811HS为核心，结合了随机存储芯片HY62256以及看门狗芯片X25165。在介绍了SL811HS控制器芯片的主要特点的基础上，重点阐述了利用这一芯片在C语言的编程控制之下如何识别U盘的插入和拔出，以及如何将单片机的数据按协议规定写入U盘，其中的协议包括FAT文件协议，USB协议和UFI命令协议。 本系统实现了单片机对U盘的数据存储，速度快，存储容量大，数据读取方便，直观明了，系统工作安全可靠，抗干扰能力强，可扩展性大，而且针对下位机设计的串口协议简单，可以满足“海马”海量数据的存储要求。

角点检测及图像匹配算法研究

本文主要研究角点检测算法和图像的匹配算法。角点是目标轮廓上具有高曲率的点，它可以较好的描述目标的特征。角点检测技术在计算机视觉和图像理解等领域应用很广，例如运动跟踪、目标识别、立体视觉等。角点检测技术被广泛应用的原因在于：角点包含丰富的图像信息，能够对视觉处理提供足够的约束，极大地提高运算速度，在图像之间进行可靠的匹配。 本文首先介绍了一些经典的基于几何特征的角点检测算法。随后本文详细描述了SUSAN算法，并针对其不足提出了一种改进算法。算法的仿真实验结果验证：该改进算法在性能上较原算法有很大提高。计算机视觉和图像处理中另一个重要的研究内容是图像的匹配，它的应用领域也很广泛。为了利用前文的角点提取结果，本文选取了Chang的点模式识别方法来完成图像匹配，算法的匹配仿真实验结果验证了算法的有效性。 本文在最后的章节中尝试了整套算法的硬件实现，硬件仿真的平台是基于DSP和FPGA的。结果证明，所设计的系统具有较好的跟踪能力和抗干扰能力。

基于小波理论的数字图像压缩方法研究

图像压缩是图像处理领域的一个重要研究课题，在图像存储、传输等应用中发挥着至关重要的作用。小波变换具有多分辨率、时频局部性、能量集中能力强等众多优点，因此特别适合于图像压缩。图像压缩主要涉及到图像变换和编码两部分。本文的大部分工作是基于图像变换而展开的，在小波变换理论、基于小波的图像压缩算法理论及其实现、提升小波变换的FPGA实现、以及对两种小波变换算法的改进等方面进行了深入研究和探讨，具体研究内容如下： 1介绍论文的研究背景和意义，并简要介绍图像压缩和小波变换的基本知识和研究现状，概述本论文的主要研究工作。 2详细阐述图像压缩的基本知识，包括图像压缩的原理、分类和图像压缩的国际标准，回顾图像压缩技术的研究历史，并展望一些新的发展方向。 3概述小波变换的基本理论，分析提升小波相对于传统小波变换的优势。分析小波变换应用于图像压缩中的优点，阐述基于小波的分层树集划分（SPIHT）编码算法，并给出实验结果。 4 本文设计了一种并行的二维提升小波变换电路硬件结构，在设计中主要针对小波基的选取、边界拓展方式、提升小波变换数字电路的流水线设计、变换整体结构设计等进行了详细的讨论。这些设计显著降低了资源的消耗，加快了变换速度，提高硬件利用率。 5 由于小波变换缺乏方向性，本文设计了基于Contourlet变换的改进策略，充分利用了Contourlet的方向性，并且克服了其冗余性，使其性能达到最优；针对提升小波不具备平移不变性的特点，将冗余分解的策略引入到提升小波，设计了基于最小熵原则的最佳冗余提升小波分解。并将这两种方法应用图像压缩，取得了较好的效果。

运动目标检测方法及其实时实现技术研究

运动目标检测是计算机视觉研究领域的一项重要课题，具有广阔的应用前景和较高的学术价值。实现可靠、快速的运动目标检测并将其相应算法固化为硬件结构具有非常重要的意义。 本文首先深入研究了基于动态场景的运动目标检测算法，详细讨论了相邻帧差法及其改进方法：三帧差分法，并提出了一种融合相位一致性边缘检测的帧间差分方法；接着在研究了背景差分法的基础上讨论了背景获取和更新机制；然后探讨了块匹配法的基本原理及其匹配准则和快速搜索策略。 其次在研究了基于时空梯度光流计算方法的基础上，结合基于全局和局部约束的混合模型，将PM非线性扩散模型引入到了光流计算过程，同时为了加速计算和克服亮度不变模型对大运动矢量的不适应性，采取了多尺度的计算策略。实验结果表明，该方法对噪声具有较强的鲁棒性并且能够较好的保持目标的运动边缘。 最后开发了一种基于Altera公司Cyclone II系列FPGA芯片的运动目标检测系统，详细介绍了系统的硬件电路设计和相关模块的FPGA实现过程。采用FPGA的实现方案，使得系统的设计灵活、集成度高。

基于RFID的基带通信IP核的设计与仿真

分析基于射频识别(RFID)技术的系统基带通信过程,建立RFID基带传输模型,利用FPGA技术实现具有基带编解码、数据收发功能的通信IP核,介绍基于模块化思想的基带通信IP核的RTL设计方法,利用QuartusⅡ与Simulink工具进行系统仿真,仿真实验结果表明,该通信模块是有效的,能够为设计RFID通信系统提供高度集成的基带通信IP核。

UHF RFID 射频前端及其编解码设计

射频识别（Radio Frequency Identification，RFID）技术，是一种利用射频通信实现的非接触式的数据采集和自动识别技术（以下通称RFID技术）。而超高频射频识别技术（Ultra High Frequency RFID，UHF RFID）具有识别距离远、识别准确率高、识别速度快、抗干扰能力强等特点而成为当前研发的热点。UHF RFID读写器的难点就在于射频前端电路和基带编解码的设计，它们设计的好坏直接决定了读写器的性能好坏。 本文首先通过介绍UHF RFID读写器射频前端设计的基本原理，采用射频通用收发模块进行射频前端设计的方法，给出了以ADF7020收发芯片为核心的UHF RFID读写器的射频前端的整体设计和具体的实现电路，设计了包括射频收发电路、射频前端匹配电路、滤波电路、环行器电路、功率放大电路等。 其次根据EPC Gen-2的协议标准进行了UHF RFID读写器的基带编码解码的仿真设计，然后开发了以FPGA为核心的完整的数字基带硬件电路，实际调试表明整个基带编解码软件在硬件基带PCB板上运行状况良好，并能对EPC Gen-2的协议标准的命令进行正确的编码解码。 最后通过研究学习软件无线电的理论和开发方法，把UHF　RFID读写器的射频前端分成射频模拟前端和射频数字前端，给出了一种基于软件无线电思想的UHF RFID射频数字前端设计模型，并借助于SIMULINK中的信号处理工具箱对构建的数字前端的进行仿真验证，仿真结果验证了用软件无线电实现UHF RFID数字前端的可行性。

PROFIBUS-DP从站通信控制器的设计与实现

PROFIBUS是一种国际化、开放式、不依赖于设备生产厂商的现场总线标准，PROFIBUS-DP作为PROFIBUS的一个分支，以其成熟性、实时性、可靠性和稳定性，在全球范围内的工业自动化领域获得了最为广泛的应用。PROFIBUS-DP协议比较复杂, 目前只有少数国外厂商提供专用的PROFIBUS-DP协议芯片，而国内对于PROFIBUS-DP总线的应用基本以购买国外自动化设备厂商的PROFIBUS-DP通信芯片为主，导致我国的自动化行业难以掌握核心技术。因此研究和开发具有自主知识产权的PROFIBUS-DP通信芯片具有广阔的前景和重要的意义。本文通过深入研究PROFIBUS-DP协议，提出了一套完整的设计方案，并设计出符合PROFIBUS-DP协议的IP核，为最终PROFIBUS-DP通信芯片的实现打下了坚实的基础。 本文详细的介绍了PROFIBUS-DP从站通信控制器的设计实现过程。首先通过分析PROFIBUS-DP协议以及参考国外现有的芯片资料，结合自身研究，提出了PROFIBUS-DP从站通信控制器的整体设计方案，给出了设计的整体框图；其次在整体设计方案的基础上详细介绍了各个功能模块的实现方法，以此为基础，采用自顶向下的设计方法，对各个模块进行详细的设计，并给出了Verilog语言实现RTL编码以及核心功能模块的仿真波形图；最后采用ALTERA公司的Cyclone EP1C6 的FPGA芯片和Philips公司的P89LV51RD2 MCU搭建了一个标准化的智能型从站，并采用ProfiCore和ProfiScrit搭建了PROFIBUS-DP从站控制器的系统级验证环境，进行了系统级验证，充分证实了设计方案的可行性。

智能相机在激光焊缝跟踪检测系统中的应用研究

本文以中国科学院知识创新工程重要方向项目“全自动激光拼焊成套装备关键技术研究与示范应用”及沈阳市科技攻关项目“激光视觉焊缝自动跟踪与质量检测系统”为依托，针对激光焊接这个难点问题，在广泛调研国内外研究现状的基础上，研究开发了一套激光视觉焊缝跟踪检测原理样机。本文主要包括以下四方面的工作：1焊缝跟踪系统的系统结构搭建；2图像处理方法研究；3图像处理方法在FPGA中的实现；4基于工业机器人的激光焊接实验 及结果分析。具体工作如下： 本文首先论述了应用于焊缝跟踪的线结构光视觉传感器检测原理，建立了激光焊缝跟踪检测系统实验平台。该平台由图像采集与处理模块、上位机系统、DSP控制器、伺服电机驱动器、伺服电机等五部分组成。 激光拼焊焊缝跟踪图像的处理方法是关键技术之一，直接影响系统的实时性，根据激光拼焊焊缝跟踪图像的特点设计了相应的图像处理算法，分析研究了基于数学形态学的焊缝跟踪结构光条纹图像增强算法，并根据本课题的特点提出了一种基于模板的边缘提取方法，能简洁快速地提取出单像素边缘，然后研究了结构光中心线提取算法以及焊缝特征点识别算法，最后通过仿真实验验证了该图像处理流程的有效性。 论文的重点在于图像处理方法在智能相机中的实时实现。跟踪系统对图像处理的实时性要求很高，传统的处理方法主要是在DSP中以软件编程的方式实现，速度难以进一步提高，本课题中通过在智能相机中的FPGA中构建一个SOPC系统，将基于硬件描述语言VHDL完成的图像预处理模块和基于Xilinx公司的microblaze软核的特征点提取模块集成在单片芯片上，实现了激光条纹特征点的实时提取，系统具有高度的灵活性与出色的功能。 最后对搭建的跟踪系统平台进行了实验研究，用实验验证了焊缝跟踪系统的性能，保证了该套系统能够满足实时跟踪的要求，可以达到预期的设计目标。

Mini-electrochemical detector for microchip electrophoresis

This paper presents the development of a mini-electrochemical detector for microchip electrophoresis. The small size (3.6 x 5.0 cm(2), W x L) of the detector is compatible with the dimension of the microchip. The use of universal serial bus (USB) ports facilitates installation and use of the detector, miniaturizes the detector, and makes it ideal for lab-on-a-chip applications. A fixed 10 M Omega feedback resistance was chosen to convert current of the working electrode to voltage with second gain of 1, 2, 4, 8, 16, 32, 64 and 128 for small signal detection instead of adopting selectable feedback resistance. Special attention has been paid to the power support circuitry and printed circuit board (PCB) design in order to obtain good performance in such a miniature size. The working electrode potential could be varied over a range of +/-2.5 V with a resolution of 0.01 mV. The detection current ranges from -0.3 x 10(-7) A to 2.5 x 10(-7) A and the noise is lower than 1 pA. The analytical performance of the new system was demonstrated by the detection of epinephrine using an integrated PDMS/glass microchip with detection limit of 2.1 mu M (S/N = 3).

Project Sanitarium: gaming TB: a serious game for a serious problem

Collaborative projects between Industry and Academia provide excellent opportunities for learning. Throughout the academic year 2014-2015 undergraduates from the School of Arts, Media and Computer Games at Abertay University worked with academics from the Infection Group at the University of St Andrews and industry partners Microsoft and DeltaDNA. The result was a serious game prototype that utilized game design techniques and technology to demystify and educate players about the diagnosis and treatment of one of the world's oldest and deadliest diseases, Tuberculosis (TB). Project Sanitarium is a game incorporating a mathematical model that is based on data from real-world drug trials. This paper discusses the project design and development, demonstrating how the project builds on the successful collaborative pedagogical model developed by academic staff at Abertay University. The aim of the model is to provide undergraduates with workplace simulation, wider industry collaboration and access to academic expertise to solve challenging and complex problems.

A Customizable Camera-based Human Computer Interaction System Allowing People With Disabilities Autonomous Hands Free Navigation of Multiple Computing Task

Many people suffer from conditions that lead to deterioration of motor control and makes access to the computer using traditional input devices difficult. In particular, they may loose control of hand movement to the extent that the standard mouse cannot be used as a pointing device. Most current alternatives use markers or specialized hardware to track and translate a user's movement to pointer movement. These approaches may be perceived as intrusive, for example, wearable devices. Camera-based assistive systems that use visual tracking of features on the user's body often require cumbersome manual adjustment. This paper introduces an enhanced computer vision based strategy where features, for example on a user's face, viewed through an inexpensive USB camera, are tracked and translated to pointer movement. The main contributions of this paper are (1) enhancing a video based interface with a mechanism for mapping feature movement to pointer movement, which allows users to navigate to all areas of the screen even with very limited physical movement, and (2) providing a customizable, hierarchical navigation framework for human computer interaction (HCI). This framework provides effective use of the vision-based interface system for accessing multiple applications in an autonomous setting. Experiments with several users show the effectiveness of the mapping strategy and its usage within the application framework as a practical tool for desktop users with disabilities.

VAMP - a vision based sensor network for health care hygiene

Adequate hand-washing has been shown to be a critical activity in preventing the transmission of infections such as MRSA in health-care environments. Hand-washing guidelines published by various health-care related institutions recommend a technique incorporating six hand-washing poses that ensure all areas of the hands are thoroughly cleaned. In this paper, an embedded wireless vision system (VAMP) capable of accurately monitoring hand-washing quality is presented. The VAMP system hardware consists of a low resolution CMOS image sensor and FPGA processor which are integrated with a microcontroller and ZigBee standard wireless transceiver to create a wireless sensor network (WSN) based vision system that can be retargeted at a variety of health care applications. The device captures and processes images locally in real-time, determines if hand-washing procedures have been correctly undertaken and then passes the resulting high-level data over a low-bandwidth wireless link. The paper outlines the hardware and software mechanisms of the VAMP system and illustrates that it offers an easy to integrate sensor solution to adequately monitor and improve hand hygiene quality. Future work to develop a miniaturized, low cost system capable of being integrated into everyday products is also discussed.

Wireless sensor node design for heterogeneous networks

Two complementary wireless sensor nodes for building two-tiered heterogeneous networks are presented. A larger node with a 25 mm by 25 mm size acts as the backbone of the network, and can handle complex data processing. A smaller, cheaper node with a 10 mm by 10 mm size can perform simpler sensor-interfacing tasks. The 25mm node is based on previous work that has been done in the Tyndall National Institute that created a modular wireless sensor node. In this work, a new 25mm module is developed operating in the 433/868 MHz frequency bands, with a range of 3.8 km. The 10mm node is highly miniaturised, while retaining a high level of modularity. It has been designed to support very energy efficient operation for applications with low duty cycles, with a sleep current of 3.3 μA. Both nodes use commercially available components and have low manufacturing costs to allow the construction of large networks. In addition, interface boards for communicating with nodes have been developed for both the 25mm and 10mm nodes. These interface boards provide a USB connection, and support recharging of a Li-ion battery from the USB power supply. This paper discusses the design goals, the design methods, and the resulting implementation.

Hardware design of cryptographic accelerators

With the rapid growth of the Internet and digital communications, the volume of sensitive electronic transactions being transferred and stored over and on insecure media has increased dramatically in recent years. The growing demand for cryptographic systems to secure this data, across a multitude of platforms, ranging from large servers to small mobile devices and smart cards, has necessitated research into low cost, flexible and secure solutions. As constraints on architectures such as area, speed and power become key factors in choosing a cryptosystem, methods for speeding up the development and evaluation process are necessary. This thesis investigates flexible hardware architectures for the main components of a cryptographic system. Dedicated hardware accelerators can provide significant performance improvements when compared to implementations on general purpose processors. Each of the designs proposed are analysed in terms of speed, area, power, energy and efficiency. Field Programmable Gate Arrays (FPGAs) are chosen as the development platform due to their fast development time and reconfigurable nature. Firstly, a reconfigurable architecture for performing elliptic curve point scalar multiplication on an FPGA is presented. Elliptic curve cryptography is one such method to secure data, offering similar security levels to traditional systems, such as RSA, but with smaller key sizes, translating into lower memory and bandwidth requirements. The architecture is implemented using different underlying algorithms and coordinates for dedicated Double-and-Add algorithms, twisted Edwards algorithms and SPA secure algorithms, and its power consumption and energy on an FPGA measured. Hardware implementation results for these new algorithms are compared against their software counterparts and the best choices for minimum area-time and area-energy circuits are then identified and examined for larger key and field sizes. Secondly, implementation methods for another component of a cryptographic system, namely hash functions, developed in the recently concluded SHA-3 hash competition are presented. Various designs from the three rounds of the NIST run competition are implemented on FPGA along with an interface to allow fair comparison of the different hash functions when operating in a standardised and constrained environment. Different methods of implementation for the designs and their subsequent performance is examined in terms of throughput, area and energy costs using various constraint metrics. Comparing many different implementation methods and algorithms is nontrivial. Another aim of this thesis is the development of generic interfaces used both to reduce implementation and test time and also to enable fair baseline comparisons of different algorithms when operating in a standardised and constrained environment. Finally, a hardware-software co-design cryptographic architecture is presented. This architecture is capable of supporting multiple types of cryptographic algorithms and is described through an application for performing public key cryptography, namely the Elliptic Curve Digital Signature Algorithm (ECDSA). This architecture makes use of the elliptic curve architecture and the hash functions described previously. These components, along with a random number generator, provide hardware acceleration for a Microblaze based cryptographic system. The trade-off in terms of performance for flexibility is discussed using dedicated software, and hardware-software co-design implementations of the elliptic curve point scalar multiplication block. Results are then presented in terms of the overall cryptographic system.