Longitudinal familial analysis of blood pressure involving parametric (co)variance functions

Abstract Background For analyzing longitudinal familial data we adopted a log-linear form to incorporate heterogeneity in genetic variance components over the time, and additionally a serial correlation term in the genetic effects at different levels of ages. Due to the availability of multiple measures on the same individual, we permitted environmental correlations that may change across time. Results Systolic blood pressure from family members from the first and second cohort was used in the current analysis. Measures of subjects receiving hypertension treatment were set as censored values and they were corrected. An initial check of the variance and covariance functions proposed for analyzing longitudinal familial data, using empirical semi-variogram plots, indicated that the observed trait dispersion pattern follows the assumptions adopted. Conclusion The corrections for censored phenotypes based on ordinary linear models may be an appropriate simple model to correct the data, ensuring that the original variability in the data was retained. In addition, empirical semi-variogram plots are useful for diagnosis of the (co)variance model adopted.

Development of nanoinjector devices for electrospray ionization - tandem mass spectrometry (ESI-MSn)

In mass spectrometric (MS) systems with electrospray ionization (ESI), the sample can be analyzed coupled to separation systems (such as liquid chromatography or capillary electrophoresis) or simply by direct infusion. The greatest benefit of the type of injection is the possibility of continuous use of small amounts of samples over a long period of time. This extended analysis time allows a complete study of fragmentation by mass spectrometry, which is critical for structure elucidation of new compounds, or when using an ion trap mass analyzer. The injector filled with the sample is placed at the ESI source inlet creating an electric field suitable for the continuous formation of a spray (solvent and sample) and consequently, the gradual and even release of the sample. For the formation of the spray, is necessary that the injector end is metalized. The formation of a bilayer of titanium and gold provided an excellent attachment of the film, resulting in a nanoinjector for ionization/spray formation in the system for MS. The nanoinjectors showed high repeatability and stability over 100 min by continuous sampling with 10 µL of sample.

Parametric analysis of effective material properties of thickness-shear piezoelectric macro-fibre composites

A previous study on the characterization of effective material properties of a d15 thickness-shear piezoelectric Macro-Fibre Composite (MFC) made of seven layers (Kapton, Acrylic, Electrode, Piezoceramic Fibre and Epoxy Composite, Electrode, Acrylic, Kapton) using a finite element homogenization method has shown that the packaging reduces significantly the shear stiffness of the piezoceramic material and, thus, leads to significantly smaller effective electromechanical coupling coefficient k15 and piezoelectric stress constant e15 when compared to the piezoceramic fibre properties. Therefore, the main objective of this work is to perform a parametric analysis in which the effect of the variations of fibre volume fraction, Epoxy elastic modulus, electrode thickness and active layer thickness on the MFC effective material properties is evaluated. Results indicate that an effective d15 MFC should use relatively thick fibres having relatively high shear modulus and relatively stiff epoxy filler. On the other hand, the electrode thickness does not affect significantly the MFC performance.

Parametric study of retangular patch antenna using denim textile material

—This paper presents a textile patch antenna designed for WBAN applications at 2.45 GHz ISM band. The antenna uses denim as substrate and conductive fabric for the ground plane and radiator layers. The main purpose of this paper is to analyze the influence of typical deviation of denim properties and patch radiator dimensions on the performance of the antenna. The parameters considered in the analysis are the relative permittivity and thickness of denim and the width and length of the rectangular patch radiator. The dependence of the central operation frequency of the antenna on those parameters was studied using the antenna reflection coefficient obtained from EM simulations. Rules of thumb for one-shot design were derived and applied to design a rectangular patch antenna. An antenna prototype was fabricated and measured, demonstrating a 10 dB impedance band of 4.8 % centered at 2.45 GHz, in good agreement with simulated results

Diseño de un sistema de captación de energía residual basado en el acondicionador EH300 de la empresa Advanced Linear Devices

Proyecto y presentación del Proyecto Fin de Carrera titulado "DISEÑO DE UN SISTEMA DE CAPTACIÓN DE ENERGÍA RESIDUAL BASADO EN EL ACONDICIONADOR EH300 DE LA EMPRESA ADVANCED LINEAR DEVICES"

CMoS lab-on-a-chip devices for individual cell biology

The development of microlectronic lab-on-a-chip devices (LOACs) can now be pursued thanks to the continous advances in silicon technology. LOACs are miniaturized devices whose aim is to perform in a more efficient way specific chemical or biological analysis protocols which are usually carried out with traditional laboratory equipment. In this application area, CMOS technology has the potential to integrate LOAC functionalities for cell biology applications in single chips, e.g. sensors, actuators, signal conditioning and processing circuits. In this work, after a review of the state of the art, the development of a CMOS prototype chip for individual cell manipulation and detection based on dielectrophoresis will be presented. Issues related to the embedded optical and capacitive detection of cells will be discussed together with the main experimental results obtained in manipulation and detection of living cells and microparticles.

Mixed-domain simulation and hybrid wafer-level packaging of RF-MEMS devices for wireless applications

In questa tesi verranno trattati sia il problema della creazione di un ambiente di simulazione a domini fisici misti per dispositivi RF-MEMS, che la definizione di un processo di fabbricazione ad-hoc per il packaging e l’integrazione degli stessi. Riguardo al primo argomento, sarà mostrato nel dettaglio lo sviluppo di una libreria di modelli MEMS all’interno dell’ambiente di simulazione per circuiti integrati Cadence c . L’approccio scelto per la definizione del comportamento elettromeccanico dei MEMS è basato sul concetto di modellazione compatta (compact modeling). Questo significa che il comportamento fisico di ogni componente elementare della libreria è descritto per mezzo di un insieme limitato di punti (nodi) di interconnessione verso il mondo esterno. La libreria comprende componenti elementari, come travi flessibili, piatti rigidi sospesi e punti di ancoraggio, la cui opportuna interconnessione porta alla realizzazione di interi dispositivi (come interruttori e capacità variabili) da simulare in Cadence c . Tutti i modelli MEMS sono implementati per mezzo del linguaggio VerilogA c di tipo HDL (Hardware Description Language) che è supportato dal simulatore circuitale Spectre c . Sia il linguaggio VerilogA c che il simulatore Spectre c sono disponibili in ambiente Cadence c . L’ambiente di simulazione multidominio (ovvero elettromeccanico) così ottenuto permette di interfacciare i dispositivi MEMS con le librerie di componenti CMOS standard e di conseguenza la simulazione di blocchi funzionali misti RF-MEMS/CMOS. Come esempio, un VCO (Voltage Controlled Oscillator) in cui l’LC-tank è realizzato in tecnologia MEMS mentre la parte attiva con transistor MOS di libreria sarà simulato in Spectre c . Inoltre, nelle pagine successive verrà mostrata una soluzione tecnologica per la fabbricazione di un substrato protettivo (package) da applicare a dispositivi RF-MEMS basata su vie di interconnessione elettrica attraverso un wafer di Silicio. La soluzione di packaging prescelta rende possibili alcune tecniche per l’integrazione ibrida delle parti RF-MEMS e CMOS (hybrid packaging). Verranno inoltre messe in luce questioni riguardanti gli effetti parassiti (accoppiamenti capacitivi ed induttivi) introdotti dal package che influenzano le prestazioni RF dei dispositivi MEMS incapsulati. Nel dettaglio, tutti i gradi di libertà del processo tecnologico per l’ottenimento del package saranno ottimizzati per mezzo di un simulatore elettromagnetico (Ansoft HFSSTM) al fine di ridurre gli effetti parassiti introdotti dal substrato protettivo. Inoltre, risultati sperimentali raccolti da misure di strutture di test incapsulate verranno mostrati per validare, da un lato, il simulatore Ansoft HFSSTM e per dimostrate, dall’altro, la fattibilit`a della soluzione di packaging proposta. Aldilà dell’apparente debole legame tra i due argomenti sopra menzionati è possibile identificare un unico obiettivo. Da un lato questo è da ricercarsi nello sviluppo di un ambiente di simulazione unificato all’interno del quale il comportamento elettromeccanico dei dispositivi RF-MEMS possa essere studiato ed analizzato. All’interno di tale ambiente, l’influenza del package sul comportamento elettromagnetico degli RF-MEMS può essere tenuta in conto per mezzo di modelli a parametri concentrati (lumped elements) estratti da misure sperimentali e simulazioni agli Elementi Finiti (FEM) della parte di package. Infine, la possibilità offerta dall’ambiente Cadence c relativamente alla simulazione di dipositivi RF-MEMS interfacciati alla parte CMOS rende possibile l’analisi di blocchi funzionali ibridi RF-MEMS/CMOS completi.

Interconnection systems for highly integrated computation devices

The sustained demand for faster,more powerful chips has beenmet by the availability of chip manufacturing processes allowing for the integration of increasing numbers of computation units onto a single die. The resulting outcome, especially in the embedded domain, has often been called SYSTEM-ON-CHIP (SOC) or MULTI-PROCESSOR SYSTEM-ON-CHIP (MPSOC). MPSoC design brings to the foreground a large number of challenges, one of the most prominent of which is the design of the chip interconnection. With a number of on-chip blocks presently ranging in the tens, and quickly approaching the hundreds, the novel issue of how to best provide on-chip communication resources is clearly felt. NETWORKS-ON-CHIPS (NOCS) are the most comprehensive and scalable answer to this design concern. By bringing large-scale networking concepts to the on-chip domain, they guarantee a structured answer to present and future communication requirements. The point-to-point connection and packet switching paradigms they involve are also of great help in minimizing wiring overhead and physical routing issues. However, as with any technology of recent inception, NoC design is still an evolving discipline. Several main areas of interest require deep investigation for NoCs to become viable solutions: • The design of the NoC architecture needs to strike the best tradeoff among performance, features and the tight area and power constraints of the on-chip domain. • Simulation and verification infrastructure must be put in place to explore, validate and optimize the NoC performance. • NoCs offer a huge design space, thanks to their extreme customizability in terms of topology and architectural parameters. Design tools are needed to prune this space and pick the best solutions. • Even more so given their global, distributed nature, it is essential to evaluate the physical implementation of NoCs to evaluate their suitability for next-generation designs and their area and power costs. This dissertation focuses on all of the above points, by describing a NoC architectural implementation called ×pipes; a NoC simulation environment within a cycle-accurate MPSoC emulator called MPARM; a NoC design flow consisting of a front-end tool for optimal NoC instantiation, called SunFloor, and a set of back-end facilities for the study of NoC physical implementations. This dissertation proves the viability of NoCs for current and upcoming designs, by outlining their advantages (alongwith a fewtradeoffs) and by providing a full NoC implementation framework. It also presents some examples of additional extensions of NoCs, allowing e.g. for increased fault tolerance, and outlines where NoCsmay find further application scenarios, such as in stacked chips.

Shape design optimization of road acoustic barriers featuring top-edge devices by using Genetic Algotithms and Boundary Elements

[EN] This paper presents a Boundary Elements (BE) approach for the efficiency improvement of road acoustic barriers, mora specifically, for the shape design optimization of top-edge devices in the search for the best designs in terms of screening performance, usually represented by the insertion loss (IL).

TCAD approaches to multidimensional simulation of advanced semiconductor devices

Technology scaling increasingly emphasizes complexity and non-ideality of the electrical behavior of semiconductor devices and boosts interest on alternatives to the conventional planar MOSFET architecture. TCAD simulation tools are fundamental to the analysis and development of new technology generations. However, the increasing device complexity is reflected in an augmented dimensionality of the problems to be solved. The trade-off between accuracy and computational cost of the simulation is especially influenced by domain discretization: mesh generation is therefore one of the most critical steps and automatic approaches are sought. Moreover, the problem size is further increased by process variations, calling for a statistical representation of the single device through an ensemble of microscopically different instances. The aim of this thesis is to present multi-disciplinary approaches to handle this increasing problem dimensionality in a numerical simulation perspective. The topic of mesh generation is tackled by presenting a new Wavelet-based Adaptive Method (WAM) for the automatic refinement of 2D and 3D domain discretizations. Multiresolution techniques and efficient signal processing algorithms are exploited to increase grid resolution in the domain regions where relevant physical phenomena take place. Moreover, the grid is dynamically adapted to follow solution changes produced by bias variations and quality criteria are imposed on the produced meshes. The further dimensionality increase due to variability in extremely scaled devices is considered with reference to two increasingly critical phenomena, namely line-edge roughness (LER) and random dopant fluctuations (RD). The impact of such phenomena on FinFET devices, which represent a promising alternative to planar CMOS technology, is estimated through 2D and 3D TCAD simulations and statistical tools, taking into account matching performance of single devices as well as basic circuit blocks such as SRAMs. Several process options are compared, including resist- and spacer-defined fin patterning as well as different doping profile definitions. Combining statistical simulations with experimental data, potentialities and shortcomings of the FinFET architecture are analyzed and useful design guidelines are provided, which boost feasibility of this technology for mainstream applications in sub-45 nm generation integrated circuits.