A CMOS Gas Sensor Array Platform With Fourier Transform Based Impedance Spectroscopy

A CMOS gas sensor array platform with digital read-out containing 27 sensor pixels and a reference pixel is presented. A signal conditioning circuit at each pixel includes digitally programmable gain stages for sensor signal amplification followed by a second order continuous time delta sigma modulator for digitization. Each sensor pixel can be functionalized with a distinct sensing material that facilitates transduction based on impedance change. Impedance spectrum (up to 10 KHz) of the sensor is obtained off-chip by computing the fast Fourier transform of sensor and reference pixel outputs. The reference pixel also compensates for the phase shift introduced by the signal processing circuits. The chip also contains a temperature sensor with digital readout for ambient temperature measurement. A sensor pixel is functionalized with polycarbazole conducting polymer for sensing volatile organic gases and measurement results are presented. The chip is fabricated in a 0.35 CMOS technology and requires a single step post processing for functionalization. It consumes 57 mW from a 3.3 V supply.

MACHINING OF MMCs: A REVIEW

Over the last few decades, Metal Matrix Composites (MMCs) have emerged as a material system offering tremendous potential for future applications. The primary advantages offered by these materials are their improved mechanical properties, particularly in the areas of wear, strength and stiffness. Of the MMCs, Aluminum matrix composites have grown in prominence due to their low density, low melting point and low cost. However, machining these materials remains a challenging task mainly due to the high abrasiveness of the reinforcing phases. Conventional machining processes such as turning, milling or drilling are adopted for machining MMCs. In this article, the existing and ongoing developments in machining MMCs vis-a-vis tool life, tool wear, machinability and understanding chip formation mechanism have been highlighted. Most of the studies discussed in this review will focus on Aluminum matrix composites. Certain areas of machining studies which have hitherto not been investigated have also been detailed.

Evaluation of dynamic voltage and frequency scaling for stream programs

Dynamic Voltage and Frequency Scaling (DVFS) offers a huge potential for designing trade-offs involving energy, power, temperature and performance of computing systems. In this paper, we evaluate three different DVFS schemes - our enhancement of a Petri net performance model based DVFS method for sequential programs to stream programs, a simple profile based Linear Scaling method, and an existing hardware based DVFS method for multithreaded applications - using multithreaded stream applications, in a full system Chip Multiprocessor (CMP) simulator. From our evaluation, we find that the software based methods achieve significant Energy/Throughput2(ET−2) improvements. The hardware based scheme degrades performance heavily and suffers ET−2 loss. Our results indicate that the simple profile based scheme achieves the benefits of the complex Petri net based scheme for stream programs, and present a strong case for the need for independent voltage/frequency control for different cores of CMPs, which is lacking in most of the state-of-the-art CMPs. This is in contrast to the conclusions of a recent evaluation of per-core DVFS schemes for multithreaded applications for CMPs.

Comparison of performance of OCDMA networks with correlation and chiplevel receivers

In this paper optical code-division multiple-access (O-CDMA) packet network is considered, which offers inherent security in the access networks. Two types of random access protocols are proposed for packet transmission. In protocol 1, all distinct codes and in protocol 2, distinct codes as well as shifted versions of all these codes are used. O-CDMA network performance using optical orthogonal codes (OOCs) 1-D and two-dimensional (2-D) wavelength/time single-pulse-per-row (W/T SPR) codes are analyzed. The main advantage of using 2-D codes instead of one-dimensional (1-D) codes is to reduce the errors due to multiple access interference among different users. In this paper, correlation receiver and chip-level receiver are considered in the analysis. Using analytical model, we compute packet-success probability, throughput and compare for OOC and SPR codes in an O-CDMA network and the analysis shows improved performance with SPR codes as compared to OOC codes.

Multiuser detection in large-dimension multicode MIMO-CDMA systems with higher-order modulation

In this paper, we are interested in high spectral efficiency multicode CDMA systems with large number of users employing single/multiple transmit antennas and higher-order modulation. In particular, we consider a local neighborhood search based multiuser detection algorithm which offers very good performance and complexity, suited for systems with large number of users employing M-QAM/M-PSK. We apply the algorithm on the chip matched filter output vector. We demonstrate near-single user (SU) performance of the algorithm in CDMA systems with large number of users using 4-QAM/16-QAM/64-QAM/8-PSK on AWGN, frequency-flat, and frequency-selective fading channels. We further show that the algorithm performs very well in multicode multiple-input multiple-output (MIMO) CDMA systems as well, outperforming other linear detectors and interference cancelers reported in the literature for such systems. The per-symbol complexity of the search algorithm is O(K2n2tn2cM), K: number of users, nt: number of transmit antennas at each user, nc: number of spreading codes multiplexed on each transmit antenna, M: modulation alphabet size, making the algorithm attractive for multiuser detection in large-dimension multicode MIMO-CDMA systems with M-QAM.

MEMS based microactuator for microjet applications

The objective of this work is to confirm the possibility of utilization of PolyVinyliDeneFlouride (PVDF) films in MEMS based microactuator for microjet applications. A membrane type microactuator is designed, developed, packaged and tested. The microactuator consists of PVDF film attached to thin Silicon diaphragm. As the voltage difference is applied across it, due to the piezoelectric behaviour, it deforms primarily in d31 mode, which in turn deflects the diaphragm. Using finite element methods, coupled field analysis is carried out to optimize the dimensions of the actuator with respect to the output force and input voltage. A cavity with a square diaphragm of 1mm×1mm×5μm is realized using standard microfabrication technique. 50μm thick PVDF film, cut with special dicing saw, is glued inside the metalized cavity using low stress, conductive, room temperature cured epoxy. The 3mm×3mm×0.675mm actuator die is packaged using Chip-On-Board technique in conjunction with low temperature soldering for taking the connections. The micro-actuator is tested in both actuation and sensing mode. The developed actuator is proposed to use with micro nozzle to study the utilization in drug delivery system.

Microstructure and tensile properties of consolidated magnesium chips

In this study tensile properties of consolidated magnesium chips obtained from solid state re-cycling (SSR) has been examined and correlated with the microstructure. Chips machined from as-cast billet of pure magnesium were consolidated through SSR technique, comprising of compaction at ambient conditions followed by hot extrusion at four different temperatures viz., 250, 300, 350 and 400 degrees C. The extruded rods were characterized for microstructure and their room temperature tensile properties. Both ultimate tensile strength and 0.2% proof stress of these consolidated materials are higher by 15-35% compared to reference material (as cast and extruded). Further these materials obey Hall-Petch relation with respect to strength dependence of grain size. Strain hardening behavior, measured in terms of hardening exponent, hardening capacity and hardening rate was found to be distinctly different in chip consolidated material compared to reference material. Strength asymmetry, measured as a ratio of compressive proof stress to tensile proof stress was higher in chip consolidated material. (C) 2012 Elsevier B.V. All rights reserved.

Process control of cantilever deflection for sensor application based on optical waveguides

This paper reports on the fabrication of cantilever silicon-on-insulator (SOI) optical waveguides and presents solutions to the challenges of using a very thin 260-nm active silicon layer in the SOI structure to enable single-transverse-mode operation of the waveguide with minimal optical transmission losses. In particular, to ameliorate the anchor effect caused by the mean stress difference between the active silicon layer and buried oxide layer, a cantilever flattening process based on Ar plasma treatment is developed and presented. Vertical deflections of 0.5 mu m for 70-mu m-long cantilevers are mitigated to within few nanometers. Experimental investigations of cantilever mechanical resonance characteristics confirm the absence of significant detrimental side effects. Optical and mechanical modeling is extensively used to supplement experimental observations. This approach can satisfy the requirements for on-chip simultaneous readout of many integrated cantilever sensors in which the displacement or resonant frequency changes induced by analyte absorption are measured using an optical-waveguide-based division multiplexed system.

Experimental Studies on the Kinematics of Cutting in Granular Materials

Slow flow in granular materials is characterized by high solid fraction and sustained inter-particle interaction. The kinematics of trawling or cutting is encountered in processes such as locomotion of organisms in sand; trawl gear movement on a soil deposit; plow movement; movement of rovers, earth moving equipment etc. Additionally, this configuration is very akin to shallow drilling configuration encountered in the mining and petroleum industries. An experimental study has been made in order to understand velocity and deformation fields in cutting of a model rounded sand. Under nominal plane strain conditions, sand is subjected to orthogonal cutting at different tool-rake angles. High-resolution optical images of the region of cutting were obtained during the flow of the granular ensemble around the tool. Interesting kinematics underlying the formation of a chip and the evolution of the deformation field is seen in these experiments. These images are also analyzed using a PIV algorithm and detailed information of the deformation parameters such as velocity, strain rate and volume change is obtained.

Stable hybrid containing haploid genomes of two obligate diploid Candida species

Candida albicans and Candida dubliniensis are diploid, predominantly asexual human-pathogenic yeasts. In this study, we constructed tetraploid (4n) strains of C. albicans of the same or different lineages by spheroplast fusion. Induction of chromosome loss in the tetraploid C. albicans generated diploid or near-diploid progeny strains but did not produce any haploid progeny. We also constructed stable heterotetraploid somatic hybrid strains (2n + 2n) of C. albicans and C. dubliniensis by spheroplast fusion. Heterodiploid (n + n) progeny hybrids were obtained after inducing chromosome loss in a stable heterotetraploid hybrid. To identify a subset of hybrid heterodiploid progeny strains carrying at least one copy of all chromosomes of both species, unique centromere sequences of various chromosomes of each species were used as markers in PCR analysis. The reduction of chromosome content was confirmed by a comparative genome hybridization (CGH) assay. The hybrid strains were found to be stably propagated. Chromatin immunoprecipitation (ChIP) assays with antibodies against centromere-specific histones (C. albicans Cse4/C. dubliniensis Cse4) revealed that the centromere identity of chromosomes of each species is maintained in the hybrid genomes of the heterotetraploid and heterodiploid strains. Thus, our results suggest that the diploid genome content is not obligatory for the survival of either C. albicans or C. dubliniensis. In keeping with the recent discovery of the existence of haploid C. albicans strains, the heterodiploid strains of our study can be excellent tools for further species-specific genome elimination, yielding true haploid progeny of C. albicans or C. dubliniensis in future.

Traffic engineered NoC for streaming applications

Streaming applications demand hard bandwidth and throughput guarantees in a multiprocessor environment amidst resource competing processes. We present a Label Switching based Network-on-Chip (LS-NoC) motivated by throughput guarantees offered by bandwidth reservation. Label switching is a packet relaying technique in which individual packets carry route information in the form of labels. A centralized LS-NoC Management framework engineers traffic into Quality of Service (QoS) guaranteed routes. LS-NoC caters to the requirements of streaming applications where communication channels are fixed over the lifetime of the application. The proposed NoC framework inherently supports heterogeneous and ad hoc system-on-chips. The LS-NoC can be used in conjunction with conventional best effort NoC as a QoS guaranteed communication network or as a replacement to the conventional NoC. A multicast, broadcast capable label switched router for the LS-NoC has been designed. A 5 port, 256 bit data bus, 4 bit label router occupies 0.431 mm(2) in 130 nm and delivers peak bandwidth of 80 Gbits/s per link at 312.5 MHz. Bandwidth and latency guarantees of LS-NoC have been demonstrated on traffic from example streaming applications and on constant and variable bit rate traffic patterns. LS-NoC was found to have a competitive AreaxPower/Throughput figure of merit with state-of-the-art NoCs providing QoS. Circuit switching with link sharing abilities and support for asynchronous operation make LS-NoC a desirable choice for QoS servicing in chip multiprocessors. (C) 2013 Elsevier B.V. All rights reserved.

TCP: thread contention predictor for parallel programs

With proliferation of chip multicores (CMPs) on desktops and embedded platforms, multi-threaded programs have become ubiquitous. Existence of multiple threads may cause resource contention, such as, in on-chip shared cache and interconnects, depending upon how they access resources. Hence, we propose a tool - Thread Contention Predictor (TCP) to help quantify the number of threads sharing data and their sharing pattern. We demonstrate its use to predict a more profitable shared, last level on-chip cache (LLC) access policy on CMPs. Our cache configuration predictor is 2.2 times faster compared to the cycle-accurate simulations. We also demonstrate its use for identifying hot data structures in a program which may cause performance degradation due to false data sharing. We fix layout of such data structures and show up-to 10% and 18% improvement in execution time and energy-delay product (EDP), respectively.

A power-scalable RF CMOS receiver for 2.4 GHz Wireless Sensor Network applications

A power scalable receiver architecture is presented for low data rate Wireless Sensor Network (WSN) applications in 130nm RF-CMOS technology. Power scalable receiver is motivated by the ability to leverage lower run-time performance requirement to save power. The proposed receiver is able to switch power settings based on available signal and interference levels while maintaining requisite BER. The Low-IF receiver consists of Variable Noise and Linearity LNA, IQ Mixers, VGA, Variable Order Complex Bandpass Filter and Variable Gain and Bandwidth Amplifier (VGBWA) capable of driving variable sampling rate ADC. Various blocks have independent power scaling controls depending on their noise, gain and interference rejection (IR) requirements. The receiver is designed for constant envelope QPSK-type modulation with 2.4GHz RF input, 3MHz IF and 2MHz bandwidth. The chip operates at 1V Vdd with current scalable from 4.5mA to 1.3mA and chip area of 0.65mm2.

System-level SoC near-field (NF) emissions: Simulation to measurement correlation

As System-on-Chip (SoC) designs migrate to 28nm process node and beyond, the electromagnetic (EM) co-interactions of the Chip-Package-Printed Circuit Board (PCB) becomes critical and require accurate and efficient characterization and verification. In this paper a fast, scalable, and parallelized boundary element based integral EM solutions to Maxwell equations is presented. The accuracy of the full-wave formulation, for complete EM characterization, has been validated on both canonical structures and real-world 3-D system (viz. Chip + Package + PCB). Good correlation between numerical simulation and measurement has been achieved. A few examples of the applicability of the formulation to high speed digital and analog serial interfaces on a 45nm SoC are also presented.

Time-Based All-Digital Technique for Analog Built-in Self-Test

A scheme for built-in self-test of analog signals with minimal area overhead for measuring on-chip voltages in an all-digital manner is presented. The method is well suited for a distributed architecture, where the routing of analog signals over long paths is minimized. A clock is routed serially to the sampling heads placed at the nodes of analog test voltages. This sampling head present at each test node, which consists of a pair of delay cells and a pair of flip-flops, locally converts the test voltage to a skew between a pair of subsampled signals, thus giving rise to as many subsampled signal pairs as the number of nodes. To measure a certain analog voltage, the corresponding subsampled signal pair is fed to a delay measurement unit to measure the skew between this pair. The concept is validated by designing a test chip in a UMC 130-nm CMOS process. Sub-millivolt accuracy for static signals is demonstrated for a measurement time of a few seconds, and an effective number of bits of 5.29 is demonstrated for low-bandwidth signals in the absence of sample-and-hold circuitry.